JPH0172628U - - Google Patents

Description

[Brief explanation of the drawing]

Figure 1 is a block diagram of a waveform generator which is an embodiment of this invention, and Figure 2 is a waveform memory 1 shown in Figure 1.
FIG. 3 is a diagram showing an example of how the sequence memory 17 of FIG. 1 is programmed.
FIG. 4 is a block diagram of a conventional waveform generator.

Claims (1)

[Claims for Utility Model Registration] A. A waveform memory in which digital values of a plurality of waveforms are divided and stored in each address, and a portion of each address is used as a control signal storage means; B. A waveform memory that is output from the waveform memory. A DA converter that converts a digital signal into an analog signal; C a sequence memory in which the start address and loop count of the waveform output from the waveform memory are sequentially stored; and D a start address that is output from the sequence memory. E. The start address stored in the address register is set, and the start address is incremented every time a DA conversion clock signal is supplied, and the above waveform is set using this incremented value as an address signal. an address counter supplied to the memory; a loop counter that sets a start address in the address counter; H) a control circuit that generates a control clock signal; and a counter that counts the control clock signal generated from the control circuit and supplies the counted value to the sequence memory as an address signal. waveform generator.