JP3235676B2 - Arbitrary waveform generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitrary waveform generator, and more particularly to an arbitrary waveform generator that generates an arbitrary waveform by a D / A converter based on waveform data stored in a digital data memory.

[0002]

2. Description of the Related Art A conventional example of an arbitrary waveform generator for generating an arbitrary waveform by a D / A converter based on waveform data stored in a digital data memory will be described with reference to FIG. 1 is a digital data memory, 2 is D
/ A converter. This digital data memory 1
Is sent to the D / A converter 2 at a predetermined clock cycle, where it is converted into an analog signal.

In this case, the accuracy of the converted analog waveform is determined by the resolution of the D / A converter 2, and the rate of change of the analog waveform is determined by the clock cycle of the D / A converter 2.

[0004]

As described above, in order to generate a higher-precision analog waveform at a higher speed, a D / A converter operating at a high resolution and at a high speed is required. The present invention provides a high-resolution, high-speed arbitrary waveform that generates a high-resolution, high-operation speed arbitrary waveform by using a low-resolution, low-operation speed D / A converter. A waveform generator is provided.

[0005]

A memory 11 for storing waveform data, a differentiator 12 for differentiating the waveform data stored in the memory 11, and a distributor for selectively outputting the differential data output from the differentiator 12 at regular intervals. 13 and the memory unit 1
0, and a D / A converter 20 including an integrator 21 for integrating the differential data selectively output by the distributor 13 and a D / A converter 22 for D / A converting the output of the integrator 21. A memory unit 10 and a D / A conversion unit 2
An arbitrary waveform generator comprising a timing generator 30 for giving a timing signal to 0 and an analog adder 40 for adding the result of D / A conversion by each D / A converter 20; A memory unit 10 comprising a memory 11 for storing data obtained by pre-differentiating the waveform data and a distributor 13 for selectively outputting the differentiated data output from the memory 11 at regular intervals. Integrator 21 and integrator 2 for integrating the differential data, respectively
A plurality of D / A converters 20 each including a D / A converter 22 for D / A converting the output of the D / A 1 are provided.
An arbitrary waveform generator comprising a timing generator 30 for providing a timing signal to the A / A converter 20 and an analog adder 40 for adding the result of D / A conversion by each D / A converter 20 The D / A converter 20 includes a D / A converter 22 for D / A converting the differential data selected and output by the distributor 13 and an integrator 21 for integrating the output.
And a memory unit 10 for differentiating the waveform data and selectively storing the results of selectively integrating the differentiated data at regular intervals. The memory units 10 separately store the results. A plurality of D / A conversion units 20 for respectively D / A converting data stored in the memory unit 10 and a D / A conversion unit.
An arbitrary waveform generator including a timing generator 30 for providing a timing signal to the A / A converter 20 and an analog adder 40 for adding the result of D / A conversion by each D / A converter 20 is also provided. Configured.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to FIG. A first embodiment of the arbitrary waveform generator of the present invention is as follows.
It comprises a memory unit 10, a plurality of, for example, four-phase D / A conversion units 20, a timing generator 30, and an analog adder 40. The memory unit 10 includes a waveform data memory 11 storing waveform data, a differentiator 12 for differentiating the waveform data stored in the memory 11, and a distributor 13 for distributing and outputting the output of the differentiator 12. Each of the D / A converters 20 includes an integrator 21 and a D / A converter 22 for adding and integrating the output of the differentiator 12 distributed and supplied via the distributor 13. That is, the memory 11 for storing waveform data and the memory 1
The memory unit 10 includes a differentiator 12 for differentiating the waveform data stored in 1 and a distributor 13 for selectively outputting the differentiated data output from the differentiator 12 at regular intervals. Integrator 21 for integrating differential data respectively and D / A for D / A converting the output of integrator 21
A plurality of D / A converters 20 each including an A / A converter 22; a timing generator 30 for providing a timing signal to the memory unit 10 and the D / A converter 20; , An arbitrary waveform generator including an analog adder 40 for adding the result of the D / A conversion.

Here, the input / output of each unit will be described with reference to FIG. The output of the differentiator 12 obtained by differentiating the waveform data stored in the memory 11 by the operation timing of the memory unit includes a ₁ , b ₁ c ₁ , d ₁ , a ₂ , b ₂ , including the sign.
c ₂ ,... That is, arrows a ₁ and b ₁
.., c ₁ , d ₁ , a ₂ , b ₂ , c ₂ ,... are differential data obtained by differentiating the output of the waveform data memory 11 by the differentiator 12. These differential data is input shown as being, to sequentially free the D / A converter 20 _A via the distributor 13 to 20 _D in FIG. 3 (b) by operation timing shown in FIG. 3 (d) . In FIG. 3B, A is D /
Shows the differential data inputted to A converter 20 _A, B is D
/ A converter indicates the differential data input to the 20 _B, which is the same for the following C and D.

FIG. 3C shows the result of cumulative addition of the differential data input to the D / A converter 20 in the integrator 21 at the operation timing shown in FIG. 3D, and outputs the result of the D / A conversion. Show. The operation timing of D / A conversion is as follows.
The timing at which the A conversion units 20 are sequentially executed at equal intervals is set. This interval is equal to the operation timing interval of the memory unit. Here, A is shows the output waveform of the D / A converter 20 _A, B shows the output waveform of the D / A converter unit 20 _B, the following C
The same applies to D and D.

The analog data successively D / A-converted by the four-phase D / A converters 20 _A to 20 _D are finally added in an analog adder 40 and are added as shown in FIG. The desired analog waveform is obtained. A second embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the first embodiment in which the integrator 21 in the D / A converter 20 is connected after the D / A converter 22. That is, the data sequentially distributed via the distributor 13 is first D / A-converted by the D / A converter 22, and the data converted here into an analog signal by the integrator 21 is converted into an analog adder 40. In this case, an additional configuration is adopted.

A third embodiment of the present invention will be described with reference to FIG. This embodiment corresponds to the first embodiment in which the memory unit 10 does not include the differentiator 12. Differentiator 1
Instead, the data obtained by differentiating the waveform data is stored in the memory in advance, and the stored differential data is stored in the D / A converter 20 via the distributor 13 as in the first embodiment. This is to sequentially distribute and supply to each integrator 21.

A fourth embodiment of the present invention will be described with reference to FIG. This embodiment is different from the third embodiment in that the differentiator 12 and the distributor 13 and the integrator 21 are not included. The waveform data stored in the memory 11 is differentiated, and the result obtained by adding the differentiated data in the integrator 21 is stored in the memory separately. The data stored in the memory for each D / A converter 22 corresponding to each data
, And adds the result in the analog adder 40.

[0012]

As described above, FIGS. 4, 5 and
FIG. 6 shows a waveform generation system when a four-phase D / A converter is employed.
The result of the simulation is shown. FIG. 4 and FIG.3
FIG. 6 is a diagram corresponding to FIG.3Corresponding to (a)
FIG. FIGS. 4A and 4B show D / A, respectively.
Conversion unit 20_AAnd 20_B5 (c) and FIG.
And (d) respectively show the D / A converter 20_CAnd 20_D
FIG. 6 shows the output of the D / A converter 20._ANot
20_D5 shows a waveform finally obtained by adding the output of FIG. Each D
The change rate of the A / A converter is the change rate of the waveform finally obtained.
It is clear that the amplitude may be almost 1/4.
You. After all, these are sequentially used by using a plurality of D / A conversion units.
, The operating speed of each D / A converter is
The rate of change of the waveform can be increased without increasing.
The maximum amplitude of the analog signal after addition is determined by each D / A conversion.
Resolution is also improved because the sum of the maximum amplitudes
You.

[Brief description of the drawings]

FIG. 1 is a diagram showing a conventional example of an arbitrary waveform generator.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating input / output data of a D / A converter according to the embodiment of the present invention.

4A and 4B are diagrams showing waveform generation simulation results, wherein FIGS. 4A and 4B each show a D / A conversion unit 20 _A;
And the output of 20 _B.

FIGS. 5A and 5B are graphs showing waveform generation simulation results. FIGS. 5C and 5D respectively show a D / A converter 20 _C.
And shows the output of 20 _D.

[Figure 6] is a diagram showing a waveform generation simulation result shows the final seek waveform plus output of from the D / A converter 20 _A 20 _D.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Memory part 11 Memory 12 Differentiator 13 Distributor 20 D / A conversion part 21 Integrator 22 D / A converter 30 Timing generator 40 Analog adder

Claims (3)

(57) [Claims] A memory for storing waveform data; and a memory for storing waveform data stored in the memory as an operation timing of the memory unit.
A differentiator to more differentiated, the n (n periods of the differential data the operation timing output by the differentiator is 2 or more integer
Number) includes the memory unit further comprising a distributor for sequentially output to the D / A converter unit in each cycle times, an integrator for integrating each of differential data is selectively outputted by the divider, the integrator the output Ri more a D / a converter for converting D / a, the n times the output of the integrator
The D / A converter for D / A conversion to the n provided for each cycle of, comprising a timing generator providing the operation Timing <br/> ring signal and the memory unit and each of the D / A converter unit arbitrary waveform generator, characterized in that, and comprises an analog adder for additive a result of the D / a conversion by the above D / a conversion unit. 2. The arbitrary waveform generator according to claim 1, wherein the D / A converter is a D / A converter for D / A converting differential data selectively output by the distributor, and integrates the output. An arbitrary waveform generator comprising an integrator. 3. A memory for storing pre-differentiated data waveform data, the operation timing of the memory portion of the memory
Cycle of the operation timing of the differential data output by
D / A conversion every n times (n is an integer of 2 or more) times
Comprising the memory unit further comprising a distributor which outputs the section, the integrator and, D / A converter for the D / A conversion output of the integrator for integrating each of differential data is selectively outputted by the divider When Ri more formed, the n times the output of the integrator
The D / A converter for D / A conversion to the n provided for each cycle of, comprising a timing generator providing the operation Timing <br/> ring signal and the memory unit and each of the D / A converter unit arbitrary waveform generator, characterized in that, and comprises an analog adder for additive a result of the D / a conversion by the above D / a conversion unit.