JP2949349B2 - Pulse width modulation circuit - Google Patents

Description

The present invention relates to a pulse width modulation circuit, and more particularly, to a pulse width modulation circuit.
The present invention relates to a pulse width modulation circuit suitable for use at a high frequency.

BACKGROUND OF THE INVENTION A so-called pulse width modulation circuit is used in various fields. For example, it is mainly used for controlling a motor, reproducing halftone of a laser printer, and the like. Of these, the motor control has a relatively low frequency and is easy to control. In addition, there is no problem because a dedicated pulse width modulation IC is also provided.

However, laser printers use a high frequency, and there is no dedicated IC for pulse width modulation. Therefore, it was constituted by discrete.

FIG. 3 is a configuration diagram showing a configuration example of the pulse width modulation circuit configured as described above. In the figure, reference numeral 1 denotes a triangular wave generating circuit for generating a triangular wave based on a data clock supplied from outside, 2 a D / A converter for converting a digital data input to an analog signal based on the data clock, 3
Is a comparator that generates a PWM signal with a controlled pulse width by comparing a triangular wave from the triangular wave generation circuit 1 with an analog signal from the D / A converter 2.

FIG. 4 is a waveform diagram showing signal waveforms at various parts in the operating state of the above-described pulse width modulation circuit.

Data clock provided externally (FIG. 4 (a))
Accordingly, the transistor Tr1 in the triangular wave generation circuit 1 repeats on / off. In synchronization with the repetition of ON / OFF of Tr1, the capacitor C1 repeats discharging / charging. This discharge / charge of C1 generates a triangular wave voltage.
Since the charging and discharging of C1 is performed via the variable resistor VR1, the peak value of the triangular wave is adjusted by VR1. This triangular wave is current-amplified by the transistor Tr2 and output to the outside via the capacitor C2 (FIG. 4 (b)). The DC offset of this triangular wave is adjusted by a variable resistor VR2 whose both ends are connected to + and-of the power supply.

On the other hand, the analog signal (FIG. 4 (c)) generated from the digital data input by the D / A converter 2 and the above-described triangular wave (FIG. 4 (b)) are compared by the comparator 3, and the PWM signal is output.
A signal (FIG. 4 (d)) is obtained.

(Problems to be Solved by the Invention) In the circuit configuration shown in FIG. 3, if noise is mixed into a triangular wave (FIG. 4b) or an analog signal (FIG. 4 (c)),
The pulse width signal, which is the comparison result, also changes easily. Therefore, degradation of accuracy due to analog processing, D / A
There is a problem that the converter is expensive. In particular, since the comparison is performed at the analog level, there is a difficulty in stabilizing the accuracy.

Digitization of this requires a high-frequency clock having a higher frequency than the data clock, which is difficult to realize.

The present invention has been made in view of the above-described problems, and an object of the present invention is to provide a pulse width modulation circuit capable of controlling a pulse width with higher precision than a method of comparing by analog, using a digital system. Therefore, the present invention is realized with a simpler configuration.

(Means for Solving the Problems) According to the present invention for solving the above problems, there are provided delay means for generating a plurality of delay signals having different delay times from a reference clock signal, and decoding of input digital data of a plurality of bits. A decoder for outputting code data, a selector for selectively passing one of the plurality of delay signals corresponding to the code data output from the decoder, and a delay signal passing through the selector. And a logic gate means for gating the clock signal and a clock signal, and a signal having a pulse width corresponding to the input digital data of a plurality of bits is obtained.

(Operation) In the pulse width modulation circuit of the present invention, of the plurality of delay signals generated by the delay means, only the signal corresponding to the digital data input passes through the selection means, and the delay signal and the clock having passed through the selection means The signal is gated by the logic gate means. As a result, a signal having a pulse width corresponding to the digital data input is generated.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, the outline of the pulse width modulation circuit of the present invention will be described with reference to the block diagram of FIG. In this figure,
Reference numeral 10 denotes a flip-flop that receives a data clock and outputs a clock having a frequency of 1/2. Reference numeral 11 denotes a delay line which receives the Q output of the flip-flop 10 and outputs a plurality of delayed signals having different delay times (hereinafter referred to as delay signals). In this embodiment, 64 elements (DL-
1 to DL-64). The delay line 11 may be a single element having a plurality of output taps or a cascade connection of a plurality of delay elements. Further, a fixed delay of a logic IC, a buffer or the like or a fixed delay of one gate in a gate array may be used. Reference numeral 12 denotes a decoder which receives a 6-bit digital data input and any one of 64 outputs (0 to 63) sequentially becomes a low level. A selection circuit 13 selectively passes the delay output of the delay line 11 in accordance with the output of the decoder 12. This selection circuit 13 has 64
Delay gates with different phases from the delay line 11.
13 is connected to one end of an OR gate. The output of the decoder 12 is connected to the other end of each OR gate. An exclusive OR (ExOR) gate 14 receives the output of the flip-flop 10 and the output of the selection circuit 13 and takes an exclusive OR.

FIG. 2 is a time chart for explaining the present embodiment.

Hereinafter, the operation of the present embodiment will be described with reference to FIG. 1 and FIG.

Data clock frequency is set by flip-flop 10.
Converted to 1/2 clock. This flip flop 1
A Q output of 0 (FIG. 2 (a)) is supplied to the delay line 10, and 64 types of delayed signals having different delay times are output (FIGS. 2 (b) to 2 (e)).

On the other hand, the output of the decoder 12 corresponds to a 6-bit digital data input, and only one of 0 to 63 is output.
L and others are H. Table 1 shows the relationship between the input and output.

Therefore, as for the output of each OR gate of the selection circuit 13, the delay signal from the delay line 11 appears only at the point where the output of the decoder 13 is L. The output of the OR gate where the output of the decoder 12 is H is fixed at H level.

Since the outputs of these OR gates are connected together to one input of the exclusive OR gate 14, the decoder
This is equivalent to selecting and outputting only the output of the OR gate at the position where the output of 12 is L.

Then, the exclusive OR gate 14 takes the exclusive OR of the delay signal selected by the selection circuit 13 and the output of the flip-flop 10. As a result, a signal appears on the output side of the exclusive OR gate 14 in which the two inputs are L when they match and H when they do not match. Since one input (delay signal) of the exclusive OR gate 14 changes according to the selection result, the output signal of the exclusive OR gate 14 has a variable pulse width, that is, a PWM signal.
Signal. Note that the PWM signal shown in FIG.
-3 (FIG. 2 (d)) is selected.
Therefore, in this embodiment, depending on which delay signal is selected,
It is possible to freely change the low-level pulse width of the PWM signal in 64 steps.

As described above, according to this embodiment, an expensive D / A converter is not required, and cost reduction can be achieved. In addition, since analog processing is not performed, it is resistant to noise, and there is no need to reduce accuracy. Unlike ordinary digital processing, a clock higher in frequency than the dot clock is not required, and the circuit configuration is simple. Further, each component used in this embodiment is suitable for integration, and the circuit can be made compact.

In the above embodiment, the case where the pulse width is changed in 64 steps has been described, but the present invention is not limited to this. In other words, while the basic circuit configuration remains the same as in the present embodiment, the desired pulse can be obtained only by modifying the number of taps (or the number of elements) of the delay line, the number of OR gates of the selection circuit, and the processing capability of the decoder as necessary. The rate of change of the width is obtained.

In the present embodiment, the description has been made using the selection circuit formed of an OR gate as the selection means and the exclusive OR gate as the logic gate means for gating the selected delay signal and the clock. It is not limited. That is, the same operation can be performed using other types of logic gates.

(Effects of the Invention) As described in detail above, according to the present invention, of the plurality of delay signals generated by the delay means, only the signal corresponding to the digital data input is selected, and the selected delay signal and clock signal are selected. Gating. As a result,
A signal having a pulse width corresponding to the digital data input is generated. Therefore, a pulse width modulation circuit capable of controlling the pulse width with higher accuracy than the analog comparison method can be realized with a simple configuration by a digital method.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of this embodiment, and FIG.
FIG. 1 is a configuration diagram showing a configuration example of a conventional pulse width modulation circuit, and FIG. 4 is a waveform diagram in an operation state of the conventional pulse width modulation circuit. 10: flip-flop 11: delay line 12: decoder, 13: selection circuit 14: exclusive OR gate

────────────────────────────────────────────────── (5) References JP-A-61-240715 (JP, A) U.S. Pat. No. 4,486,861 (US, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H03K 7 / 08

Claims (1)

(57) [Claims] A delay means for generating a plurality of delay signals having different delay times from a reference clock signal; a decoder for decoding input digital data of a plurality of bits and outputting code data; Selecting means for selectively passing one delayed signal corresponding to the code data output from the decoder among the signals; and logic gate means for gating the delayed signal and the clock signal passed through the selecting means. A pulse width modulation circuit for a printer, comprising: obtaining a signal having a pulse width corresponding to the input digital data of a plurality of bits.