JPH0326016A - Pulse width modulation circuit - Google Patents

Abstract

PURPOSE:To control the pulse width high accuracy by selection only a signal among plural delay signal in response to a digital data input, and gating a selected delay signal and a clock signal. CONSTITUTION:A data clock is converted into a clock whose frequency is 1/2 by a flip-flop 10, a Q output of the flip-flop 10 is fed to a delay line 11 and 64 kinds of different delay signals from delay times are outputted. Any of 0- 63 of outputs of a decoder 12 is at an L and others are at H corresponding to the 6-bit digital data. Thus, a delay signal from the delay line 11 appears at an output when an output of the decoder 12 is at an L level at the output of each OR gate of a selection circuit. Then an exclusive OR gate 14 takes exclusive OR between the delay signal selected by the selection circuit 13 and an inverse of Q output of the flip-flop 10 and its output signal is a signal whose pulse width is variable. Thus, the pulse width is controlled with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a pulse width modulation circuit, and more particularly to a pulse width modulation circuit suitable for use at high frequencies.

(Background of the Invention) So-called pulse width modulation circuits are used in various fields. 'For example, its main uses include motor control and halftone reproduction for laser printers. Among these, motor control has a relatively low frequency and is easy to control. In addition, a dedicated pulse width modulation IC is also available, so there is no problem.

However, laser printers use high frequencies,
A dedicated IC for pulse width modulation is also not available. Therefore, it was made up of discrete components.

FIG. 3 is a structural diagram showing an example of the configuration of the pulse width modulation circuit configured as described above. In the figure, 1 is a triangular wave generation circuit that generates a triangular wave based on an externally applied data clock, 2 is a D/A converter that converts digital data input into an analog signal based on the data clock, and 3
is a combiner that generates a PWM signal whose pulse width is controlled by comparing the triangular wave from the triangular wave generating circuit 1 and the analog signal from the D/A converter 2.

Moreover, FIG. 4 is a waveform diagram showing signal waveforms of various parts in the operating state of the above-mentioned pulse width modulation circuit.

The transistor Tri in the triangular wave generation circuit 1 repeats on/off in accordance with the data clock (FIG. 4(a)) applied from the outside. In synchronization with this repeated on/off of Tr1, the capacitor C1 repeats discharging/charging. A triangular wave voltage is generated by discharging/charging the CI. Note that since charging and discharging of C1 is via the variable resistor VR1, the peak value of the triangular wave is adjusted by this VRI. This triangular wave is current-amplified by the transistor Tr2 and output to the outside via the capacitor C2 (FIG. 4(b)). Incidentally, this triangular wave is subjected to DC offset adjustment by a variable resistor VR2 whose both ends are connected to + and - of the power supply.

On the other hand, the analog signal (Fig. 4 (C)) generated manually by the digital data in the D/A converter 2 and the above-mentioned triangular wave (
Fig. 4(b)) is compared with the converter 3, and the PWM
A signal (FIG. 4(d)) is obtained.

(Problem to be Solved by the Invention) In the circuit structure shown in Fig. 3, if noise is mixed into the triangular wave (Fig. 4b) or the analog signal (Fig. 4(C)), the pulse width as a comparison result The signal also changes easily. Therefore,
Deterioration of accuracy due to analog processing, D/A
There are problems such as the converter is expensive. In particular, since comparisons are made at an analog level, there is a problem in stabilizing accuracy.

Digitizing this requires a high frequency clock with a higher frequency than the data clock, which is difficult to achieve.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a pulse width modulation circuit using a digital method, which is capable of controlling pulse widths with higher precision than analog comparison methods. The purpose is to realize this with a simpler structure.

(Means for Solving the Problems) The present invention to solve the above problems includes: a delay means for generating a plurality of delay signals having different delay times from a reference clock signal; a decoder for decoding digital data input; It has a selection means for selectively passing the delayed signal from the delay means based on the output of the decoder, and a logic gate means for gating the delayed signal passed through the selection means and the clock signal. It is characterized by obtaining a signal with a pulse width that corresponds to the data input.

(Function) In the pulse width modulation circuit of the present invention, among the plurality of delayed signals generated by the delay means, only the one corresponding to the digital data input passes through the selection means, and the delayed signal that has passed through the selection means is The clock signal is gated by logic gate means.

As a result, a signal with a pulse width corresponding to the digital data input is produced.

(Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, the outline of the pulse width modulation circuit of the present invention will be explained with reference to the block diagram of FIG. In this figure, 1
0 is a flip-flop that receives a data clock and outputs a clock with a frequency of 172. 11 is flip
This is a delay line that receives the Q output of the flop 10 and outputs a plurality of delayed signals (hereinafter referred to as delayed signals) having different delay times. Note that this embodiment will be described as having 64 elements (DL-1-DI, -64).

Also, this delay line 1]. may be a single element having a plurality of output taps or a plurality of delay elements connected in cascade. Furthermore, logic IC
, a fixed delay of a buffer or the like or a fixed delay of one gate in a gate array may be used. 1
2 is a decoder which receives 6-bit digital data input, and one of 64 outputs (0 to 63) becomes low level sequentially. Reference numeral 13 denotes a selection circuit that selectively passes the delayed output of the delay line 11 based on the output of the decoder 12. This selection circuit 13 is composed of 64 OR gates, and delay signals having different phases from the delay line 11 are connected to one end of each OR gate constituting the selection circuit 13. Further, the output of the decoder 12 is connected to the other end of each OR gate. 14 is an exclusive OR (Ex OR) gate which receives the Q output of the flip◆flop 10 and the output of the selection circuit 13 and calculates an exclusive OR.

FIG. 2 is a time chart for explaining this embodiment.

The operation of this embodiment will be explained below with reference to FIGS. 1 and 2.

The data clock is converted by a flip-flop 10 into a clock with a frequency of 1/2. The Q output of this flip-flop 10 (Fig. 2(a)) is the delay line 10.
2, and 64 types of delay signals with different delay times are output (FIG. 2(b) to FIG. 2(e)).

On the other hand, as for the output of the decoder 12, only one of 0 to 63 is L and the others are H, corresponding to the 6-bit digital data input. Table 1 shows this input/output relationship.

Therefore, the output of each OR game 1 of the selection circuit 13 is output from the delay line 1 only at the point where the output of the decoder 13 is L.
A delayed signal from 1 appears. The output of decoder 12 is H
The output of the OR gate at a certain location is fixed at H level.

Table 1 Note that the outputs of these OR gates are connected together to one input of the exclusive OR gate 14, so only the outputs of the OR gates where the output of the decoder 12 is L are selected and output. It is equivalent to being present.

Then, the exclusive OR gate 14 takes the exclusive OR of the delayed signal selected by the selection circuit 13 and the Q output of the flip-flop 10. As a result, exclusive OR gate 14
A signal appears on the output side of , which becomes L when the two inputs match and becomes H when they do not match.

Since one input (delayed signal) of the exclusive OR gate 14 changes depending on the selection result, the output signal of the exclusive OR gate 14 is a signal with variable pulse width. In other words, it becomes a PWM signal. Incidentally, the PWM signal shown in FIG. 2(g) is DL
-3 (Fig. 2(d)) is selected. Therefore, in this embodiment, the low-level pulse width of the PWM signal can be freely changed in 64 steps by selecting which delay signal.

As explained above, according to this embodiment, an expensive D/A converter is not required, and costs can be reduced.

Furthermore, since analog processing is not performed, it is resistant to noise and there is no need to worry about deterioration in consistency. Unlike normal digital processing, a clock with a higher frequency than the dot clock is not required, and the circuit structure is simple. Furthermore, each component used in this example is suitable for integration, and it is also possible to make the circuit compact.

Incidentally, in the above embodiment, a case has been described in which the pulse width is changed in 64 steps, but the invention is not limited to this. In other words, the desired configuration can be obtained by simply changing the number of taps (or number of elements) of the delay line, the number of OR gates of the selection circuit, and the processing capacity of the decoder as necessary, while keeping the basic circuit configuration the same as in this embodiment. The rate of change of pulse width is obtained.

Furthermore, in this embodiment, the selection circuit consisting of an OR gate is used as the selection means, and the exclusive OR gate is used as the logic gate means for gating the selected delay signal and the clock. It is not limited. That is, it is also possible to perform similar operations using other types of logic gates.

(Effects of the Invention) As explained in detail above, in the present invention, only one of the plurality of delayed signals generated by the delay means is selected according to the digital data input, and the selected delayed signal and clock signal are I started gating the . As a result, a signal having a pulse width corresponding to the digital data input is generated. Therefore, compared to an analog comparison method, a pulse width modulation circuit that can control the pulse width with high precision can be realized with a digital method and a simpler configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a time chart for explaining the operation of this embodiment, and FIG.
FIG. 4 is a structural diagram showing an example of the structure of a conventional pulse width modulation circuit, and FIG. 4 is a waveform diagram of the conventional pulse width modulation circuit in an operating state. 10... Flip-flop 11... Delay line 12... Decoder 13... Selection circuit 14.
・Exclusive OR gate

Claims (1)

[Scope of Claims] Delay means for generating a plurality of delayed signals with different delay times from a reference clock signal, a decoder for decoding digital data input, and a delay from the delay means based on the output of the decoder. It has a selection means for selectively passing a signal, and a logic gate means for gating the delayed signal and clock signal that have passed through the selection means, and obtains a signal with a pulse width corresponding to digital data input. Pulse width modulation circuit.