JPS63229917A - One-odd number frequency divider - Google Patents

Abstract

PURPOSE:To attain simple circuit constitution by providing an (n+1) (n is an odd number being 3 or over) counter, a control signal generating circuit obtaining a control signal from an output of (n+1)/2 count and a circuit switching the polarity of the clock signal of the count input. CONSTITUTION:A control signal generating circuit 13 generating a switching control signal by an output of a counter 12 and a clock switching circuit 11 switching the polarity of the clock signal given to the counter 12 by the control signal are provided. Then an output of inverse of Q2 of a FF circuit 23 becomes an input signal to a terminal D1 of the FF circuit 22 and the clock signal from the output section of the clock switching circuit 11 is given to a clock input section CLK of each FF circuit. A Q1 output signal of the FF circuit 22 and a Q2 output signal of the FR circuit 23 are given to the control circuit 13 and the control signal generated from the logic circuit 24 is fed to an exclusive OR circuit 21 via a delay circuit 25. Through the circuit constitution above, a one-odd number frequency is generated with accurate duty ratio of 50%.

Description

[Detailed Description of the Invention] [Summary] In a frequency divider that generates a signal divided by an odd number of clock signals, a switching control signal is created from the most significant bit output of the counter of the frequency divider, and this control signal is used to The clock switching circuit is controlled so that the counter can operate at the rising point of the leading edge of the clock signal and the falling point of the trailing edge, and a divided clock signal with a duty ratio of 50% is generated by controlling the selection of the operating point.

[Industrial application field]

The present invention relates to improvements in odd-number dividers.

When a clock signal with a duty ratio of 50% is input to a frequency divider and the frequency is divided to generate a divided clock signal of a desired frequency, the duty ratio may be 50% depending on the frequency division ratio.
It is not always possible to obtain a 0% clock signal.

However, depending on the use of the divided clock signal,
Since a clock with a 0% duty ratio is required, it is desirable to provide such a frequency divider circuit with a simple configuration.

[Conventional technology]

FIG. 6 shows a block circuit diagram of an example of a 1/3 frequency divider as a conventional 1/3 frequency divider.

The 1/3 frequency divider includes D flip-flops 1.2.3, a NAND circuit 4, and an OR circuit 5.

NAND circuit 4 is 0 of flip-flow knob circuit 1.2
1 and Q2, and the output signal is given as a D1 input signal of the flip-flop circuit 1.

The OR circuit 5 receives the flip-flop circuit 2 as an input signal.
It is given the 02 output signal of the flip-flop circuit 3 and the 03 output signal of the flip-flop circuit 3, and outputs a frequency-divided signal from its output section.

Each flip-flop circuit 1-3 is supplied with the same clock signal to its respective CLKI-CLK3 input.

Further, 02 of the flip-flop circuit 2 is given as a D3 human input signal of the flip-flop circuit 3.

FIG. 7 is an operational waveform diagram of each part of the circuit shown in FIG.

The frequency divider circuit is placed in an initial state for starting operation by the clear signal (ii).

In response to changes in the input clock signal, flip-flop 1.
2 is its output signal capability (iii) and Q2 is (iv)
, and also changes the output signal of the NAND circuit 4 to (V).

At this time, the 7th output part number of the flip-flop circuit 2 is (vi
), and this signal waveform has a one-cycle change for every three-cycle change of the clock signal (i), and has a frequency that is one-third of the input clock signal.

However, since the duty ratio of this output signal is not 50%, a flip-flop circuit 3 and an OR circuit 5 are provided to create a logical OR of the ■output (vi) of the flip-flop circuit 2 and the 03 output of the flip-flop circuit 3. , (viii
) with a duty ratio of 50%.

[Problem that the invention seeks to solve]

As mentioned above, the conventional 1/n frequency divider (1/n frequency divider)
The problem is that it is necessary to provide a frequency dividing circuit and a flip-flop circuit to set the duty ratio of the output signal to 50%, and the number of elements is large, making it difficult to form a simple circuit configuration.

[Means for solving problems]

As shown in the principle diagram of the present invention in FIG. 1, the present invention includes an n+l counter 12 (n is an odd number of 3 or more) having a flip-flop circuit, and a control signal from the (n+1)/2 count output of this counter. By providing a control signal generating circuit 13 to obtain the clock signal and a clock switching circuit 11 which switches the polarity of the clock signal input to the counter according to the control signal, an odd number divided frequency wave having a duty ratio of 50% and 1/n of the input clock signal can be generated. Problem solved.

[Effect]

In the present invention, the control signal generation circuit 13 provided at the output part of the n+1 counter 12 extracts a control signal when the counter counts (n+1)/2, supplies it as a control signal to control the clock switching circuit 11, and supplies it as a control signal to control the clock switching circuit 11. The switching circuit 11 is operated so that both the falling point and the rising point of the leading edge of the clock signal can be used selectively, and the polarity of the clock signal is changed and applied to the counter, and the duty ratio is 1/n of 50%. Generates an odd frequency divided wave.

〔Example〕

The present invention will be explained according to illustrated embodiments.

FIG. 2 is a block circuit diagram of a one-third frequency divider according to an embodiment of the present invention, and FIG. 3 is an operational waveform diagram of the circuit according to the embodiment of FIG.

The 1/3 frequency divider includes a 2-bit counter 12 including a flip-flop circuit connected in two stages, a control signal generation circuit 13 that generates a switching control signal based on the output of the counter 12, and a clock signal that is supplied to the counter by the control signal. A clock switching circuit 11 that switches polarity is provided.

The clock switching circuit 11 consists of an exclusive OR circuit 21, and the 2-bit counter 12 consists of 21 D flip-flop circuits 22 and 23.

The 02 output of the flip-flop circuit 23 is given to the 01 of the flip-flop circuit 22 as an input signal.

The clock signal obtained from the output section of the clock switching circuit 11 is applied to the clock input section CLK of each flip-flop circuit.
given to.

The control signal generation circuit 13 includes an AND circuit 24, and the 01 output signal of the flip-flop circuit 22 and the 02 output signal of the flip-flop circuit 23 are inputted thereto.

A control signal generated from the AND circuit 24 in response to these input signals is supplied to the exclusive OR circuit 2I via the delay circuit 25.

This supplied signal is the most significant bit of the counter 12.

As is clear from the operating waveform diagram in FIG. 3, the clock switching circuit 11 receives a clock signal (i) and a signal (vi ) is given.

As a result, the exclusive OR circuit 21 receives the clock signal (i
), the trailing edge descending portion that occurs at time tl is switched, and (viii
), it is output as the rising edge of the leading edge at tl, and the flip-flop circuit 22 of the 2-bit counter 12
．． 23 clock signal. In this way, the output signal of the flip-flop 22 will be as shown in (iii).
A 1/3 frequency divided wave with a duty ratio of 50% is output.

FIG. 4 is a block circuit diagram of a 7 frequency divider according to another embodiment of the present invention, and FIG. 5 is an operation waveform diagram of the circuit of the embodiment shown in FIG.

The 7 frequency divider circuit is a three-stage flip-flop circuit 32.34
．． 37, and the counter input duty ratio clock signal of 50% is input to the counter via the exclusive OR circuit 31. The circuit 31 corresponds to the clock switching circuit 11 in the principle diagram of the present invention. The output signal of the third stage most significant digit Q3 is input to the exclusive OR circuit 31 via the delay circuit 38.

The flip-flop circuit 32 is. When the exclusive OR circuit 31 is given a low level control signal from Q3, it operates at the rising point of the input exclusive OR circuit 31 signal.

However, when a high level signal of the most significant digit bit signal is applied from Q3, it starts to operate at the falling point of the large clock signal.

In the clock signal i) of FIG. 5, the injection force of the flip-flop 32 changes at its rising point up to the fourth clock signal, but the control signal from 03 passes through the delay circuit 38 to the clock signal vi). When applied to circuit 31 as delayed outputs, clock pulses number 4 through 7 change 01 at the falling point of the clock pulse.

If both the rising point and falling point of the input cross signal are used for counter operation in this way, the fourth
The frequency was divided by 7 between the rising point of the clock pulse and the rising point of the 11th clock pulse, and the duty ratio was 50.
% clock signal is generated.

〔Effect of the invention〕

The present invention makes it possible to generate a frequency divided by an odd number (n) while accurately maintaining a duty ratio of 50% with a simple circuit configuration, and its effects are extremely large.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a block circuit diagram of a 1/3 frequency divider according to an embodiment of the present invention, Fig. 3 is an operation waveform diagram of the embodiment circuit of Fig. 2, Fig. 4 is a block circuit diagram of a 1/7 frequency divider according to an embodiment of the present invention, FIG. 5 is an operating waveform diagram of the circuit of the embodiment shown in FIG. 4, and FIG. 6 is a block circuit diagram of a conventional 1/3 frequency divider. , FIG. 7 is an operating waveform diagram of the circuit of FIG. 6. In the figure, 2.3.22.23.32.34.37 is a flip-flop circuit, 4 is a NAND circuit, 5 is an OR circuit, 11 is a clock switching circuit, 12 is a fi+l counter, and 13 is a control Signal generation circuit, 2131.33.36 is exclusive OR circuit, 24.35
is an AND circuit. Fig. 1 Block circuit diagram of a 1/3 frequency divider according to Akira Nagi's embodiment; Bronch circuit diagram of a conventional 1/3 frequency divider Fig. 6

Claims (1)

[Claims] Even value n+1 counter (12) and the counter (12)
a switching circuit (11) that takes out the (n+1)/2 count output of the counter and switches the polarity by controlling the input clock signal of the counter; and a switching control signal generating circuit (13) that supplies a switching control signal to the switching circuit. with a duty ratio of 5
An odd-number frequency divider, characterized in that it generates a clock having a period of 1/n of 0%.