DE10355698B4 - Flip-flop with multiple operation mode - Google Patents

Abstract

Flip-Flop (1) with multiple operation mode with:
(a) a master latch (2) clocked by an external clock signal (clk) having a clock period T for receiving and latching a data signal (D ), wherein the operation mode control signal (DRD) switches the flip-flop (1) between a first and a second operating mode;
(b) a slave latch (22) clocked by the external clock signal (clk) coupled to the master latch (2) for generating and outputting an output signal (Q) in response to the operation mode control signal (DRD) ;
(c1) wherein the flip-flop (1) operates in the first operating mode as a clock edge-controlled D flip-flop and outputs the data signal (D) as an output signal (Q);
(c2) wherein the flip-flop (1) outputs, in the second operation mode, a clocked signal having the same clock period T as the external clock signal (clk) as an output signal (Q); and where
(d) in both operating modes all rising signal edges of the output signal (Q) from the data signal ...

Description

The The invention relates to a flip-flop with multiple operation mode, in particular for one Clock frequency divider with clock pass mode.

Flip-flops are switching elements that are able to store binary information and find many uses u.a. in registers, shift registers, Save, counters and in particular frequency dividers.

Under a flip-flop is in the following the series connection of two Latches understood, where a latch is a bistable flip-flop which is a data input, an output and a clock input having. At logical H level (high) one to the clock input applied clock signal, a latch switches the data signal applied to the data input through to the exit, so it's transparent. Is the clock signal however, at an L level (low), the latch is in memory mode and gives at its output a signal according to the level of the front switching the clock signal from H level to L level Data signal at the data input off.

The Transparency of the latches is lost, if you have two latches, the with complementary clock signals are controlled in series, to a flip-flop. at the edge-triggered D flip-flop, the rising edge triggers, the output of the first master latch is at the data input coupled to the second slave latch. The output of the master latch follows the data signal as long as the clock signal is at L level and the Slave latch remains locked. If the clock signal goes to H level, so locks the master latch, and the following slave latch takes over logical state of the output of the master latch.

Out In the art, registers are the parallel arrays of D flip-flops, which are supplied with a common clock signal known - as it is for example, in semiconductor circuit technology, U. Tietze, Ch. Schenk, 12th edition, 2002, Springer Verlag, Berlin, ISBN 3-54-42849-6. In particular, frequency divider circuits known with D flip-flops, which consists of a clock signal specific clock period T clocked output signals with multiples of the clock period T deliver. Often in circuits clock signals with different clock periods needed e.g. in microprocessor chips that Controller circuits for contain various tasks that require different clocks. Also in phase locked loops (PLL = phase locked loop) are flip-flops and switchable Clock frequencies needed. In particular, the output of a signal, the same clock period T as the externally applied clock signal, is usually required.

The document EP 1 081 857 A1 describes, for example, a D flip-flop circuit arrangement of two latches, which is operable with both rising and falling clock edges. The document WO 03/021785 A2 discloses a clock divider circuit for dividing a clock by any even number. The document aims to avoid D flip-flop delays.

The 1 shows a circuit arrangement with a D-type flip-flop F according to the prior art, a multiplexer M and two series-connected inverters I1, I2. A data signal D is connected via an input DE of the circuit arrangement to the data input DS of the flip-flop F, which is clocked by a clock signal clk, which is applied to its clock input CT. An output signal at its output QQ is coupled to the multiplexer M. The D-type flip-flop F is connected in parallel with an inverter chain I1, I2, which is passed through by the clock signal clk, which is supplied via an input TX of the state-of-the-art circuit, and which is likewise fed to the multiplexer M.

Of the Multiplexer M switches depending on a control signal DD, over a control terminal S is led to the circuit, either the output signal Q of the D flip-flop F or delayed by the two inverters I1, I2 clock signal clk to an output A by.

The circuit arrangement 1 The prior art allows operation as a conventional D flip-flop, wherein the data input signal D is output via the multiplexer M as the output signal Q of the clock signal clk clocked flip-flop F to the output. In a second operating mode specified by the control signal DD, the multiplexer M switches the clock signal clk, which has passed through the inverters I1, I2, to the output A. The inverters I1, I2 are dimensioned such that, when switching from the flip-flop operating mode to the clock operating mode, the rising clock edges of the output signal Q of the flip-flop F coincide with the rising clock edges of the delayed clock signal clk.

The same known principle of delaying looping through an external clock signal clk shows the 2 for a dual frequency divider. The frequency divider or divider U is formed by a D flip-flop F according to the prior art, wherein the output signal Q is fed back to the data input DS of the flip-flop F as a data signal QR. Thus, the coaster U delivers an Off output signal Q, which has twice the clock period 2T of the clock signal clk, which is led externally via an input TX to the clock input CT of the flip-flop F. The output signal Q of the divider U is fed from a multiplexer M, which is controlled by a control signal DD, in a first divisor mode to the output A. In a second mode, the clock-passing mode, the multiplexer M switches the clock signal clk delayed by two series-connected inverters I1, I2 to the output A as a function of the control signal DD (direct drive). The inverters I1, I2 are dimensioned such that the delay of the signals Q, QR caused by the divider U or flip-flop F is compensated and no clock offset occurs when switching between the divider mode and the clock pass mode.

The Prior art circuitry has a series of disadvantages. To the clock offset in the divide or clock pass mode to minimize the inverters I1, I2 and delay lines exactly to the signal delay time, which is caused by the flip-flop F, to be adjusted. It however, only an even number of inverters I1, I2 can be used with each inverter always having a minimum delay time for the clock signal represents. Therefore lets an adjustment to the signal delay time caused by the Flip-flop F is caused to reach only in discrete steps. About that hangs out the delay time from inverters or similar delay elements from the temperature, the supply voltage and also manufacturing methods from. The same applies to the delay caused by flip-flops, so that a more precise Balance in changing Operating conditions is very difficult. Another disadvantage of parallel implementation the clock signal is a high power consumption, because even during the Clock pass mode of the frequency divider is constantly in operation. In addition, will According to the prior art, the clock output signal in the frequency divider mode and clock cycle mode generated from different signals. in the Divisor mode, the output signal is generated by the feedback D flip-flop, while in clock-pass mode, only the external clock signal is delayed output becomes. As a result, the level of the output clock signal in the Divide mode of the level swing of the delayed external clock signal distinguish and act adversely. This is particularly disadvantageous when switching between modes.

It It is an object of the present invention to provide a flip-flop, in particular for use in clock frequency dividers, in a first operating mode operates as a flip-flop and in a second mode of operation a clocked Outputting the same clock period as an external one Clock signal outputs, and the rising edges of the output signal via a wide range of operating conditions when switching between the operating modes are synchronous. The present Invention is also the task is based, a clock frequency divider with clock pass mode to provide that no clock skew when switching between a Divider and a clock crossing mode over a wide range of Operating conditions.

According to the invention this Task by a flip-flop with the features of the claim 1 and by a clock frequency divider with clock pass mode with the features of claim 14 solved.

Accordingly, a Flip-flop provided with multiple operation mode, which is one of a external clock signal having a clock period T, clocked Master latch for receiving and buffering one by means of a first logic circuit with an operating mode control signal logic linked Data signal, wherein the operation mode control signal that Flip-flop between a first and a second operating mode switches. The flip-flop according to the invention further comprises a slave latch clocked by the external clock signal which is coupled to the master latch for generating and Output of an output signal in response to the operation mode control signal. The flip-flop operates in the first operating mode as a clock edge-triggered D flip-flop and outputs the data signal as an output signal. In the second Operating mode, the flip-flop gives a clocked signal, which has the same clock period as the external clock signal, as an output signal out. In this case, in the two operating modes all rising signal edges the output signal with the data signal and the operation mode control signal through the first logic circuit, the master latch and the slave latch generated.

Further, the object solves a clock frequency divider with clock pass mode with a first inventive flip-flop with multiple operating mode, which is clocked Tet of the external clock signal, wherein at the third terminal of the flip-flop according to the invention a clock pass mode control signal is applied and applied to its output a frequency-divided output clock signal ; at least one second resettable D flip-flop clocked by the external clock signal and having a data input to which the output clock signal of the first flip-flop is coupled and a data output to which an intermediate signal is applied. It is to the data input of the first flip-flop with the output clock signal by means of a NOR gate, logic-coupled intermediate signal applied. In the first mode of operation, the frequency divider provides an output clock signal having a larger clock period than the external clock signal. In the second mode of operation, the frequency divider provides an output clock signal having the same clock period T as the external clock signal.

The The idea underlying the invention is that the rising Flanks of the output signal in all operating modes of the same Elements of the flip-flop are generated. This means that in the first operating mode or frequency divider mode, the output signal from the operating mode control signal and the data signal or fed back Data signal from the master and slave latch and the first logic circuit is generated, and in the second mode of operation or clock cycle mode not the external clock signal, for example, by delay stages modified, but by the master latch and the Slave latch and the first logic circuit an output clock signal is generated, the same clock period as the external clock signal having.

There thereby the output signal in both operating modes and the rising Flanks of the output signal in the same manner in the flip-flop according to the invention are generated, also occurs when switching between the operating modes no Taktbzw. Signal offset on. Thus, there are no further synchronization measures with external gates, e.g. Inverter stages as a delay line as in the prior art, not agile. Another advantage of flip-flops according to the invention and the clock frequency divider is that its function independent of external influences, such as e.g. Fluctuations in the supply voltage or temperature changes, independently is. Advantageously, the flip-flop and the clock frequency divider according to the invention is simple to integrate and as resettable D-flip-flop executable. The clock frequency divider lets at any time in particular from the clock pass mode switch to the frequency divider mode without the duty cycle of the To influence output clock signal.

In an advantageous embodiment has the flip-flop according to the invention a first connection for the external clock signal, a second terminal for the data signal, a third port for the operation mode control signal and an output for outputting the Output signal on. Linked the first logic circuit, which is preferably an OR gate, the operation mode control signal with the data signal to a first Intermediate signal, the master latch receives this first intermediate signal and gives in dependence of the inverse external clock signal to a second intermediate signal the slave latch off. The second slave latch has a second logic circuit on, preferably with a first inverter and a first AND gate, wherein the first AND gate the operation mode control signal inverted by the first inverter the output signal logically linked to a third intermediate signal. The Slave latch further comprises a selection circuit, which depends on from the external clock signal, the second or third intermediate signal as output signal to the output switches.

The preferred embodiment points opposite a conventional one Latch only a minimal circuit overhead, namely the selection circuit and the first and second logic circuits.

In a preferred embodiment of the flip-flop according to the invention The selection circuit has tristate drivers, each of which are driven complementary to the external clock signal. Tristate drivers serve the particularly safe switching and interconnection of logical signals.

In a further preferred embodiment of the flip-flop, the selection circuit is designed as a multiplexer. There Multiplexer present in standard libraries is an embodiment With such a particularly easy to implement.

In a preferred embodiment of the flip-flop according to the invention is the master latch as resettable D-latch executed with a reset input to which a reset signal is coupled, and the second logic circuit, the reset signal, the Operation mode control signal and the output signal to the third Intermediate signal logically linked. A third logic circuit, preferably a second inverter and a second AND gate, combines the external clock signal and the reset signal inverted from the second inverter logically to a fourth intermediate signal, wherein the selection circuit of the fourth Intermediate signal is controlled.

The preferred development has the advantage that the flip-flop invention not only has two operating modes, but also resettable is.

In an alternative embodiment of the multi-mode flip-flop according to the invention, a first terminal for the external clock signal, a second terminal for the data signal, a third terminal for the operating mode control signal and an output for outputting the output signal are provided. The first logic circuit, which preferably out as an OR gate leads logically connects the operating mode control signal to the data signal to a first intermediate signal. The alternative embodiment of the flip-flop according to the invention further comprises a second logic scarf device, which preferably comprises an inverter and an AND gate, wherein the AND gate, the inverted by the inverter reset signal, the operating mode control signal and the output signal to a second intermediate signal linking. The master and slave latches are integrated in a resettable D flip-flop having a data input to which the first intermediate signal is coupled, a clock input to which the external clock signal is coupled, a reset input to which the second intermediate signal coupled to and having a data output coupled to the output.

In this alternative embodiment the inventive idea is particularly easy to implement because only a common one resettable D flip-flop, an inverter and two logic gates are interconnected.

In a particularly advantageous embodiment of the invention is attached coupled to the output of the flip-flop is a bus-hold cell. This affects itself particularly advantageous if only a small capacitive load is coupled to the output. The bus hold cell then acts stabilizing.

In Another preferred development is the inverted output signal fed back to the third terminal of the flip-flop as a data signal. This development creates a clock frequency divider, the external Clock to a clock with twice the clock period converts, and Furthermore According to the invention, a clock signal outputs with the clock period of the external clock signal.

In a preferred embodiment the frequency divider according to the invention At least one of the flip-flops is designed as resettable flip-flop.

Further advantageous embodiments and refinements of the invention are Subject of the dependent claims and the description with reference to the drawing.

The Invention will be described below with reference to the figures in the drawing specified embodiments explained in more detail. It shows:

1 a circuit arrangement with D-flip-flop according to the prior art;

2 a dual clock divider of the prior art;

3 a block diagram of a flip-flop according to the invention;

4 : Signal curves in the flip-flop according to the invention;

5 a preferred embodiment of the flip-flop according to the invention;

6 a preferred development of the flip-flop with reset input according to the invention;

7 an alternative embodiment of the flip-flop according to the invention; and

8th a block diagram of a clock frequency divider according to the invention.

The 3 shows a block diagram of an embodiment of the flip-flop according to the invention 1 with multiple operation mode. The flip-flop 1 has all the connections of a conventional flip-flop and in addition a connection 6 for receiving an operation mode control signal DRD, which the flip-flop 1 when it is at logical L level, in the first operating mode switches, ie the flip-flop operates as a clock edge-triggered D flip-flop. When it is at logic H level, the flip-flop operates in the second mode of operation, the clock pass mode, ie, the flip-flop 1 gives at his exit 10 a clock signal having the same clock period as the externally applied clock signal clk.

The flip-flop 1 has a first connection 4 for receiving the external clock signal clk on, a second terminal 5 for a data signal D and an output 10 for outputting an output signal Q.

It is a master-latch 2 provided, which at an inverting clock input 33 receiving the external clock signal clk, a data input 32 and an exit 34 having. At the data input 32 is a first intermediate signal Z1, which from the operating mode control signal DRD and an incoming data signal D by means of an OR gate 7 is generated.

Lies the operation mode control signal DRD to L level is the first intermediate signal Z1 is equal to the data signal D. In the clock pass mode, the operation mode control signal is present DRD to H level, whereby the first intermediate signal Z1 also a H level has.

The flip-flop 1 also has a slave latch 22 on which the output of the master latch 2 or a second intermediate signal Z2 receives. In the slave latch 22 is a third intermediate signal Z3 by means of a logic circuit 29 from the factory mode control signal DRD and the feedback output Q of the flip-flop 1 generated. In the logic circuit 29 links an AND gate 18 the output Q of the flip-flop 1 with that through an inverter 17 inverted operating mode control signal DRD logic to the third intermediate signal Z3.

In the first mode of operation, the AND gate provides 18 an H level as a third intermediate signal Z3, if the output signal Q is also at H level and stores by the feedback this state. The AND gate 18 However, it supplies an L level as a third intermediate signal Z3 if the output Q of the flip-flop 1 is at L level and stores this state. In the clock pass mode, however, the third intermediate signal Z3 is always at L level.

The selection circuit 13 , which is controlled by the external clock signal clk, switches the second intermediate signal Z2 to the output 10 of the flip-flop 1 as the output signal Q through, when the clock signal is at H level, and switches the third intermediate signal Z3 as an output signal Q to the output 10 when the external clock signal clk is at L level.

Based on 4 which shows the timing waveforms of the clock signal clk, the operation mode control signal DD, a data signal D and the corresponding output signal Q, will be described below the operation of the flip-flop according to the present invention 1 as it is in the 3 is shown explained.

The external clock signal clk has a clock period T. As long as the operation mode control signal DD is at H level (from t0 - t2) is at the data input 32 of the master latch 2 always an H level on, at the output 34 of the master latch 2 as the second intermediate signal Z2 at the selection circuit 13 is applied. Thus, the output Q is at each half-clock in which the external clock signal clk is high and the selection circuit 13 thus the second intermediate signal Z2 to the output 10 turns on, always at H level.

In the second half-cycle, the external clock signal clk is at logical L level and the selection circuit 13 the third intermediate signal switches as output Q to the output 10 of the flip-flop 1 , Since the third intermediate signal Z3 is always at the L level in the clock passing mode, an output signal Q is thus generated which maps the external clock signal clk, and the output signal Q has the same clock period T as the external clock signal clk.

However, the external clock signal clk is not turned on, but an output signal equivalent to the external clock signal clk is output from the master latch 2 and the slave latch 22 generated from the operation mode control signal DRD and the data signal D. The output signal Q thus always follows the external clock signal clk in the clock pass mode.

At a time t2, the operation mode control signal DD is set to L level, whereby the flip-flop 1 is put in the flip-flop mode. The data signal D is high until time t3, which is one-half clock after the time t2 when the operation mode control signal DD changes from H level to L level. In the flip-flop mode is at the output 10 an output signal Q, which corresponds to the second intermediate signal Z2 of the master latch 2 corresponds as long as the external clock signal clk sets to H level. When the external clock signal clk goes to L level, the slave latch stops 22 with the AND gate 18 to which the output signal Q is fed back, the logic level of the output signal Q as the third intermediate signal Z3, which from the selection circuit 13 turn to the exit 10 is turned on.

A change in the level of the output signal Q thus occurs only when the level of the external clock signal clk changes from the high level H, or at a rising clock edge. Therefore, the output signal Q follows the data signal D, which changes from H to L level at time t3 (as in FIG 4 shown) with a half-cycle delayed at time t4. The same applies to the transition of the data signal D at the time t5 from L to H level. The output Q accordingly changes from L to H level half a clock later at time t6.

Because the OR gate 7 for generating an H level in the clock pass mode of the flip-flop 1 before the master latch 2 at the entrance 32 is switched, the clock through-going mode is taken or left in synchronism with the falling clock edge of the external clock signal clk.

At time t7, the operation mode control signal DD is set from L to H while the data signal D is at H level. During the half-clock, which lasts from t7 to t8, the external clock signal clk is at H level, and the selection circuit 13 the second intermediate signal Z2 switches as output signal Q to the output 10 of the flip-flop 1 by which remains unchanged as long as the external clock signal clk has the L level. Only with the falling clock edge at the time t8 reached the flip-flop 1 the clock pass mode and switches by means of the selection circuit 13 the low level third intermediate signal Z3 as the output signal Q, whereby the output signal Q is clocked and has the same clock period T as the external clock signal clk.

The 5 shows a preferred embodiment of the flip-flop according to the invention 1 which are essentially all elements of 3 and where at the exit 10 of the flip-flop in addition a so-called bus-hold cell 21 is coupled. The selection circuit is as a pair of tristate drivers 19 . 20 executed.

The bus hold cell or bus keeper cell 21 serves to stabilize the output signal Q when a particularly low capacitive load at the output 10 of the flip-flop 1 is applied. A bus keeper cell may have two cross-coupled inverters acting as a weak latch and last at the output 10 maintained logical level.

The first tristate driver 19 acts as a controllable switch, which is controlled by the external clock signal clk and the second intermediate signal Z2 then to the output 10 turns on when the external clock signal is at logic H level. The second tristate driver 20 is complementarily controlled by the external clock signal clk and then switches the third intermediate signal Z3 to the output 10 when the external clock signal clk is at logical L level. The preferred embodiment of the flip-flop according to the invention 1 is thus very stable and delivers accurate H and L levels to the output 10 ,

The 6 shows a preferred embodiment of the flip-flop according to the invention 1 with reset or reset connection. The flip-flop 1 sees a resettable D-latch 3 with an inverting reset input 9 , an inverting clock input 33 , a data input 32 and an exit 34 as master-latch before. The flip-flop 1 has a first entrance 4 for the external clock signal clk, a second input 5 for the data signal D, a third input 6 for the operation mode control signal DRD, a fourth input 8th for a reset signal RES and an output 10 for the output signal Q on.

The operation mode control signal DRD and the data signal D are an OR gate 7 Logically linked to a first intermediate signal Z1, which is connected to the data input 32 of the resettable D-latch 3 is guided. The clock signal clk is at the inverting clock input 33 of the resettable D-latch 3 guided.

A second logical circuit 29 that have an inverter 17 and an AND gate 18 has the reset signal RES, the operation mode control signal DRD which by the inverter 17 is inverted, and the output signal Q to a third intermediate signal Z3.

A third logic circuit 28 has a second inverter 14 and a second AND gate 12 and connects the external clock signal clk with the reset signal RES, which from the second inverter 14 is inverted, to a fourth intermediate signal Z4.

A multiplexer 11 which serves as a selection circuit is controlled by the fourth intermediate signal Z4 and switches either the second intermediate signal Z2 or the third intermediate signal Z3 depending on the output to the output 10 as output signal Q through.

If the reset signal RES is at logical L level, the external clock signal clk is applied as an intermediate signal Z4 to the multiplexer as the control signal, the resettable master latch 3 works as a D-latch and the logic circuit 29 and the multiplexer 11 act as a slave latch.

At logical H level of the intermediate signal 4 the multiplexer switches the second intermediate signal Z2 to the output 10 through, and at logic L level of the fourth intermediate signal Z4, the multiplexer switches 11 the third intermediate signal Z3 as output Q to the output 10 of the flip-flop 1 by. The preferred development thus operates like the flip-flop according to the invention 3 ,

When the reset signal RES is at logic H level, the inverting reset input is present 9 of the D-latch 3 to L level and the D-Latch 3 delivers at its output 34 an L level as a second intermediate signal Z2. The fourth intermediate signal Z4 is then always at L level, so that as output signal Q always a zero level is output.

The 7 shows an alternative embodiment of the flip-flop according to the invention with multiple operating mode. The alternative embodiment of the flip-flop 1 has a first connection 4 for the external clock signal clk, a second connection 5 for the data signal D, a third connection 6 for the operation mode control signal DRD and an output 10 to output the output signal Q on.

Further, a resettable D flip-flop 16 provided that a clock input 25 , a data input 21 , a data output 27 and a reset input 26 wherein a logical H level at the reset input is an asynchronous reset of the D flip-flop 16 triggers.

An OR gate 7 links the operation mode control signal DRD to the data signal D to a first intermediate signal Z1 which is applied to the data input 21 of the D flip-flop 16 is created.

A logic circuit supplies a second intermediate signal Z5 by means of an AND gate 24 , which the operating mode control signal DRD, the output signal Q and that of an inverter 23 inverted clock signal clk linked. The second intermediate signal Z5 is at the reset input 26 of the D flip-flop 16 placed. The data output 27 of the D flip-flop 16 supplies the output signal Q to the output 10 of the flip-flop according to the invention 1 with multiple operation mode.

In this alternative embodiment of the flip-flop 1 is the asynchronous reset of the resettable D flip-flop 16 used to generate the falling clock edges of the output signal Q in the clock pass mode.

in the Clock pass mode, the first intermediate signal Z1 is always at logical H level and is output as output Q as long as that external clock signal clk is high.

With a falling clock edge, or a change of the external clock signal from H to L level provides the AND gate 24 an H level as a second intermediate signal Z5 to the reset input 26 of the D flip-flop 16 , so that the output signal Q is also set to L level. Thus, in the clock pass mode, the output signal Q always follows the externally applied clock signal clk.

In the clock pass mode, the falling edges of the output signal Q experience a slightly higher delay than the rising edges of the signals due to the delay times of the asynchronous reset and the inverter 23 and AND gates 24 , When switching between flip-flop mode and clock pass mode, however, no offset occurs because the rising edges of the output signal are always affected by the resettable D flip-flop 16 are generated.

The 8th shows a clock frequency divider 30 with clock crossing mode with a first flip-flop according to the invention 1 with multiple operation mode and a second resettable D flip-flop 16 , The clock frequency divider 30 is a triple frequency divider with a clock input 35 for receiving an external clock signal clk, a control input 36 for receiving a clock passing mode control signal DRD, a reset input 37 for receiving a reset signal RES and an output 38 for outputting a frequency-divided output clock signal DIV.

The clock inputs 4 . 25 the flip-flops 1 . 16 receive the external clock signal clk. To the data input 21 of the second flip-flop 16 the frequency-divided output clock signal DIV is fed back. The second flip-flop 16 delivers at its data output 27 an intermediate signal Z6 which is logically linked by a NOR gate to the frequency-divided output signal DIV and to the data input 5 of the flip-flop according to the invention 1 is run with multiple operating mode.

If that at the third port 6 of the flip-flop according to the invention 1 applied clock pass mode control signal is at logical L level and the reset input 26 of the second flip-flop 16 supplied reset signal is at logic L level, the inventive clock frequency divider operates 30 as a triple divider. The clock frequency divider is at its output 38 a frequency-divided output clock signal DIV, which is a threefold clock period 3T of the external clock signal clk.

On the other hand, when the clock-through mode control signal DRD is at H level, the clock frequency divider outputs 30 at its exit 38 that of the first flip-flop according to the invention 1 at its exit 10 supplied clocked signal having the same clock period T as the external clock signal clk.

As an inventive flip-flop 1 with multiple mode in the clock divider 30 is used, are in both modes of operation all rising signal edges of the output signal only from the clock pass mode control signal DRD of the flip-flop according to the invention 1 generated. Thus, no clock offset between the frequency-divided output clock signal DIV in the first operation mode and the signal having the same clock period T as the external clock signal clk can occur in the clock pass mode.

The frequency divider according to the invention makes it possible to switch over and to output clocked signals having different clock frequencies or frequency-divided signals and a signal corresponding to the source clock signal clk or the externally applied clock signal clk, without a signal offset occurring or the level deviation being changed. The frequency divider according to the invention 30 It is also easy to integrate and works independently of external influences such as fluctuations in the supply voltage, temperature changes or inaccuracies in the manufacturing process. In addition, the frequency parts according to the invention in standard CMOS technology can be produced at low cost.

Although the present invention above based on preferred embodiments she is not limited to it but in many ways and modifiable.

The invention is not based on the structure of the multiple shown in the preceding figures xers or the tristate driver. In particular, the selection circuit may be constructed of well-known controllable switches and the logic operation or inversions of signals may be modified in any manner, without deviating from the basic principle of the invention. Synchronization of the falling edges of the clocked output signals in the two operating modes can also be achieved using the idea underlying the invention, for example, by inverting the external clock signal.

1

Flip-flop with multiple mode

2

Master latch

3

resettable D latch

4

clock input

5

data input

6

Control signal input

7

OR gate

8th

Reset input

9

Reset input

10

output

11

multiplexer

12

AND gate

13

select circuit

14

inverter

15

logic circuit

16

D flip-flop

17

inverter

18

AND gate

19

Tristate drivers

20

Tristate drivers

21

data input

22

Slave latch

23

inverter

24

AND gate

25

clock input

26

Reset input

27

data output

28

logic circuit

29

logic circuit

clk

clock signal

A

output

M

multiplexer

DRD

Direct-drive signal

F

D flip-flop

I1

inverter

I2

inverter

RES

Reset signal

D

data signal

Q

output

Z1, Z2, Z3, Z4, Z5, Z6

intermediate signal

U

frequency divider

DE

data input

DS

data input

CT

clock input

QQ

data output

DIV

Output clock signal

T

clock period

QR

feedback control signal

Claims (15)

Flip flop ( 1 multi-operation mode comprising: (a) a master latch clocked by an external clock signal (clk) having a clock period T ( 2 ) for receiving and buffering one by means of a first logic circuit ( 7 ) with an operating mode control signal (DRD) logically linked data signal (D), wherein the operating mode control signal (DRD) the flip-flop ( 1 ) switches between a first and a second operating mode; (b) a slave latch clocked by the external clock signal (clk) ( 22 ), which is sent to the master latch ( 2 ) for generating and outputting an output signal (Q) in response to the operation mode control signal (DRD); (c1) where the flip-flop ( 1 ) operates in the first operating mode as a clock edge-controlled D flip-flop and outputs the data signal (D) as an output signal (Q); (c2) where the flip-flop ( 1 ) in the second operating mode outputs a clocked signal having the same clock period T as the external clock signal (clk) as an output signal (Q); and wherein (d) in both modes of operation, all rising signal edges of the output signal (Q) from the data signal (D) and the operation mode control signal (DRD) through the first logic circuit ( 7 ), the master latch and the slave latch ( 22 ) are generated. Flip flop ( 1 ) according to claim 1, characterized in that the flip-flop ( 1 ) (a) a first connection ( 4 ) for the external clock signal (clk), a second connection ( 5 ) for the data signal (D), a third connection ( 6 ) for the operating mode control signal (DRD) and an output ( 10 ) for outputting the output signal (Q); and characterized in that (b) the first logic circuit ( 7 ) the operation mode control signal (DRD) is logically linked to the data signal (D) to a first intermediate signal (Z1); (c) the master latch ( 2 ) receives the first intermediate signal (Z1) and, depending on the inverse external clock signal (clk), sends a second intermediate signal (Z2) to the slave latch (Z1). 22 ) outputs; (d) the slave latch ( 22 ) a second logic circuit ( 29 ) for the logic operation of the operating mode control signal (DRD) with the output signal (Q) for generating a third intermediate signal (Z3) and a selection circuit ( 13 ), which in response to the external clock signal (clk) the second or third intermediate signal (Z1, Z3) as an output signal (Q) to the output ( 10 ), has. Flip flop ( 1 ) according to claim 2, characterized in that the first logic circuit ( 7 ) has an OR gate. Flip flop ( 1 ) according to claim 2 or 3, characterized in that the second logic circuit ( 29 ) a first inverter ( 17 ) and a first AND gate ( 18 ), wherein the first AND gate ( 18 ) that of the first inverter ( 17 ) inverted operating mode control signal (DRD) with the output signal (Q) to the third intermediate signal (Z3) linked. Flip flop ( 1 ) according to one of claims 2 - 4, characterized in that the selection circuit ( 13 ) Tristate driver ( 19 . 20 ), each of which is complementarily driven by the external clock signal (clk). Flip flop ( 1 ) according to one of claims 2 - 4, characterized in that the selection circuit ( 13 ) a multiplexer ( 11 ) having. Flip flop ( 1 ) according to one of claims 2 - 6, characterized in that (a) the master latch ( 2 ) as a resettable D-latch ( 3 ) with a reset input ( 9 ) to which a reset signal (RES) is coupled; (b) the second logic circuit ( 29 ) logically combining the reset signal (RES), the operation mode control signal (DRD) and the output signal (Q) to the third intermediate signal (Z3); (c) a third logic circuit ( 28 ), the external clock signal (clk) is logically linked to the reset signal (RES) to a fourth intermediate signal (Z4), and (d) the selection circuit ( 11 ) is controlled by the fourth intermediate signal (Z4). Flip flop ( 1 ) according to claim 7, characterized in that the third logic circuit ( 28 ) a second inverter ( 14 ) and a second AND gate ( 12 ), wherein the second AND gate ( 12 ) that of the second inverter ( 14 ) inverted reset signal (RES) to the fourth intermediate signal (Z4). Flip flop ( 1 ) according to claim 1, characterized in that the flip-flop ( 1 ): (a) a first port ( 4 ) for the external clock signal (clk), a second connection ( 5 ) for the data signal (D), a third connection ( 6 ) for the operating mode control signal (DRD) and an output ( 10 ) for outputting the output signal (Q); and (b) wherein the first logic circuit ( 7 ) the operation mode control signal (DRD) is logically linked to the data signal (D) to a first intermediate signal (Z1); and (c) the flip-flop a second logic circuit ( 15 ) for logically combining the reset signal (RES) with the operation mode control signal (DRD) and the output signal (Q) to a second intermediate signal (Z5); and wherein (d) the master and slave latches are stored in a resettable D flip-flop ( 16 ), which has a data input ( 21 ) to which the first intermediate signal (Z1) is coupled, a clock input ( 25 ) to which the external clock signal (clk) is coupled, a reset input ( 26 ) to which the second intermediate signal is coupled, and a data output ( 27 ) to the output ( 10 ) is coupled. Flip flop ( 1 ) according to claim 9, characterized in that the first logic circuit ( 7 ) has an OR gate. Flip flop ( 1 ) according to claim 9 or 10, characterized in that the second logic circuit ( 15 ) an inverter ( 23 ) and an AND gate ( 24 ), wherein the AND gate ( 24 ) that of the second inverter ( 23 ) inverted reset signal (RES), the operating mode control signal (DRD) and the output signal (Q) to the second intermediate signal (Z5) linked. Flip flop ( 1 ) according to one of claims 2 - 11, characterized in that to the output ( 10 ) a bus hold cell ( 21 ) is coupled. Flip flop ( 1 ) according to any one of claims 1-12, characterized in that the inverted output signal (Q) to the third terminal ( 5 ) of the flip-flop ( 1 ) is fed back as a data signal (D). Clock frequency divider ( 30 ) with clock-pass mode comprising: (a) a first flip-flop ( 1 ) with multiple mode according to one of claims 1 - 13 which is clocked by the external clock signal (clk), wherein at the third terminal ( 6 ) a clock pass mode control signal (DRD) is present and at its output ( 10 ) a frequency divided output clock signal (DIV) is applied; (b) at least one second D flip-flop ( 16 ) which is clocked by the external clock signal (clk) and which has a data input ( 21 ) to which the output clock signal (DIV) of the first flip-flop ( 1 ), and a data output ( 27 ) to which an intermediate signal (Z6) is applied; where (c) to the data input ( 5 ) of the first flip-flop ( 1 ) with the output clock signal (DIV) by means of a NOR gate ( 31 ) Logically linked intermediate signal (Z6) is present. Clock frequency divider ( 30 ) according to claim 14, characterized in that the at least one of the flip-flops ( 1 . 16 ) is designed as a resettable flip-flip.