JPS59156028A - Clock controlled type frequency dividing circuit - Google Patents

Abstract

PURPOSE:To attain sure frequency dividing operation and also to improve the frequency response by using the 2nd clock signal having a frequency >= two times of that of the 1st clock signal and synchronized therewith so as to control a pulse to be frequency-divided. CONSTITUTION:A clock signal phi1 becomes an input to a counter circuit CO as a pulse to be frequency-divided via a gate AND2, and the signal is frequency- divided at the circuit CO as shown in Figs. (a)-(d). Then, when the 15th pulse to be frequency-divided is inputted, all the outputs (a)-(d) of FF11-FF14 go to ''H'' [Figs. (a)-(d)], a coincident output (e) of a detecting circuit DE goes to ''H'' [Fig. (e)] and a clock signal phi2 is enabled at a gate NAND. That is, a signal being the inversion of the signal phi2 is obtained at an output terminal (f) of the gate NAND, an AND output of the signals phi1, phi2 is formed as a pulse to be frequency-divided [Fig. (g)] at an output terminal of the AND2 and given to the FF11. Then, the output (a) of the FF11 goes from ''H'' level to ''L''. Further, the coincidence output (e) goes to ''L'' and the signal phi2 is inhibited by the gate NAND, then the output signal (f) goes to ''H'' and the clock signal being the normal signal phi1 is inputted to the counter circuit Co afterward.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a clock-controlled frequency divider circuit that controls a divided pulse signal using a clock signal, and particularly relates to a clock-controlled frequency divider circuit that controls a divided pulse signal using a clock signal. This invention relates to a lock control type frequency divider circuit with good response.

[Prior art]

An example of a conventional clock-controlled frequency divider circuit is shown and explained in FIG. 1. FIG. 1 is a circuit diagram showing a conventional 2n-1 (hexadecimal) counter.

In the figure, FF1 to FF4 are D-type 7 flip-flops with a preset, and their negative outputs a to d are the inputs of the AND, and the coincidence output e of the AND is the flip-flop FF1.
~FF4 is configured to be supplied to the preset terminal Ps. Note that φ is a clock signal of the frequency-divided pulse.

The operation of the circuit configured as described above will be explained with reference to FIG. 2 showing its time chart.

First, the clock signal of the divided pulse having the waveform shown by φ in FIG.
A frequency-divided waveform as shown in FIGS. 2(a) to 2(a) is obtained from the output of the FF4. Then, when the 15th pulse is input, all the outputs of each flip 70-tube FFI to FF4 go to "H" level.
When the coincidence output e of ND becomes 'H' level, flip-flops FFl-FF4 are forcibly preset.

Next, when preset, the outputs of each of the seven lip-flops FFI to FF4 go to the "L" level, so the coincidence output e of the AND gate MΦ is shown in Figure 2 (
As shown in e), the level becomes ``H#H# level L'', the preset of each of the 7 lip flops FF1 to FF4 is canceled, and the clock signal φ of the frequency-divided pulse becomes the level of each of the 7 lip flops FF1 to FF4.
The frequency is divided by lip-flops FF1-FF4. During this repetition, the circuit shown in FIG. 1 operates as a hexadecimal counter.

However, in such a circuit, each of the seven lip-flops FFI to FF4 is preset by the "H" level of the coincidence output e of the AND gate nΦ.
Because there is a slight time delay, the preset signal disappears as soon as the first flip-flop FF is preset, and the remaining flip-flops FF are not preset and do not reach their initial state, and the divided pulse The disadvantage is that the frequency of the clock signal φ is divided, resulting in a malfunction as a hexadecimal counter.

Furthermore, as the frequency of the clock signal φ is increased, the pulse width of the preset signal of the coincidence output e at the time of AND get becomes narrower, and sufficient time is not obtained to preset each of the seven lip-flops FFI to FF4. , it had the disadvantage of causing the same malfunction as above.

[Object and structure of the invention]

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks, and its purpose is to provide reliable branching operation and clock control with good frequency response. The purpose of the present invention is to provide a type frequency divider circuit.

In order to achieve this object, the present invention uses a counter circuit to generate a signal assembled from the matching signals of each of the seven lip-flops and a second clock signal having a frequency 92 times higher than the frequency of the first clock signal of the divided pulse. The device is equipped with a switching circuit for controlling by switching from the first clock signal at the time of resetting the clock signal.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 3 is a circuit diagram showing an embodiment of the clock-controlled frequency divider circuit according to the present invention, and shows the case of a hexadecimal counter.

In FIG. 3, CO is a counter circuit which divides the frequency of the divided pulse into 2n-1, and is constituted by cascade-connected positive edge D-type flip-flops FFII to FF14. DE is a detection circuit that detects the output of the counter circuit CO, and the flip 70 tubes FF11 to F
It is constituted by 1 of an AND gate M which inputs each 100 outputs (negative outputs) @/%/d of F14 and performs the logical product of these four outputs to obtain a matching output e. SW is a switching circuit for alternately switching the first clock signal φ1 as a shorter frequency divided pulse signal and applying it to the counter circuit CO in combination at the time of AND-get of the detection circuit DE;
A two-man powered NAND game that inputs the coincidence output e (coincidence signal) from the detection circuit DE (ANI) 1 and the second clock signal φ2 (NAND and this NAND game)
It is constituted by a two-person AND gate AND2 which receives the output f of the NAND and the first clock signal φ1, performs a logical product of these two signals, and obtains a coincidence signal g. The coincidence signal g from AND2 is sent to the first stage 7 lip-flop F of the counter circuit CO.
It is configured to be supplied as the clock input CK of F11.

Next, the operation of the embodiment shown in FIG. 3 will be explained with reference to FIG. 4 showing its time chart.

First, the 7 lip-flop FF11 of the counter circuit CO
~ Negative output a which is each hundred output of FF14.

b, c, d are the detection circuits DE (four-person game) AND
This is the input for I. Then, the first clock signal φ
l is input to the counter circuit CO as a frequency-divided pulse via the AND gate AND2 of the switching circuit SW, and is divided by the frequency as shown in FIGS. 4(a) to (d). . Next, when the 15th divided pulse is input, the flip-flop FF1l
~Each hundred output a''-d of FF14 is shown in Fig. 4(a)~(d
) As shown in FIG.
), the second clock signal φ2 is enabled at the NAND gate of the switching circuit SW.

In other words, the fourth gate is connected to the output terminal of this NAND gate NAND.
An inverted signal of the second clock signal φ2 having a waveform as shown in FIG.
The AND output of the second clock signal φ2 and the second clock signal φ2 is produced as a divided pulse, and this divided pulse is applied to the clock input CK of the first stage flip 70-tube FF1l of the counter CO.

Here, since this second clock signal φ2 is synchronized with the first clock signal φ1 and has a frequency more than double, as shown in FIG. 4, when the divided pulse is input to the counter circuit CO, , the state of the flip-flop FF11 changes, and its Q output a changes from the "H# level" to the "L" level, as shown in FIG. 4(a).

Then, when the coincidence output e of the detection circuit DE changes from the ``H'' level to the ``L'' level, the second clock signal φ2 is inhibited in the NAND gate NAND. Output signal (f
) is forced to "H" level, and after that, the normal first clock signal φl is the clock signal of AND gate A.
It is given as an input to the counter circuit CO via ND2.

By repeating this series of operations, a reliable hexadecimal counter can be constructed.

In addition, when the clock frequency is high, the present invention controls the clock instead of applying resets in parallel as shown in the conventional example in Fig. 1, so the branching operation is sequential, which is better than the conventional example. frequency response is improved.

〔Effect of the invention〕

As explained above, according to the present invention, the divided pulses are controlled using the second clock signal, which is synchronized with the first clock signal and has twice the frequency or more. From this, reliable frequency division operation can be performed.
Further, since the D-type flip-flop does not require presetting, it can be configured with a small number of elements, and has the advantage of good frequency response, so it has an extremely large practical effect.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of a conventional frequency divider circuit, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is an example of a clock-controlled frequency divider circuit according to the present invention. The circuit diagram and FIG. 4 are time charts for explaining the operation of FIG. 3. FFII~FF14 Fist...7 Lip Flop, CO
・・Fist・Counter circuit, ANDl, AND2・・
・NAND gate, DE...detection circuit, NAND・
...Nant gate, SW...φ, switching circuit,
φl, φ2...Clock signals.

Claims (1)

[Claims] A counter circuit formed by cascading a plurality of flip-flops, a detection circuit that ANDs the outputs of each of the seven flip-flops of this counter circuit, and a coincidence signal from this detection circuit and a first clock signal of the divided pulse. and a second clock signal having a frequency at least twice as high as the frequency of the second clock signal, and a switching circuit that controls the counter circuit by switching a signal assembled from the first clock signal when the counter circuit is reset. A clock-controlled frequency divider circuit.