SU842818A1 - Device for monitoring pulse train - Google Patents

Description

(54) DEVICE FOR CONTROL OF SEQUENCE

PULSES

The outputs and the outputs are connected to the counting inputs of the first and second triggers, respectively, the zero outputs of the triggers are connected to the inputs of the first and second integration blocks, respectively, an adder, delay lines, three nullorgans, a reference voltage block, an AND element and a third OR element, the unit output of the first trigger is connected to the input of the delay line, the output of which is connected to the first input of the element I, the output of the sensor is connected to the first input of the first, second and third null organs, the first output of the block is the standard Voltage is connected to the second input of the first null organ, the output of which is connected to the upstream input of the AND element, the second output of the reference voltage block is connected to the second input of the second zero-organ, the output of which is connected to the first inverse input of the third element OR, third output of the block the reference voltages are connected to the second input of the third null organ, the output of which is connected to the second inverse input of the third OR element, the output of the AND element is connected to the direct input of the third OR element, the output of which is the output roystva.

As a result, the device can monitor pulse sequences with intervals between edges, with edge overlap, monitor a clock device, issuing simultaneously controlling and synchronizing series of pulses, cases where the leading edge of the controlling pulses at the previous output coincides with the leading edge at the subsequent output, and the synchronizing pulses are tied to the middle of the control pulses and, by their duration less than them, to control the dropout from the pulse sequence of one two or more pulses going through each other, fixes a malfunction of the triggering device of the source of pulses of the const I or const O type at the output, and can also control the change in the pulse frequency, Figure 1 shows the block diagram of the device for controlling the pulse sequence; 2 and 3 pulse diagrams of the device.

The device contains elements OR 1, 2; and 14, triggers 3 and 4, fleas 5. and 6 integration, adder 7, scaffold line 8, three zero-bodies 9 - block 12 of reference voltages, and And element 13.

When controlling the sequence at intervals between fronts and with overlapping fronts, the proposed device works as follows.

The inputs of the first element OR are given signals from the clocking buses with odd numbers and the inputs of the second element OR - even numbers. With the correct alternation of pulses at the outputs of the elements OR 1 and 2, a sequence with a period of alternation of pulses is obtained. At the outputs of the flip-flops 3 and 4, pulses with a certain frequency appear, which arrive at the inputs of the integration blocks 5 and 6 where they are limited in amplitude and integrate.

The RC integration unit constant is chosen equal to dp in order to obtain triangular pulses with approximately linear sides at the outputs of the integration blocks. The pulse width at the output of the integration blocks is determined by the formula

. (l-eV), where Up is the amplitude of impulses on

the input of the blocks of integration t voltage rise at their output

: The triangular pulses from the outputs of the integration blocks are fed to the inputs of the adder 7, in which they are summed, amplified and shifted the total pulses. Trapezoidal pulses are obtained at the output of the adder with an amplitude of K- (Up + UP.J) 4-Ucn,

where and

and Uo.spaces, pulses on

Pz

P-i outputs of integration blocks,

TO

the gain at the output of the adder,

and the bias voltage

CW is required to shift the pulses into a positive or negative voltage range.

Trapezoidal pulses from the output of the adder arrive at the first inputs of the zero-organs 9-11. At their second inputs, the unit of reference voltages outputs the following voltages: at the second input of the null organ 9

UjT, "-Uc I P- -ai, null-organ 10..

  + whether and zero-orga .. -de

Claims (3)

di is the voltage value that is selected depending on the control objectives. If it is necessary to control only the presence of pulses on the clocking buses, di is chosen the greatest; if it is necessary to determine the loss of a single pulse, the di is chosen to be smaller, and to control the pulse frequency, the di is chosen to be the smallest. At the outputs of the zero-organs 10 and 11 there will be a constant single signal, and on the output of the zero-organ 9 pulse sequence with a frequency equal to the pulse frequency at the output of the adder. These pulses arrive at the second input of the element I 13, to the first input of which, via the delay line 8, pulses from a single output of the flip-flops 3, and they appear during the switching of the single arm of the flip-flop from zero to one. The delay line delays the impulse arriving at the first input of the AND element for a time equal to the sum of the time of the transition processes of the integration block, cyNwaTOpa and null organ. With such a value of the delay time, the appearance of pulses at the first input of the element And corresponds to the appearance of a zero signal at the second input of the element And, therefore, at the output of the element And there will be a zero signal. Thus, the direct input of the OR 14 element receives a zero signal, and the inverse inputs receive individual signals, with the result that the OR output of the OR signal produces a zero signal, which indicates the correct operation of the controlled clock system (Figure 2a). When at least one (or two or more pulses following each other) drop out of a pulse sequence, the flip-flop moment of one of the triggers is delayed by time T (or more). In this case, the output voltage of one of the integration blocks is greater (or less) than the maximum (or minimum) voltage (depending on the output pulse). At the output of the adder 7, the amplitude of the output pulses increases (or decreases) and will be more (or less than Ug-rj) and at the output of the zero-body 10 (or 11) a zero signal appears, which is fed to the inverting input of the OR element, the output of which appears an error signal (Fig.26). When the pulses are lost to the clocking bus at the zero outputs, three of 3 and 4 can be set in pairs of single or zero signals. In this case, at the outputs of blocks 5 and integration, the output voltage tends either to its maximum value or to the minimum. As a result, the output of the adder 7 is set to a voltage greater than and less than or less than 1 e-g ® of the output of the element OR 14 an error signal appears. If a zero signal is set at the zero output of one of the triggers, and a zero signal at the zero output of the other, the voltage at the output of one of the integration blocks increases, and the output of the other tends to zero, and the zero voltage sets before the maximum. In this case, the voltage at the output of the adder 7 exceeds the Chatt. At the output of the element OR 14, an error signal appears. When the pulse frequency on the clocking tires decreases, their frequency also decreases at the outputs of the flip-flops 3 and 4. At the outputs of the integration blocks 5 and 6, the frequency of the triangular pulses also decreases and their span increases, which leads to a decrease in the frequency of trapezoidal pulses and to increase their range at the output of the adder 7 (figv). The amplitude of the pulses at the output of the adder 7 will then be greater than Pat, then less than the Pats. At the outputs of the zero-organs 10 and 11, zero signals appear, and at the output of the OR 14 element, there are single signals that signal a malfunction. At the clocking tires, the outputs of the flip-flops 3 and 4 also increase the frequency of the pulses, while at the outputs of blocks 5 and b of the integration the following frequency of the triangular pulses also increases and decreases their span, which leads to an increase in the trapezoid frequency pulses and to decrease their scope at the output of the adder 7 (Fig. 2d). The amplitude of the pulses at the output of the adder is less than 5m., At the output of the zero-body 9, a constant single signal appears that goes to the second input of the element and 13, at the first input of which pulses are received from a single trigger 3. At the output of the element And, in this case, there are pulses that arrive at the direct input of the element OR 14, at the output of which an error signal appears. Consider the operation of the device when monitoring pulse sequences that differ with duration of pulses. For example, the inputs of the element OR 1 are supplied with control pulses with odd numbers and synchronization pulses with even numbers, the inputs of the element OR 2 control pulses with even numbers and synchronization pulses with odd numbers. . The operation of the device is similar to that described above with the only difference that the loss of synchronizing pulses is controlled in the same way as a decrease in the pulse frequency (Fig. 3). For example, for a sequence of pulses in which the duration of the control pulses is equal and the duration of the synchronizing pulses is equal, where T is the period of the control or synchronizing pulses at the output of the elements or 1, And 2, as well as at the outputs of the 3 and 4 triggers. the constant of the integration blocks is chosen to be equal to the NFCMF. When at least one control impulse falls out of the pulse sequence, the moment of transferring one of the triggers is lost at the output of one of the blocks 5 and b of the input voltage is greater (or less) than the maximum (or minimum). At the output of the adder 7, the amplitude of the output pulses increases (or decreases), and at the output of one of the null organs 10 and 11 c., A zero signal is generated, and at the output of the OR element is 14-unit, which signals a failure (Fig. 3 If a single synchronizing pulse from the pulse sequence .switches one flip-flop, the instant of switching over one of the triggers is delayed by the time. I T. At the output of one of the integration blocks, the voltage will be greater (or less) than the maximum (or minimum). case at su exit The output voltage of the mator is less than Oj-, as a result of which the moment the pulse arrives at the first input of Eymeit I 13 at its second input will be a single signal j coming from the output of the null organ 9. A single signal is sent to the forward gate of the OR 14 element which then appears at the output of the device and signals a malfunction (Fig. 3). The above considered operation of the proposed device for controlling the sequence of pulses relates to logic elements, in which, the formula isoRoregon elnosti pulses comprising two flip-flop, two blocks integrated Vani, two OR inputs koto-. phx are the inputs of the device, and the outputs are connected to the counting inputs of the first and second triggers, respectively, the zero outputs of the triggers are connected to the inputs of the first and second integration blocks, respectively, in order to expand (Functional capabilities due to monitoring the pulse frequency ,, an adder, a delay line, three zero-orbits, a block of reference voltages, an AND element and a third OR element are introduced into the device. The single output of the first trigger is connected to the line input. and the delay, the output of which is connected to the first input of the element I, the output of the adder is connected to the first input of the first, second and third null organs, the first output of the reference voltage block is connected to the second input of the first zero organ, the output of which is connected to the second input of the element And, the second output of the reference voltage block is connected to the second input of the second zero-organ, the output of which is connected to the first inverse input of the third OR element, the third output of the reference voltage block is connected to the second input of the third zero-organ, output otorrhea connected to the second inverted input of the third OR member, the output member and coupled to the direct input of the third OR gate, whose output is the output device. . Sources of information taken into account in the examination 1. USSR author's certificate number 337782, cl. G On P il / 00, 1970. 2. Authors certificate of the USSR M 440665, cl. G 06 F 11/00, 1972. 3. Authors certificate of the USSR 9 643875, class, G 06 F 11/00, 1976 (prototype).