JPS63244931A - Frequency divider - Google Patents

Abstract

PURPOSE:To constitute a fixed frequency divider or a variable frequency divider without inserting a logic gate in a feedback loop, by attaching a switching function on the input part of a flip-flop, and changing the number of stages of the feedback loop. CONSTITUTION:When a control signal M is set at 0 and the output Q2 of the flip-flop 2 at 0, 0 is applied on a control terminal 7 being connected to an OR gate, and a switch 4 is connected to B side, thereby, frequency division is performed with the loop of the flip-flops 1, 2, and 3, and when the output Q2 is set at 1, the switch 4 is connected to A side, then, the frequency division is performed with the loop of the flip-flops 2 and 3. Meanwhile, when the signal M is set at 1, the frequency divider always performs the frequency division with the loop of the flip-flops 2 and 3.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a frequency divider, and particularly to a variable divider or a 2n
This invention relates to a fixed splitter having a splitting ratio other than the above.

[Conventional technology]

Conventionally, this type of branching device has been constructed of cascade-connected flip-flops, feedback loops, and gate circuits, as shown in FIGS. 6 and 7, for example.

Figure 6 shows 7 lip-flops 1-3 and NOR game)11.
12, and is an example of a conventional variable division divider in which the frequency division ratio of either 1/4 frequency division or 115 frequency division can be selected by control signal M.

On the other hand, Figure 7 shows flip 70 knobs 1 to 3 and NOR game)
This is another example of a conventional variable divider which is configured with 13.14 and can select either division ratio of 115 frequency division or 176 frequency division by control (i-no.M).

Combinations of division ratios of the frequency dividers shown in FIGS. 6 and 7 are shown in Table 1 below.

Table 1 Combinations of frequency division ratios [Problems to be solved by the invention] The conventional frequency divider described above has a gate circuit in the signal feedback loop, so the operable frequency can be reduced by the delay of this feedback loop. The characteristic drawback is that the
As can be seen by comparing the figure and FIG. 7, the disadvantage is that the logical configuration differs greatly depending on the division ratio.

In contrast to the conventional frequency divider described above, the present invention uses a 2-input/1-output switch in place of the logic gate circuit, and changes the number of flip-flop stages in the signal feedback loop isometrically to obtain the desired signal. It has an original content of obtaining the division ratio.

[Means for solving problems]

The branching device of the present invention includes a plurality of master slave flip-flops whose inputs and outputs are connected in a ring oscillator configuration and whose clock inputs operate in synchronization with each other, and a first master slave flip-flop among the plural master slave flip-flops. a 2-input, 1-output switch having two inputs connected to the output and input of the 70-tube, and an output connected to the input of one of the plurality of 70-tube mastersleip flip-flops following the first mastersleip 7-tube; This 2-input 1-output switch is controlled by the output of any one of the plurality of master slave 7 lip flops other than the first master slave 7 lip flop, or by the gate output obtained by logically calculating this output and the control signal. Features.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a logic circuit diagram of a first embodiment of the present invention. In the figure, 1 to 3 are master slave flip 70 blocks, C is a clock signal applied in synchronization to these 7 flip 70 blocks 1 to 3, M is a control signal for selecting the division ratio,
4 is a 2-input, 1-output switch. This switch 4 is
When '1'' (logical value) is applied to the control terminal 7, the input signal is output to the output terminal S, and conversely, when lOn is applied, the input signal B is output to the output terminal S.

When the control signal M is “0”, the output Q of the flip-flop 2! When is 0#, '0# is applied to the control terminal 7 connected to the OR gate 5, the switch 4 is connected to the B side, the clip 70 is divided by the loop of tubes 1 → 2 → 3, and the output is When Q2 is 1'', switch 4 is connected to the A side and the frequency is divided by a loop of 7 lip-flops 2→3.

That is, the half period is divided into 1/6, and the remaining half period is divided into 1/4. Therefore, in one period, 1/(2+3)=
Performs frequency division by 115.

On the other hand, when the control signal M is '1#, 2 inputs OR
The output of gate 5 is always 1, the switch is always connected to the A side, and the frequency divider is 1 in a loop of 7 lip-flops 2→3.
/Divide the frequency by 4. In order to show the above operation, a time chart of this embodiment is shown in FIG.

Similarly, FIG. 2 shows a second embodiment of the present invention.
This is a logic circuit diagram of a variable frequency divider for frequency division and 1/6 frequency division, in which the 2-input OR gate 5 in FIG. 1 is replaced with a 2-input NOR gate 9. A time chart of this embodiment is shown in FIG.

In addition, as a third embodiment of the present invention, as shown in FIG. 3, by adding one 7 lip-flop 8 to the frequency divider shown in FIG. configured.

Here, since the two-input OR gate 5 in FIG. 1 is replaced with the two-input NOR gate 9 in FIG. 2, the third
It is easily understood that by replacing the two-input OR gate 5 shown in the figure with a two-input NOR gate, a 1/7° to 1/8 variable division divider can be constructed.

Table 2 shows the combinations of the division ratios in FIGS. 1 to 3.

Table 2 The combinations of frequency division ratios of the frequency divider of the present invention or more are the OR gate 5 or N which outputs the switch control signal 7.
This is the case when the slave 7 lip 70 cup output is connected to the OR gate 9.

As shown in FIG. 8, when the master flip-flop output Qs of the 7-rip 7-o-tube 3 is connected to the OR gate 5, the same function as in FIG. 1 is obtained. A time chart of the fourth embodiment of the present invention shown in FIG. 8 is shown in FIG. As can be seen from the figure, the output Qf is a signal delayed by half a cycle of the output Q2. Furthermore, it is easy to understand that the use of the master 7 lip-flop output instead of the slave 7 lip-flop output can also be applied to the cases of FIGS. 2 and 3.

Generally, when n-stage flip 70 tubes are used, according to the present invention, a 1/(2n-2), 1/(2n-1) variable splitter or a 1/(2n-1), 1/ It can be seen that a 2n variable branching unit is constructed. Furthermore, by removing the control terminal 6 and gates 5 and 9 in FIGS. 1 to 3, the output Q of 7 lips 70 tubes 2! Alternatively, it is clear that a fixed frequency divider can be constructed by controlling the switch 4 using the output Q.

As described above, in the first to fourth embodiments, OR gate 5 or N
Although the case where the OR gate 9 is used has been described, a frequency divider having a similar function can be obtained by using an AND gate or a NAND gate.

〔Effect of the invention〕

As explained above, the divider of the present invention provides a switch function to the input section of a flip-flop and changes the number of stages of the feedback loop, thereby allowing a fixed divider or a variable divider to be created without inserting a logic gate into the feedback loop. configured. That is, since there is no logic gate in the feedback loop, there is an effect that the maximum operating frequency of the divider can be increased.

Also, by simply adding a 71J lip-flop, if n 7-lip flops are used, 1/(2n
-2), 1/(2n-1) variable frequency divider or 1
/(2n-1), 1/2n variable division divider is constructed, and the frequency divider of the present invention also has the advantage of being widely applicable.

[Brief explanation of the drawing]

1, 2, 3, and 8 are logic circuit diagrams of the first to fourth embodiments of the present invention, and FIGS. 4, 5, and 9 are logic circuit diagrams of the first to fourth embodiments of the present invention, respectively. The time charts of the first, second and fourth embodiments, and FIGS. 6 and 7 are logic circuit diagrams of conventional branching devices. 1.2.3...Master-slave flip-flop, 4...Switch, 5...OR gate, 6...Control signal terminal, 7... ...Switch control proton S9j engineering 1-14...NOR
Gate. M=0 (÷S) M=f (
÷4) 4th bacterium H=o (÷5n M
-/ (-=6) 5th ■ 6th illustration 7 mouth

Claims (1)

[Claims] A plurality of master-slave flip-flops whose inputs and outputs are connected in a ring oscillator configuration, and whose clock inputs operate in synchronization with each other, and an output and an input of a first master-slave flip-flop among the plurality of master-slave flip-flops. a two-input one-output switch having an input connected thereto and an output connected to the input of one of the plurality of master-slave flip-flops following the first master-slave flip-flop, the two-input one-output switch A frequency divider characterized in that the frequency divider is controlled by an output of any one of the plurality of master-slave flip-flops other than one master-slave flip-flop, or a gate output obtained by performing a logical operation on this output and a control signal.