JPS6010923A - Frequency dividing circuit - Google Patents

Abstract

PURPOSE:To obtain a frequency dividing circuit having the capacity for generating a frequency dividing output of one over an optional integral number with simple constitution by inputting an optional number of order of a logical output of DFFs connected in series to the DFF of the 1st stage. CONSTITUTION:When the 3rd clock pulse CP is applied, outputs QB, QC of the DFF21B, 21C go to 1 and an output QND of an NAND circuit goes to 0. When the 4th clock pulse CP is applied, an output QA of the DFF21A goes to 0 and when the 5th clock pulse CP is applied, an output QB of the DFF21B goes to 0 and an output QND of an AND circuit 22 goes again to 1. The outputs QA, QB and QC of the DFF21A, 21B and 21C are an output of period 5T comprising 3T of 1 level and 2T of 0 level (T is the period of the clock pulse), i.e., a frequency dividing output having 1/5 of the clock pulse CP.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a frequency divider circuit that generates an output divided by an integer fraction of an input clock.

(2) Background of the Technology Frequency divider circuits are widely used to obtain a low frequency source from one stable oscillation source that has a synchronous relationship with it and has an arbitrary low frequency relationship.

In addition, the method of obtaining a low-frequency source by dividing the high-frequency source requires smaller components than the method of obtaining a low-frequency source directly.
It is preferred because the overall size is compact and the frequency is stable. Furthermore, a frequency dividing circuit is an indispensable element when obtaining a stable high frequency source having an arbitrary harmonic relationship with respect to one reference oscillation source.

Since frequency divider circuits are thus widely used, efforts have been made to realize a desired frequency divider circuit with a simple configuration.

(3) Prior Art and Problems In general, an N-adic counter functions as a 1/N frequency dividing circuit, so conventionally, a frequency dividing circuit has been constructed by using a counter.

Figure 1 shows 1150 using a conventional synchronous quinary counter.
Frequency divider circuit: FIG. 2 shows a 1/7 frequency divider circuit using a conventional synchronous heptad counter.

In each figure, IIA to llc and 13A to 13C are all JK flip-flops, 12°15 is an AND circuit, 14 and 16 are NAND circuits, CP is a clock pulse, and R
8 is a reset pulse. If a clock pulse CP is now input to the clock pulse input terminal T, the flip
The outputs of the clock pulse CP divided by 115 and 1/7 are sent to the outputs Qc of the flops IIC and 13C, respectively.

As is clear from the figure, the circuit configuration of the 1/7 frequency divider is more complicated than that of the 115 frequency divider. Moreover, the larger the frequency division ratio is, the more complicated the circuit configuration of the conventional frequency division circuit becomes, which is extremely disadvantageous.

Furthermore, when a synchronous counter is used, it is difficult to increase the maximum repetition frequency of the clock pulse CP due to the delay in the carry system, and there is a problem that the frequency division operation cannot be made faster.

(4) Object of the Invention The object of the present invention is to provide a high-speed frequency divider circuit that eliminates the drawbacks of conventional frequency divider circuits using counters and can generate a frequency divided output of any integer fraction with a simple circuit configuration. is to provide.

(5) Structure of the Invention In order to achieve the above-mentioned object, the present invention comprises N delay-synchronized flip-flops connected in series, and arbitrary second and Q-th flip-flops of the flip-flops.・By taking the output of the flop and inputting the logical output of both outputs to the first stage flip-flop, each flip-flop generates a divided output of 1/(P+Q) of the clock pulse frequency. It is characterized by this.

(6) Embodiments of the Invention 1 Embodiments of the present invention will be described in detail based on FIGS. 3 to 8.

FIG. 3 is a block diagram of an embodiment of the present invention regarding a 115 frequency divider circuit, and FIG. 4 is an operational waveform diagram thereof.

In Figure 3, 20 is a 115 frequency divider circuit, 2IA, 21
B and 21C are delay-synchronized flip-flops (hereinafter referred to as D
(referred to as FF). T is the input terminal of the clock pulse cp, D
is a signal input terminal, Q6 to Qc are output terminals or outputs, 01
~0c is a negative output terminal or output of Q11~Qc, and 22 is a NAND circuit.

DFF21A to 21C all use clock pulse C.
When P is applied to the clock terminal T, the input state applied to the signal input terminal at that time is changed to the next clock pulse C.
A typical example of a flip-flop is a D-type flip-flop, which outputs to the output terminal Q A "Q c until R is applied.
It is well known that it can be constructed using 3T type flip-flops, JK type rough flip-flops, etc., and the DFF of the present invention naturally includes these types and is not limited to D type flip-flops. .

FIG. 5 shows a well-known D-type flip-flop using an R3T-type flip-flop.
3 is an R3T flip-flop, and 24 is an inverter (or knot circuit). The circuit in Figure 5 is a D-type flip.
Since it is well known that it operates in the same way as a flop, a detailed explanation of its operation will be omitted.

Next, the frequency division operation shown in FIG. 3 will be explained with reference to the operation waveform diagram shown in FIG. 4.

When a clock pulse cp is applied to the clock input terminals T of DFFs 21A to 21C, DFF 21A receives the first clock pulse CP 1 , DFF 21B receives the second clock pulse CP2, and DFF 21C receives the third clock pulse CP3, respectively. Generates a "1" output.

During this time, since the output QNCI of the NAND circuit 22 is rlJ, "1" is input to the signal input terminal of the DFF 21A.

At the time when the third clock pulse CP3 is applied, D
The outputs QB and Qc of FF21B and 21C are both “1”.
”, so the output QND of the NAND circuit 22, that is, D
The input of FF21A becomes "0".

Therefore, when the next clock pulse CP4 is applied, the output Q^ of the DFF 21A becomes "0". below,
The output QB of the DFF 21B becomes "0" at the time when the clock pulse CPs is applied.

When the clock pulse CPs is applied, the output Q of the DFF 21B [I becomes rOJ, the output Q of the NAND circuit 22
ND, that is, the input of the DFF 21A becomes "1" again.

Therefore, when clock pulse CPe is applied, DFF
The output QA of 21A becomes "1" again, and the above-described operation is repeated.

Referring to FIG. 4, as is clear from the above explanation,
When the period of the clock pulse CP is T, the outputs QA to Qc of each DFF21A to 21C are outputs with a period of 5T, where the "1" period is 3T and the "0" period is 2T, that is, the clock pulse frequency of the clock pulse CP. 11
The output is divided by 5.

In addition, each DFF21A to 21C has a clock pulse CP.
Although the description has been made assuming that the circuit operates on the rising edge of , even if it operates on the falling edge of , the output waveforms in FIG. 4 are only shifted to the right by T/2, and there is no difference in the frequency dividing operation.

FIG. 6 shows one embodiment of the general form of the frequency divider circuit of the present invention having a frequency division ratio of 1/an arbitrary integer. N DFFs 25A to 25M to 25N are connected in series, and the output QM of the M-th and N-th DFFs 25M and 25N,
QN is supplied to a NAND circuit 26.

To explain the operation of FIG. 6 together with the operation waveform diagram of FIG. 7, until the Nth clock pulse CP N is applied, D
Since the output QN of the FF 25N is "0'1", the output QND of the NAND circuit 26, that is, the input applied to the signal input terminal of the first stage DFF 25A is "1".

The output QM of DFF25M is the Mth clock pulse C
It becomes "1" when PM is added, and the output QN of the DFF 25N becomes "1" when the Nth clock pulse CPN is added.

Therefore, at the time when the Nth clock pulse CPN is applied, the output QNO of the NAND circuit 26, that is, the DFF
The input of 25A becomes "0".

As a result, the output QA of the DFF25A changes from "1" to "0" at the N+1st clock pulse CPN+1, and
The output QM of FF25M changes from "1" to "0" at the N+Mth clock pulse CPN0M, and the output QN of the DFF25N changes from "1" to "1" at the 2Nth clock pulse CP2N.
” becomes “0”.

Since the output QM of the DFF 25M becomes "0" when the iN+Mth clock pulse CPN0M is added, the output QNO of the NAND circuit 26, that is, the input of the DFF 25A changes from "0" to "1" again.

Therefore, the output Qn of the DFF25A becomes "
The value changes from "0" to "1" again, and the above-described operation is repeated thereafter.

Referring to FIG. 7, as is clear from the explanation so far, the outputs Q^, Q of each DFF 25A, 25M, 25N
Both M and Qx are outputs with a period (M+N)T in which the "1" period is NT and the "0" period is MT, that is, 1/CM of the clock pulse frequency 6 of the clock pulse CP.
+N) frequency divided output.

By changing M between 1 and N, a cross-sectional frequency division output can be obtained from each DFF. The circuit configuration basically does not change even if the frequency division ratio increases, so compared to conventional frequency divider circuits where the circuit configuration becomes more complicated as the frequency division ratio increases, the circuit configuration is extremely simple. A frequency divider circuit with .

In addition, since there is no logic circuit between each DFF like in conventional frequency divider circuits, the delay in the carry system is reduced, making it possible to increase the maximum repetition frequency of clock pulses, that is, to speed up the frequency division operation. can.

FIG. 8 shows still another embodiment of the present invention.

The circuit configuration in FIG. 8 is the same as the circuit in FIG.
Each DFF25A to 25N is connected via these selector switches.
The configuration is such that it is connected to the output terminal of the 6th
Same as the figure. Common terminal 2 of changeover switch 27.28
7p and 28p are connected to the input side of the NAND circuit 26, and switching terminals 27a to 27n and 28a to 28n are connected to D
Connected to output terminals Q^ to QN of FF25A-DFF25N.

In this configuration, each DFF 25A to 2
5N can send out a frequency-divided output having a frequency division ratio of 1/2 of an arbitrary integer between 172 and 1/2N of the clock pulse CP.

For example, if the selector switch 27 is connected to the output Qp of the P-th DFF 25p and the selector switch 28 is connected to the output QA of the Q-th DFF 25Q, a divided output with a frequency division ratio of 1/(P+Q) can be obtained from each DFF. be able to. These frequency division operations are similar to those shown in FIG.

Although the embodiments of the present invention have been described above, the NAND circuits 22 and 26 may be constructed from other logic circuits such as NOR circuits, or may be constructed from an AND circuit or a combination of an OR circuit and a NOT circuit. Also, the output Q of the negative output terminal of each DFF
It can also be configured in combination with A""QN.

(7) As described in detail, according to the present invention, an output having a frequency division ratio of 1/an arbitrary integer can be generated by each flip with a simple circuit configuration.
A frequency divider circuit that outputs from a flop can be realized. Even if the frequency division ratio increases, the circuit is not complicated in any way, and it is extremely easy to change the frequency division ratio. Since the frequency division ratio can be changed simply by changing the connection of the output terminal without changing the basic circuit configuration, it is easy to integrate the frequency division circuit. Furthermore, even if the frequency division ratio is changed or increased, each DFF is always directly connected and no logic circuit is inserted between them, so the maximum repetition frequency of clock pulses can be increased and the frequency division operation can be increased. It can be made faster.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional 115 frequency divider circuit, Figure 2 is a block diagram of a conventional 1/7 frequency divider circuit, Figure 3 is a block diagram of a 115 frequency divider circuit of the present invention, and Figure 4 is a block diagram of a conventional 1/7 frequency divider circuit. 3 is an operating waveform diagram, FIG. 5 is a block diagram of a D-type flip-flop using R3T flip-flops, FIG. 6 is a general block diagram of the frequency divider circuit of the present invention, and FIG. FIG. 8 is a block diagram of another embodiment of the general frequency divider circuit of the present invention. 11A-IIC, 13A-13G...JK flip-flop, 12, 15...AND circuit,
14.22,26... NAND circuit, 20...
...115 frequency divider circuit, 21A to 21C, 25A, 25
M, 25N...Delayed flip-flop (D
F F), 23...R3T flip-flop, 24...Inverter (knot circuit), 27
．． 28......Selector switch. Patent applicant Fujitsu Ltd.

Claims (1)

[Claims] 1. Take out the outputs of N delay-synchronized flip-flops connected in series and the arbitrary P-th and Q-th flip-flops of these flip-flops, and calculate the output of both. A frequency divider circuit characterized in that by inputting a logic output to a first-stage flip-flop, each flip-flop generates a divided output of 1/(P+Q) of a clock pulse frequency. 2. The frequency dividing circuit according to claim 1, wherein the values of P and Q of the logic circuit are fixed values. 3. The frequency dividing circuit according to claim 2, wherein at least one of P and Q of the logic circuit is N. 4. The frequency dividing circuit according to claim 1, wherein at least one of P or Q of the logic circuit is variable.