JPH03198417A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To set an arbitrary extent of delay and to reduce the circuit scale by setting the extent of delay without changing a minimum unit of the settable extent of delay. CONSTITUTION:A frequency dividing circuit 1 which divides the frequency of a minimum clock MCK to 1/2, 1/4, and 1/8 divided clocks C1 to C3, flip flops (delay elements) F1 to F3 which are operated based on clocks C1 to C3 respectively, a delay extent setting circuit 2 which generates control signals S1 to S3 to set the extent of delay, and switch circuits 3A to 3C which are switched by control signals S1 to S3 from the delay extent setting circuit 2 are provided. Connection of delay elements which take plural clocks C1 to C3, which are obtained by frequency division of the minimum clock MCK, as respective extents of delay is set. Thus, the extent of delay is easily freely set from a small extent to a large extent by the small number of circuit constituting elements.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital delay circuit, and particularly to a digital delay circuit that sets a delay amount without changing the minimum unit of the settable delay amount.

[Conventional technology]

Conventionally, such digital delay circuits have been constructed using shift registers made up of a plurality of flip-flops.

FIG. 6 is a diagram of a digital delay circuit showing an example of such a conventional technique.

As shown in FIG. 6, the conventional digital delay circuit consists of flip-flops F1 to Fm to which input data Din is input.
A shift register composed of ``'c and a delay amount setting circuit 2
and a select switch 21 that switches and applies a predetermined delay amount in response to a signal from the delay amount setting circuit 2, and obtains a digital/delay output DA. Note that MCK is a clock.

[Problem to be solved by the invention]

In the conventional digital delay circuit described above, the minimum unit of the μ extension that can be set is one period of the shift register clock (MCK), so if a large delay amount is expected, the shift register It is necessary to increase the number of stages, and the scale of the select switch and delay amount setting circuit for switching the delay amount increases accordingly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital delay circuit which can arbitrarily set the amount of delay and which can be configured to have a small circuit scale.

[Means to solve the problem]

The digital delay circuit of the present invention includes a delay amount setting circuit that generates a control signal for selecting and setting a delay amount, and a clock that provides a minimum delay amount, and a plurality of different periods obtained by dividing this clock. It has a frequency dividing circuit that generates a divided clock, and a plurality of delay elements each having a delay amount corresponding to one period of the plurality of frequency divided clocks, and sets the amount of delay based on a signal from the delay amount setting circuit. It is characterized by

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a digital delay circuit diagram showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment includes a frequency dividing circuit 1 which divides the minimum clock MCK and outputs clocks 01 to C3 whose frequencies are divided into 1/2, 1/4° and 1/8, respectively; Flip-flops F1 to F3 each operate based on clocks C1 to C3, and control signals 81 to S3 that set the amount of delay.
It has a delay amount setting circuit 2 that generates the delay amount setting circuit 2, and switch circuits 3A to 3C that are respectively switched by control signals 81 to S3 from the delay amount setting circuit 2. These switch circuits 3A to 3C, when the control signals 81 to S3 are "H",
It is assumed that input B is selected and input A is selected when II L II. In addition, DIN is a digital input, D O
UT is the delayed digital output.

FIG. 2 is a diagram showing the relationship between the set delay amount and the set signal in FIG. 1.

As shown in FIG. 2, the relationship between the values of the control signals 81 to S3 of the delay amount setting circuit 2 and the delay amounts O to 7T from the input DIN to the delay circuit to the output DoU is shown here.

In Fig. 3, the delay amount in Fig. 1 is 3T, that is, Sl-"L"'
, S2-“'H” indicates the operation of S3='“H”.

In this embodiment, the number of flip-flops for setting the delay is three, but when the number of flip-flops is n, the amount of delay that can be set is 0 to (2''-1)T.
It is. Furthermore, in order to realize the same amount of delay with the conventional circuit (FIG. 6), (2'-1>> flip-flops are required.

FIG. 4 is a circuit diagram of the main part of a digital delay circuit showing a second embodiment of the present invention.

As shown in FIG. 4, this embodiment includes a frequency divider circuit 1 which receives a minimum clock MCK and generates clocks 01 to C3 of different cycles, and three flip-flops D1 having a clock power C and a control power S. -D3, and the delay amount setting circuit is the same as that of the first embodiment described above, so it is omitted, and only the outputs of the control signals S1 to S3 are shown.

FIG. 5 is a specific circuit diagram of the flip-flop circuit shown in FIG. 4.

As shown in FIG. 5, if the control signal S input is "H",
It performs normal flip-flop operation, gives input data I a delay according to the clock input, and outputs digital data O. Conversely, when the S input is "L", transfer gates 17 to 20 are all "'On" and the delay amount is 0.The delay amount and delay amount setting in FIGS. 4 and 5 The relationship between the circuit control signals 81 to S3 is as shown in FIG. 2, the same as in the first embodiment described above.

〔Effect of the invention〕

As explained above, the digital delay circuit of the present invention has
By setting the connection of delay elements each using multiple clock signals obtained by frequency-dividing a clock that provides the minimum unit of delay, it is possible to easily change from small to large delays with a small number of circuit components. This has the effect of allowing you to freely set the amount.

[Brief explanation of drawings]

FIG. 1 is a digital delay circuit diagram showing the first embodiment of the present invention, FIG. 2 is a diagram showing the relationship between the set delay amount and the setting signal in FIG. 1, and FIG. 3 is a diagram showing the circuit operation of FIG. 1. 4 is a digital delay circuit diagram showing a second embodiment of the present invention, FIG. 5 is a specific circuit diagram of the flip-flop shown in FIG. 4, and FIG. 6 is a timing diagram of various signals for explanation. 1 is a diagram of a digital delay circuit showing an example of the conventional art. 1... Frequency dividing circuit, 2... Delay amount setting circuit, 3A~3
C... switch circuit, F1 to F3. Di~D3...
D-type flip-flop, 10.11...NAND gate, 12-16...inverter, 17-20...transfer gate, S, ~S3...control signal, C1~
C3...Clock.

Claims (1)

[Claims] A delay amount setting circuit that generates a control signal for selecting and setting the amount of delay, and a frequency divider that receives a clock that provides the minimum amount of delay and generates divided clocks with a plurality of different periods by dividing this clock. A digital delay circuit comprising: a circuit; and a plurality of delay elements each having a delay amount corresponding to one period of the plurality of frequency-divided clocks, and setting the delay amount based on a signal from the delay amount setting circuit. .