JPH0884069A - Variable frequency divider - Google Patents

Abstract

PURPOSE: To provide frequency division output whose duty factor is approximately 50% and level is stable regardless of a set frequency division number. CONSTITUTION: A first down counter part 89 counts the pulse number of internal frequency division signals Q' for a number P set in frequency division number setting terminals 55 to 58. A second down counter part 1 counts the pulse number of the internal frequency division signals Q' for the number P/2 set in the frequency division number setting teminals 56 to 58. A reset/output generation circuit 42 outputs an 'L' level corresponding to that the second down counter part 1 ends counting and outputs an 'H' level corresponding to that the first down counter part 89 ends the counting. Thus, the duty factor of the frequency division output OUT becomes approximately 50%.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable frequency divider, and more particularly to a variable frequency divider capable of arbitrarily setting a frequency division number.

[0002]

2. Description of the Related Art FIG. 8 shows a block diagram of a conventional variable frequency divider.
It is a lock figure. With reference to FIG. 8, this variable frequency divider is
Input terminal 51, output terminal 52 and a plurality (six in the figure)
The frequency division number setting terminals 53 to 58 are provided. To the input terminal 51
A clock signal CLK to be divided is input to the.
The divided signal OUT is output from the output terminal 52.
It The frequency division number setting terminals 53 to 58 have the frequency division number K of
First to sixth digit numbers S1 ', S2', P1 to P4
This is a terminal for setting to "1" or "0". Division
The number K is K = S1 ′ + 2 × S2 ′ + 2²× P1 + 2³× P
2 + 2^Four× P3 + 2 ^FiveIt is represented by × P4. Below, variable
When explaining the operation of the frequency divider, unless otherwise specified, S
1 '= 1, S2' = 1, P1 = 1, P2 = 0, P3 =
0, P4 = 0, that is, the frequency division number K is (100111)₂
= 39 is set.

The variable frequency divider further comprises a 2-modulus prescaler (4/5 frequency divider) 61, a 2-bit swallow counter 62, a 4-bit pulse counter 63 and a reset / output generation circuit 64.

As shown in FIG. 9, the 2-modulus prescaler 61 includes NOR gates 71 and 74 and a data flip-flop circuit (hereinafter abbreviated as DF-F) 72 ,.
73,75 are included. The clock terminals C of the DF-Fs 72, 73 and 75 receive the clock signal CLK. DF-F72
Is output to the input terminal D of the DF-F73. OR
The gate 74 receives the inverted output of the DF-F 73 and the select signal SEL, and outputs the signal φ74 to the input terminal D of the DF-F 75. The OR gate 71 is a DF-F 73,7.
5 outputs Q73 and Q75 and outputs signal φ71 to DF-F
It outputs to the input terminal D of 72. The inverted output of the DF-F73 becomes the inner partial frequency signal Q '.

FIG. 10 is a time chart showing the operation of the 2-modulus prescaler 61. Referring to FIGS. 9 and 10, when the swallow counter 62 finishes counting and the select signal SEL becomes “H” level at the same time, N
The output φ74 of the OR gate 74 is fixed to the “L” level, and the output Q75 of the DF-F75 is also “L” one clock later.
Fixed to the level. As a result, the OR gate 71 and the DF-Fs 72, 73 become the OR gate 74 and the DF-F.
Configure a divide-by-4 divider independent of 75. Therefore, the internal partial frequency signal Q ′ has two clocks in the “H” period and two in the “L” period while the select signal SEL is at the “H” level.
It is a clock divided by four signal.

If the select signal SEL becomes "L" level at the same time when the swallow counter 62 starts counting,
The output φ74 of the NOR gate 74 is the output Q of the DF-F73.
73, and the output Q75 of DF-F75 is signal φ
74 is delayed by one clock. NO at this time
The output φ71 of the R gate 71 falls due to the rise of the signal Q73 and rises due to the fall of the signal Q75 which is delayed by one clock from the signal Q73. Becomes DF
The output Q73 of -F73 is the signal φ71 delayed by two clocks. The internal partial frequency signal Q ′, which is the inverted output of the DF-F73, has an “H” period of 3 clocks and an “L” period of 2 while the select signal SEL is at the “L” level.
It becomes a clock divided by 5 signal.

As shown in FIG. 11, the swallow counter 62 includes gate elements 76 and 77, an inverter 78, NOR gates 79 to 82 and 87, OR gates 83 and 84, and a toggle flip-flop circuit with set / reset (hereinafter, referred to as "toggle flip-flop circuit").
(Abbreviated as TF-F) 85 and 86. Gate element 7
Reference numerals 6 and 77 each include a terminal for directly outputting the signal input from the input terminal and a terminal for inverting and outputting the signal input from the input terminal.

The input terminals of the gate elements 76 and 77 are connected to the frequency division number setting terminals 53 and 54, respectively. The outputs of the gate elements 76 and 77 are input to one input terminals of NOR gates 79 and 81. The inverted outputs of the gate elements 76 and 77 are input to one input terminals of the NOR gates 80 and 82. The other input terminals of the NOR gates 79 to 82 receive the reset signal SCRST inverted by the inverter 78. The reset signal SCRST is output from the reset / output generation circuit 64.

The outputs of the NOR gates 79 and 81 are input to the reset terminals R of the TF-Fs 85 and 86, respectively.
The outputs of the NOR gates 80 and 82 are TF-F8, respectively.
It is input to the set terminals S of 5,86.

The output of TF-F85 is input to the clock terminal C of TF-F86. The NOR gate 87 is TF-
Upon receiving the outputs of F85 and F86, it outputs the counter output signal SCO. The OR gate 83 has a reset signal SCRST.
And a counter output signal SCO to receive a select signal S
Output EL. The OR gate 84 uses the reset signal SC
Receives RST, counter output signal SCO and inner partial frequency signal Q '. The output φ84 of the OR gate 84 is TF-F
It is input to the clock terminal C 85.

FIG. 12 is a time chart showing the operation of the swallow counter 62. 11 and 12, when reset signal SCRST is at "L" level, the outputs of NOR gates 79 to 82 are fixed to "L" level. When the count by the pulse counter 63 is completed and the reset signal SCRST becomes “H” level, N
The outputs of the OR gates 79 and 81 are at "L" level, and N
The outputs of the OR gates 80 and 82 become the "H" level. Therefore, both TF-F85 and 86 are preset to "H" level ("1"), and the count output SCO becomes "L" level.

When the reset signal SCRST goes to "L" level, the output φ84 of the OR gate 84 becomes equal to the internal partial frequency signal Q ', the TF-Fs 85 and 86 start counting, and the select signal SEL goes to "L" level. become. TF
The output of -F85 is inverted every time the internal frequency-divided signal Q'rises from "L" level to "H" level. TF-F86
The output of TF-F85 is "H" from "L" level.
Inverts every time you rise to a level.

When the count is completed and the outputs of TF-F85 and 86 are both at the "L" level, the count output signal S
CO becomes "H" level, and signals SEL and φ84 become "H" level. Therefore, the select signal SEL
Becomes "L" level during the period from the falling of the reset signal SCRST to the rising of the count output signal SCO.

FIG. 13 is a circuit block diagram showing configurations of the pulse counter 63 and the reset / output generation circuit 64. Referring to FIG. 13, the pulse counter 63 has an input unit 8
8 and a down counter unit 89. The input section 88 includes gate elements 91 to 94 and NOR gates 95 to 102, and the down counter section 89 includes TF-F103 to 106.
And an OR gate 107.

The input terminals of the gate elements 91 to 94 are connected to the setting terminals 55 to 58, respectively. Gate element 91
The outputs of ~ 94 are NOR gates 95, 97, 99, 10
1 is input to one input terminal. Gate elements 91-94
The inverted output of the NOR gates 96, 98, 100, 10
2 is input to one input terminal. NOR gates 95-1
The other input terminal of 02 receives the preset signal R ′ from the output section 90. NOR gates 95, 97, 99, 101
The outputs of the above are input to the reset terminals R of the TF-Fs 103 to 106, respectively. NOR gates 96, 98, 10
The outputs of 0 and 102 are TF-F 103 to 106, respectively.
Is input to the set terminal S of.

The clock terminal C of the TF-F 103 receives the internal partial frequency signal Q '. The outputs of the TF-Fs 103 to 105 are input to the clock terminals C of the TF-Fs 104 to 106 of the next stage, respectively. The OR gate 107 is TF-F1.
03 output Q1 and TF-F104 inverted output / Q2
And the output Q3 of the TF-F105 and the output Q4 of the TF-F106.

The reset / output generation circuit 64 also includes an output section 90 and an inverter 108, and the output section 90 has an O level.
R gates 109 and 112 and DF-F110 and 111
including. The OR gate 109 receives the output D ′ of the OR gate 107 and the inverted output of the DF-F 110. The output of the OR gate 109 is input to the input terminal D of the DF-F110. The output of the DF-F110 is input to the input terminal D of the DF-F111. The output of the DF-F111 becomes the preset signal R ', and the inverted output of the DF-F111 becomes the reset signal SCRST. The OR gate 112 is DF-
Receives the inverted output of F110 and 111. OR gate 11
The output of 2 becomes the output OUT of the variable frequency divider.

14 and 15 are time charts showing the operation of the reset / output generation circuit 64. FIG.
3, FIG. 14 and FIG. 15, when preset signal R ′ attains “L” level, frequency division number setting terminals 55-5
NOR gate 95, depending on the set level given to
The output of 98, 100, 101 becomes "L" level, and N
The outputs of the OR gates 96, 97, 99 and 102 are at "H" level. Therefore, TF-F103 ~ 106,
The preset values are “H” level (“1”), “L” level (“0”), “L” level (“0”), and “H” level (“1”), respectively.

When the preset signal R'becomes "H" level, the down counter section 89 starts counting. TF
The outputs of -F103 to 106 are inverted each time the input to each clock terminal C rises from the "L" level to the "H" level. The output of the OR gate 107, that is, the count output signal D ′ is TF-F 103, 105, 106.
Output Q1, Q3, Q4 and inverted output of TF-F104
It becomes the "L" level during the period when both Q2 are at the "L" level, that is, the period two counts before the count of the down counter unit 89 ends. The inverted output POUT of the DF-F110 becomes “H” level in response to the first falling of the signal Q ′ after the signal D ′ becomes “L” level,
It goes to "L" level in response to the second fall of signal Q '.

The inverted output SCRST of the DF-F111 is
After the signal D ′ becomes the “L” level, it becomes the “H” level in response to the second falling of the signal Q ′, and the signal Q ′ becomes 3
It goes to the “L” level in response to the falling of the third time.

The output OUT of the OR gate 112 becomes "H" level in response to the second fall of the signal Q'after the signal D'becomes "L" level, and the third rise of the signal Q '. The level becomes “L” in accordance with the decrease.

That is, the output OUT is a down counter.
Part 89 is preset value (1001) ₂Count = 9
The "H" level for only 2 counts during the period.

As mentioned above, the first (11) of the signal Q '
₂ = 3 counts are obtained by dividing the clock signal CLK by 5
It is a frequency-divided signal, and the remaining 6 counts of the signal Q ′ are a frequency-divided 4 signal obtained by dividing the clock signal CLK by 4. Therefore, the output OUT becomes the “H” level for 2 × 4 = 8 clocks out of 3 × 5 + 6 × 4 = 39 clocks, which is the clock signal CLK divided by (100111) ₂ = 39.

[0024]

When the frequency-divided output OUT of the variable frequency divider is used for communication, the duty ratio of the frequency-divided output OUT is 50 from the viewpoint of power efficiency.
%, Preferably constant.

However, in the conventional variable frequency divider, the set frequency division number K is the period during which the frequency division output OUT is at "H" level.
Since the down counter unit 89 is fixed to the period for counting 2 regardless of the above, there is a problem that the duty ratio of the frequency division output OUT becomes smaller as the set frequency division number K becomes larger and the power efficiency becomes worse.

That is, when the set frequency division number K is in the range of 32 to 63, the “H” period of the frequency division output OUT is 2 counts × 4 clocks = 8 clocks, and one cycle of the frequency division output OUT is K clocks. Therefore, the duty ratio is (8 / K) x 1
It becomes 00 (%). For example, the set frequency division K is (1000
00) ₂ = 32, the duty ratio is (8/32) ×
Although 100 = 25%, the set frequency division number K is (11110
1) When ₂ = 61, the duty ratio is 13%. When the set frequency division number K is in the range of 32 to 63, the duty ratio is 1
It changes within the range of 3 to 25%, and if 50% is used as a reference, it is -3
It varies from 7 to -25%.

Further, in the conventional variable frequency divider, the logical sum of two signals POUT and SCRST that do not overlap each other is used as the frequency division output OUT, so that the frequency division output OUT is spiked as shown in FIG. It caused malfunction of the device.

Therefore, a main object of the present invention is to provide a variable frequency divider capable of obtaining a frequency division output having a duty ratio of about 50% and a stable level regardless of the set frequency division number. is there.

[0029]

A variable frequency divider according to the present invention is a variable frequency divider capable of arbitrarily setting a frequency dividing number, and a frequency dividing number setting means for setting the frequency dividing number, A first counter that outputs a first count signal in response to counting the number of pulses of the input signal by half the frequency division number set by the frequency division number setting means, the frequency division number setting means The second counter that outputs the second count signal in response to counting the number of pulses of the input signal by the number of frequency divisions set in step 1, and the period until the first count signal is output is the first Is output, and an output circuit that outputs a signal of the second level is provided during a period from the output of the first count signal to the output of the second count signal. I am trying.

Further, the frequency division number setting means sets the first to Mth frequency division number setting terminals for setting the first to Mth digits of the frequency division number to the first or second logic, respectively. Including,
The first counter counts the number of pulses of the input signal by the number of M-1 digits set at the second to Mth frequency division number setting terminals, and the second counter counts the first to Mth. The number of pulses of the input signal may be counted by the number of M digits set by the frequency division number setting terminal.

Further, the first count signal is set to the input signal in response to the first digit of the frequency division number set at the first frequency division number setting terminal being the first logic. A delay circuit for delaying by a time corresponding to a half cycle and outputting to the output circuit may be provided.

Further, the frequency division number setting means sets the first to Mth frequency division number setting terminals for setting the first to Mth digits of the frequency division number to the first or second logic, respectively. Including,
The number of the input signal is set to 2 ^N by the number of N-digit pulses set at the 1st to Nth (where N <M) frequency division number setting terminals.
The first counter is provided with a signal generating means for outputting a second ^divided signal obtained by dividing the input signal by 2 ^N times after outputting the first divided signal obtained by dividing by +1 times. N + 2
From the Mth frequency division number setting terminal, the number of pulses of the first and second frequency division signals is counted by the number of MN-1 digits set by the Mth frequency division number setting terminal, and the second counter counts from the (N + 1) th to the Mth. The number of pulses of the first and second frequency division signals may be counted by the number of MN digits set by the frequency division number setting terminal of.

Further, the first count signal is set to the second value in accordance with the fact that the N + 1th digit of the frequency division number set at the N + 1th frequency division number setting terminal is the first logic. A first delay circuit that delays by a time corresponding to a half cycle of the divided signal and outputs the delayed signal to the output circuit may be provided.

Further, when the Nth digit of the frequency division number set at the Nth frequency division number setting terminal is the first logic, the second count signal is changed to the second count signal. A second delay circuit that delays by a time corresponding to a half cycle of the divided signal and outputs the delayed signal to the output circuit may be provided.

[0035]

In the variable frequency divider of the present invention, the first counter that counts the number of pulses of the input signal by 1/2 of the set frequency division number and the number of pulses of the input signal by the set frequency division number And a second counter for outputting a signal of the first level during the counting period of the first counter, and from the end of the counting of the first counter to the end of the counting of the second counter. The second level signal is output to. Therefore, the duty ratio is 5 regardless of the set frequency division number.
It is possible to obtain a frequency-divided output with 0% and a stable level.

Further, first to Mth setting terminals for setting the first to Mth digits of the frequency division number are provided, and the first counter is set to the Mth to Mth setting terminals by the second to Mth setting terminals. If it counts by -1 digit and the second counter counts by M digits set by the 1st to Mth setting terminals, an arithmetic unit for halving the set frequency division number It is possible to easily count 1/2 of the set frequency division number without providing such as.

If the first digit of the set frequency division number is the first logic, a delay circuit for delaying the first count signal by a half cycle of the input signal is provided. When the set frequency division number is odd, the output time of the signal of the first level can be extended by the time corresponding to a half cycle of the input signal, and the duty ratio of the frequency division output can be set to 50%.

Further, only the first to Mth setting terminals for setting the first to Mth digits of the frequency division number and the Nth digit pulse number set by the first to Nth setting terminals are used. Input signal 2
^A first frequency-divided signal that is frequency-divided by ^N + 1 times and then outputs a first frequency-divided signal that is frequency-divided by 2 ^N times the input signal. 1st as many as M-N-1 digits set from the N + 2 to Mth setting terminals
And the number of pulses of the second frequency-divided signal is counted, and the second counter is set to Mth setting terminals from the (N + 1) th to Mth setting terminals.
If the number of pulses of the first and second frequency-divided signals is counted by the number of -N digits, the input signal can be frequency-divided in two stages, and a large frequency division number can be set. Also, the first
Also, it is possible to easily count 1/2 of the number of pulses of the first and second frequency-divided signals without providing an arithmetic unit or the like that halves the number of pulses of the second frequency-divided signal.

Further, according to the fact that the (N + 1) th digit of the set frequency division number is the first logic, the first delay for delaying the first count signal by a time corresponding to a half cycle of the second frequency division signal. By providing a circuit, when the number of pulses of the first and second frequency-divided signals is an odd number, the output time of the signal of the first level can be extended by the time corresponding to a half cycle of the second frequency-divided signal. Therefore, the duty ratio of the frequency division output can be brought close to 50%.

A second delay circuit for delaying the second count signal by a half cycle of the input signal is provided in accordance with the Nth digit of the set frequency division number being the first logic. For example, when the number of pulses of the first frequency-divided signal is large, the output time of the signal of the second level can be extended by the time corresponding to a half cycle of the second frequency-divided signal, and the duty ratio of the frequency-divided output can be reduced. Fifty
It can be close to%.

[0041]

【Example】

[Embodiment 1] FIG. 1 is a circuit block diagram showing a configuration of a main part of a variable frequency divider according to a first embodiment of the present invention.

Referring to FIG. 1, this variable frequency divider comprises a 4-bit pulse counter 41 and a reset / output generation circuit 4.
Including 2 and. The pulse counter 41 and the reset / output generation circuit 42 correspond to the pulse counter 63 and the reset / output generation circuit 64 of FIG. 8, and the overall configuration of the variable frequency divider is the same as that of the conventional one shown in FIGS. It is the same as the variable frequency divider.

The pulse counter 41 includes an input unit 88, a first
Down counter section 89 and second down counter section 1. Input unit 88 and first down counter unit 8
Since 9 is the same as that shown in FIG. 13, the description is omitted.

The second down counter section 1 has a TF-F5
.About.7 and OR gate 8. The reset terminals R of TF-F5 to 7 are NOR gates 97, 99 and 10, respectively.
Receives the output of 1. The set terminal S of TF-F5-7 is
The outputs of NOR gates 98, 100 and 102 are received, respectively. The clock terminal C of TF-F5 has an internal partial frequency signal Q '.
Receive. The outputs of TF-F5 and 6 are T of the latter stage, respectively.
It is input to the clock terminals C of F-F6 and 7. The OR gate 8 receives the output Q5 of TF-F5, the inverted output / Q6 of TF-F66, and the output Q7 of TF-F7, and outputs the second count output signal D2 '.

Reset / output generation circuit 42 includes an inverter 108, a first output section 2 and a second output section 3. The first output unit 2 includes an OR gate 9 and a DF-F1.
The second output section 3 includes OR gates 12, 1
5 and DF-F 13, 14, 16.

The clock terminals C of the DF-Fs 10, 11, 13, and 14 receive the signal / Q 'obtained by inverting the internal partial frequency signal Q'in the inverter 108. The OR gate 9 receives the second counter output signal D2 ′ output from the second down counter unit 1 and the inverted output of the DF-F10. O
The output of the R gate Q is input to the input terminal D of the DF-F10. The output of DF-F10 is the input terminal D of DF-F11.
Is input to The inverted output of DF-F11 becomes the output POUT2 of the first output unit 2.

The OR gate 12 receives the first count output signal D'output from the first down counter section 89,
It receives the inverted output of DF-F13. The output of the OR gate 12 is input to the input terminal D of the DF-F13. DF-
The output of F13 is input to the input terminal D of the DF-F14 at the next stage. The output of the DF-F14 becomes the preset signal R'and the inverted output of the DF-F14 is the reset signal SCRST.
Becomes The OR gate 15 has an inverted output P of the DF-F 14.
OUT and an output POUT2 of the first output unit 2 are received. The output of the OR gate 15 is input to the clock terminal C of the DF-F 16. The input terminal D and the inverting output terminal / Q of the DF-F16 are connected to each other. The output of the DF-F16 becomes the output OUT of the variable frequency divider.

FIG. 2 is a time chart showing the operation of the variable frequency divider of FIG. Referring to FIGS. 1 and 2, when preset signal R ′ attains to “L” level, setting terminals 55-
The preset value (1001) _{2 of} 58 is input to the first down counter unit 89 via the input unit 88, and the setting terminal 5
The preset value (100) _{2 of} 6 to 58 is input to the second down counter unit 1. The preset value (100) ₂ of the setting terminals 56 to 58 is 1/2 of the preset value (1001) ₂ of the setting terminals 55 to 58. However, the numbers after the decimal point are truncated.

When the preset signal R'rises to the "H" level, the first and second down counter units 89, 1 start counting. TF-F103-106, 5-7
Output is inverted each time the input of the clock terminal C rises from the "L" level to the "H" level.

The output of the OR gate 8, that is, the second count signal D2 'becomes "L" level during the period two counts before the end of the counting by the second down counter section 1.
In the output POUT2 of the DF-F11, the signal D2 'is "L".
After reaching the level, it becomes "H" level in response to the second rise of the signal Q ', and becomes "L" level in response to the third rise of the signal Q'.

The output of the OR gate 107, that is, the first count signal D'becomes "L" level during the period two counts before the count of the first down counter unit 89 is completed. In the output POUT of the DF-F14, the signal D'is "L".
After reaching the level, it becomes "H" level in response to the second fall of the signal Q ', and becomes "L" level in response to the third fall of the signal Q'.

The output of DF-F16, that is, the output OUT of the variable frequency divider, goes to "L" level in response to the rise of signal POUT2, to "H" level in response to the rise of signal POUT, and to the rise of signal POUT2. Becomes "L" level.

That is, the output OUT has a period in which the first down counter unit 89 counts the preset value (1001) ₂ = 9 set by the setting terminals 55 to 58 as one cycle, and the second down counter unit 1 Are setting terminals 56-58
The "H" level is set during the period of counting the preset value (100) ₂ = 4 set by.

As described above, the first 3 counts of the internal partial frequency signal Q'is the clock signal CLK divided by 5, and the remaining 6 counts of the internal partial frequency signal Q'is 4 times the clock signal CLK. It is a divided one. Therefore, one cycle of the frequency-divided output OUT is 3 × 5 + 4 × 6 = 39 clocks, and 3 × 5 + 4 × 1 = 19 clocks out of 39 clocks are at the “H” level. Therefore, the duty ratio is 100 × 19 / 39≈49%.

Next, as in the conventional example, the set frequency division number K is set to 3
Calculate the change in duty ratio when changing in the range of 2 to 63
Put out. In this embodiment, the DF-
Since F16 is provided, the output after reset is at "H" level.
Or it cannot be specified as "L" level, but it is calculated
For convenience of description, it is set to the “H” level. The frequency division number K is
And the formula K = S1 ′ + 2 × S2 ′ + 2²× P1 + 2³×
P2 + 2^Four× P3 + 2 ^FiveIt is represented by × P4. Also, this
In the above embodiment, the period "H" of the divided output OUT is S1 '+ 2.
× S2 '+ 2²× P2 + 2³× P3 + 2^Four× P4 clock
It becomes ku. Therefore, the duty ratio is 100 × (S
1 '+ 2 x S2' + 2²× P2 + 2³× P3 + 2^Four× P
4) / K (%). Based on this formula, the duty ratio
When the set frequency division number K is in the range of 32 to 63,
The duty ratio changes in the range of 44-54% and 50%
As a reference, it changes in the range of -8 to + 4%.

The duty ratio of the frequency division output OUT is 5
It is the first down counter unit 8 that does not become 0% constant.
When the count value of 9 is an odd number, the second down counter unit 1 has a half of the count value of the first down counter unit 89.
Counting the number after truncating the number after the decimal point,
The cause is that the internal partial frequency signal Q'changes into a frequency-divided by 4 or a frequency-divided by 5.

In this embodiment, the first down counter section 89 for counting the preset value and the second down counter section 1 for counting 1/2 of the preset value are provided, and the second down counter section 1 is provided. The second count signal D which indicates that the counting of the first down counter unit 89 is finished by outputting the "L" level in response to the first count output signal D'which indicates that the counting of
An "H" level is output according to 2 '. Therefore, the frequency division output OUT whose duty ratio is close to 50% can be obtained regardless of the set frequency division number K.

Further, a DF-F16 forming a frequency divider by 2 is provided in front of the frequency division output OUT, and the first and second count output signals D'and D2 'are delayed by two cycles of the signal / Q'. Since the generated signals POUT and POUT2 are used as the clock input of the DF-F16, the frequency division output OUT is generated as in the conventional example.
It does not cause a malfunction such as a communication device due to a spike. Second Embodiment In the first embodiment, the second down counter unit 1
Counts the number of half of the count value of the first down counter unit 89, which is rounded down after the decimal point,
When the count value of the first down counter unit 89 is an odd number, the count value of the second down counter unit 1 becomes smaller than the count value of the first down counter unit 89, and the duty ratio deviates from 50%. there were. The purpose of this embodiment is to solve this problem.

FIG. 3 is a circuit block diagram showing the structure of the main part of a variable frequency divider according to the second embodiment of the present invention.

Referring to FIG. 3, the variable frequency divider includes a pulse counter 41 and a reset / output generation circuit 43. The pulse counter 41 includes an input unit 88, a first down counter unit 89 and a second down counter unit 1,
The reset / output generation circuit 43 includes an inverter 108, a first
Output unit 20 and second output unit 3.

This variable frequency divider is different from the variable frequency divider shown in FIG. 1 in that the first output section 20 has a master type data flip-flop circuit (hereinafter abbreviated as MF-F) 21 and 2:
That is, the selector 22 of No. 1 is newly provided. M
F-F21 outputs data 0.5 clocks after the data is taken in. The selector 22 includes two input terminals A and B, an output terminal O, and a control terminal S.
When the control terminal S is "L" level ("0"), the input terminal A and the output terminal O are conductive, and when the control terminal S is "H" level ("1"), the input terminal B and the output terminal O. Conducts.

The input terminal D of the MF-F21 is DF-F11.
Of the DF-F10,1
Inversion signal of inner partial frequency signal Q '/
Receive Q '. The input terminals A and B of the selector 22 receive the inverted output of the DF-F11 and the inverted output of the MF-F21, respectively. The control terminal S of the selector 22 is connected to the setting terminal 55. The output of the selector 22 becomes the output POUT2 of the first output section 20. The OR gate 15 of the second output unit 3 receives the signals POUT and POUT2.

FIG. 4 is a time chart showing the operation of the variable frequency divider of FIG. The operations of the input unit 88, the first down counter unit 89, and the second down counter unit 1 are the same as those in the first embodiment, and the preset signal R ′, the first counter output signal D ′, and the second counter output signal. The timing of the reset signal SCRST for D2 'and the swallow counter 62 is also the same.

The difference from the first embodiment is that depending on whether the preset value P1 of the setting terminal 55 is "1" or "0", the frequency division output OUT for the falling edge of the second count output signal D2 'is generated. This is the point at which the fall timing changes.

That is, when P1 = 1 as in the above-mentioned example, the input terminal B and the output terminal O of the selector 22 become conductive, so that the signal POUT2 becomes an inverted output of the MF-F21. Therefore, the rising edge of signal POUT2 is delayed from the falling edge of signal D2 'by 2.5 cycles of signal / Q'. As a result, the "H" period of the frequency-divided output OUT is lengthened by 0.5 counts, and the "H" period and the "L" period of the frequency-divided output OUT are both 4.5 counts.

On the other hand, when P1 = 0, for example, the first
The preset value of the down counter unit 89 is (1000)
_{When 2} = 8, the input terminal A and the output terminal O of the selector 22 become conductive, so that the signal POUT2 is DF-F1.
Inverted output of 1. Therefore, the rising edge of the signal POUT2 is delayed from the falling edge of the signal D2 'by 2.0 cycles of the signal / Q', as in the first embodiment. This allows
Both the “H” period and the “L” period of the divided output OUT are 4.0 counts.

Next, as in the first embodiment, the change in duty ratio when the set frequency division number K is changed is calculated. In this embodiment, the "H" period of the divided output OUT is S1 '+ 2 * S2'.
+ 2 × P1 + 2 ² × P2 + 2 ³ × P3 + 2 ⁴ × P4 clocks, so the duty ratio is 100 × (S1 ′ + 2
× S2 ′ + 2 × P1 + 2 ² × P2 + 2 ³ × P3 + 2 ⁴ ×
P4) / K (%). Therefore, when the set frequency division number K is in the range of 32 to 63, the duty ratio changes in the range of 50 to 54%, and when 50% is the reference, it changes in the range of 0 to + 4%.

In this embodiment, when the count value of the first down counter section 89 is an odd number, the second count output signal D2 ', which indicates that the counting of the second down counter section 1 has finished, is started. Since the time until the fall of the frequency-divided output OUT is extended by 0.5 count, the duty ratio of the frequency-divided output OUT can be brought close to 50%. [Third Embodiment] In the first and second embodiments, the inner partial frequency signal Q'is 4
Since the number of pulses of the internal partial frequency signal Q ′ is counted regardless of whether the signal is the frequency-divided signal or the frequency-divided 5 signal, the duty ratio of OUT of the frequency-divided output is increased when the number of pulses of the frequency-divided 5 signal is large. There was a problem that it was out of 50%. The purpose of this embodiment is to solve this problem.

FIG. 5 is a circuit block diagram showing the structure of the main part of the variable frequency divider according to the third embodiment of the present invention.

Referring to FIG. 5, the variable frequency divider includes a pulse counter 41 and a reset / output generation circuit 44. The pulse counter 41 includes an input unit 88, a first down counter unit 89 and a second down counter unit 1,
The reset / output generation circuit 44 includes an inverter 108, a first
Output unit 30 and second output unit 3.

This variable frequency divider differs from the variable frequency divider shown in FIG. 3 in that a 3: 1 selector 31 is provided instead of the 2: 1 selector 22 and the intermediate inverted output of the DF-F11. This is the point used. The selector 31 has three input terminals A, B and C, an output terminal O, and two control terminals S.
1 and S2 are included. As shown in FIG. 6, the control terminals S1,
When both S2 are "L" level ("0"), the input terminal A and the output terminal O are conductive, and the control terminals S1 and S2 are "L" level ("0") and "H" level ("1", respectively). )), The input terminal C and the output terminal O become conductive, and the control terminal S
When the terminals 1 and S2 are at "H" level ("1") and "L" level ("0"), respectively, the input terminal B and the output terminal O are electrically connected, and the control terminals S1 and S2 are both at "H" level ( In the case of "1"), the input terminal A and the output terminal O are electrically connected. In addition, the data taken into DF-F11 is 0.5
Intermediate clock output terminal M and intermediate inverted output terminal /
It is output to M and, after 1.0 clock, is output to the output terminal Q and the inverted output / Q.

The input terminals A, B and C of the selector 31 receive the inverted output of the DF-F11, the inverted output of the MF-F21 and the inverted output of the DF-F11, respectively. The control terminals S1 and S2 of the selector 31 are set terminals 55 and
54 is connected. The output of the selector 31 becomes the output POUT2 of the first output section 30. The OR gate 15 of the second output unit 3 receives the signals POUT and POUT2.

FIG. 7 is a time chart showing the operation of the variable frequency divider of FIG. The operations of the input section 88, the first down counter section 89, and the second down counter section 1 are the same as those in the first and second embodiments, and the preset signal R ', the first counter output signal D', and the second counter output. The same applies to the timing of the signal D2 'and the reset signal SCRST for the swallow counter 62.

The difference from the second embodiment is that depending on whether the set value S2 'of the setting terminal 54 is "1" or "0", the frequency division output OUT for the falling edge of the second count output signal D2' is obtained. This is the point where the timing of the falling edge of changes.

That is, when S2 '= 0 (S2 = 0), the operation is the same as in the first embodiment. This is because when the number of pulses of the divided-by-5 signal is small, it is not necessary to consider the influence of the divided-by-5 signal.

Further, as in the above example, S2 '= 1, P1
= 1 (S1 = S2 = 1), the input terminal A and the output terminal O of the selector 31 become conductive, and therefore the signal POUT2
Is the inverted output of DF-F11. Therefore, the signal P
The trailing edge of OUT2 is delayed from the trailing edge of signal D2 'by two cycles of signal / Q'. As a result, the "H" period of the divided output OUT becomes 4 counts, and the divided output O
The "L" period of the UT is 5 counts. That is, P1
= 1 even if S2 '= 1 and the number of pulses of the frequency-divided 5 signal is large, the timing of the fall of the divided output OUT with respect to the fall of the signal D2' is not delayed. In the above example, the duty ratio of the divided output OUT is 100 × (3 × 5 + 1 × 4) / (3 × 5 + 6 ×
4) = 49%.

Further, S2 '= 1, P1 = 0 (S2 = 1,
When S1 = 0, for example, the frequency division number K is (10001).
1) When ₂ = 35, the input terminal C of the selector 31
And the output terminal O are electrically connected, the signal POUT2 is DF
It becomes the intermediate inverted output of -F11. Therefore, the signal PO
UT2 rises from the falling edge of signal D2 '
It is delayed by 1.5 cycles of Q '. As a result, the “H” period of the divided output OUT is 3.5 counts, and the “L” period of the divided output OUT is 4.5 counts. That is, even if P1 = 0, if S2 ′ = 1 and the number of pulses of the divided-by-5 signal is large, the falling timing of the divided output OUT with respect to the falling of the signal D2 ′ is 0.5 counts. It was designed to be hastened. In the above example, the duty ratio of the frequency division output OUT is 100 × (3 × 5
+ 0.5 × 4) / (3 × 5 + 5 × 4) ≈49%.
Next, as in the first and second embodiments, the change in the duty ratio when the set frequency division number K is changed is calculated. In this embodiment, the "H" period of the divided output OUT is S1 '+ 2 × P1 + 2 ² × P.
2 + 2 ³ × P3 + 2 ⁴ × P4 clocks, so the duty ratio is 100 × (S1 ′ + 2 × P1 + 2 ² × P2 +
2 ³ × P3 + 2 ⁴ × P4) / K (%). Therefore, when the set frequency division number K is in the range of 32 to 63, the duty ratio changes in the range of 47 to 52%, and when 50% is the reference, it changes in the range of -3 to + 2%.

In this embodiment, when the number of pulses of the divided-by-5 signal is large, the second count output signal D indicating that the counting of the second down counter unit 1 has been completed.
Since the time from the fall of 2'to the fall of the divided output OUT has been advanced by 0.5 counts, the divided output OUT
The duty ratio of can be close to 50%.

[0079]

As described above, in the variable frequency divider of the present invention, the first counter for counting the number of pulses of the input signal by 1/2 of the set frequency division number and the set frequency division number A second counter that counts the number of pulses of the input signal is provided, the first level signal is output during the counting period of the first counter, and the second counter of the second counter is output after the counting of the first counter is completed. Second in the period until the count ends
The signal of the level of is output. Therefore, it is possible to obtain a frequency division output whose duty ratio is 50% and whose level is stable regardless of the set frequency division number.

Further, there are provided first to Mth setting terminals for setting the first to Mth digits of the frequency division number, and the first counter is the M-1th digit set by the Mth setting terminal. If the second counter counts only the number of M digits set by the first to Mth setting terminals, an arithmetic unit or the like for halving the set frequency division number is provided. Without doing so, it is possible to easily count 1/2 of the set frequency division number.

Further, if the first digit of the set frequency division number is the first logic, a delay circuit for delaying the first count signal by a half cycle of the input signal is provided, When the set frequency division number is an odd number, the output time of the first level can be extended by the time corresponding to a half cycle of the input signal, and the duty ratio of the frequency division output can be 50%.

Further, the first to Mth setting terminals for setting the first to Mth digits of the frequency division number and the N number of pulses set by the first to Nth setting terminals are input. Signal 2 ^N
And a signal generating means for outputting a second divided signal obtained by dividing the input by 2 ^N times after outputting the first divided signal obtained by dividing by +1 times. The number of pulses of the first and second frequency-divided signals is counted by the number of MN−1 digits set at the Mth setting terminal, and the second counter is set at the N + 1th to Mth setting terminals. If the number of pulses of the first and second frequency-divided signals is counted by the number of MN digits, the input signal can be frequency-divided in two stages, and a large frequency division number can be set. Further, it is possible to easily count 1/2 of the number of pulses of the first and second frequency-divided signals without providing an arithmetic unit or the like for multiplying the number of pulses of the first and second frequency-divided signals by 1/2. You can

Further, according to the fact that the (N + 1) th digit of the set frequency division number is the first logic, the first delay which delays the first count signal by a time corresponding to a half cycle of the second frequency division signal. By providing a circuit, when the number of pulses of the first and second frequency-divided signals is an odd number, the output time of the signal of the first level can be extended by the time corresponding to a half cycle of the second frequency-divided signal. Therefore, the duty ratio of the frequency division output can be brought close to 50%.

Further, a second delay circuit for delaying the second count signal by a half cycle of the input signal is provided in response to the Nth digit of the set frequency division number being the first logic. For example, when the number of pulses of the first frequency-divided signal is large, the output time of the signal of the second level can be extended by the time corresponding to a half cycle of the second frequency-divided signal, and the duty ratio of the frequency-divided output can be reduced. Fifty
It can be close to%.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration of a main part of a variable frequency divider according to a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of the variable frequency divider shown in FIG.

FIG. 3 is a circuit block diagram showing a configuration of a main part of a variable frequency divider according to a second embodiment of the present invention.

FIG. 4 is a time chart showing the operation of the variable frequency divider shown in FIG.

FIG. 5 is a circuit block diagram showing a configuration of a main part of a variable frequency divider according to a third embodiment of the present invention.

6 is a truth table showing the operation of the selector 31 of the variable frequency divider shown in FIG.

FIG. 7 is a time chart showing the operation of the variable frequency divider shown in FIG.

FIG. 8 is a block diagram showing a configuration of a conventional variable frequency divider.

9 is a circuit block diagram showing a configuration of a 2-modulus prescaler of the variable frequency divider shown in FIG.

FIG. 10 is a time chart showing the operation of the 2-modulus prescaler shown in FIG.

11 is a circuit block diagram showing a configuration of a swallow counter of the variable frequency divider shown in FIG.

12 is a time chart showing the operation of the swallow counter shown in FIG.

13 is a circuit block diagram showing configurations of a pulse counter and a reset / output generation circuit of the variable frequency divider shown in FIG.

FIG. 14 is a time chart showing operations of the pulse counter and the reset / output generation circuit shown in FIG.

FIG. 15 is a time chart for explaining problems of the variable frequency divider shown in FIG.

[Description of Reference Signs] 1 second down counter section, 2, 20, 30 first output section, 3 second output section, 41, 63 pulse counter, 42, 43, 44, 64 reset / output generation circuit, 53 to 58 frequency division setting terminal, 61 2 modulus prescaler, 62 swallow counter, 88 input section,
89 First down counter section, 90 Output section.

Claims (6)

[Claims] 1. A variable frequency divider capable of arbitrarily setting a frequency division number, the frequency division number setting means for setting the frequency division number, and the frequency division number set by the frequency division number setting means. According to counting the number of pulses of the input signal by half, the first
A second counter for outputting a count signal of the input signal, a second counter for outputting a second count signal in response to counting the number of pulses of the input signal by the frequency division number set by the frequency division number setting means, And a period of time from the output of the first count signal to the output of the second count signal during the period until the output of the first count signal A variable frequency divider comprising an output circuit for outputting a second level signal. 2. The frequency division number setting means sets the first to Mth frequency division number setting terminals for setting the first to Mth digits of the frequency division number to the first or second logic, respectively. Wherein the first counter counts the number of pulses of the input signal by the number of M-1 digits set at the second to Mth frequency division number setting terminals, and the second counter counts the number of pulses of the input signal. The variable frequency divider according to claim 1, wherein the number of pulses of the input signal is counted by the number of M digits set by the M to Mth frequency division number setting terminals. 3. When the first digit of the frequency division number set at the first frequency division number setting terminal is the first logic, the first count signal is changed to the input signal of the input signal. The variable frequency divider according to claim 2, further comprising a delay circuit that delays by a time corresponding to a half cycle and outputs the delayed signal to the output circuit. 4. The frequency division number setting means sets the first to Mth frequency division number setting terminals for setting the first to Mth digits of the frequency division number to the first or second logic, respectively. 2 ^{N of the} input signal for the number of N-digit pulses set by the first to Nth (where N <M) frequency division number setting terminals.
The first counter is provided with signal generating means for outputting a second ^divided signal obtained by dividing the input signal by 2 ^N times after outputting the first divided signal obtained by dividing by +1. The number of pulses of the first and second frequency-divided signals is counted by the number of M−N−1 digits set from the N + 2 to M-th frequency division number setting terminals, and the second counter is The number of pulses of the first and second frequency division signals is counted by the number of MN digits set at the frequency division number setting terminal of M.
The variable frequency divider according to claim 1. 5. The first count signal is set to the second count in response to the N + 1th digit of the frequency division number set at the N + 1th frequency division number setting terminal being the first logic. A delay circuit for delaying by a time corresponding to a half cycle of the divided signal and outputting the delayed signal to the output circuit.
The variable frequency divider according to claim 4. 6. The second count signal is set to the second value when the Nth digit of the frequency division number set at the Nth frequency division number setting terminal is the first logic. 6. The variable frequency divider according to claim 4, further comprising a second delay circuit that delays by a time corresponding to a half cycle of the divided signal and outputs the delayed signal to the output circuit.