JPS6333737B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency divider circuit that divides the frequency of an input clock to a predetermined frequency division ratio, and more particularly to a frequency divider circuit that can set a non-integer frequency division ratio.

As is well known, multiple flip-flops (hereinafter referred to as
Since the frequency division ratio of a frequency divider circuit consisting of FF (abbreviated as FF) and gates is limited to integers, in order to obtain an output with a non-integer frequency division ratio for the input clock, the frequency of the input clock must be multiplied. The need arose. 1st
The figure shows a frequency divider circuit with a frequency division ratio of 7.5:1 as an example of a conventional non-integer frequency divider circuit. Further, FIG. 2 is a timing diagram of waveforms at each part in FIG. 1.

In Figure 1, f in1 is the input clock, f
out1 is the divided output. f×1 is inverter 1,
This is the output of a frequency multiplier circuit consisting of a resistor Rd, a capacitor Cd, and an ExOR gate 2, and has a frequency twice that of the input clock f in1. This output f×1
, flip-flops 3 to 6 and gates 7 to 11
As a result, the frequency ratio of the input clock f in1 and the frequency divided output f out1 becomes 7.5 to 1 as shown in the following equation.

f out1/f in1=f×1/f in1×f out1/f×
1 = 2 x 1/15 = 1/7.5 However, in the conventional method, an integration circuit consisting of a resistor Rd and a capacitor Cd is required to multiply the frequency, and a large current is consumed to charge and discharge the capacitor Cd. . Furthermore, providing a resistor and a capacitor in an integrated circuit requires a large area, resulting in many problems such as a reduction in the degree of integration.

SUMMARY OF THE INVENTION An object of the present invention is to realize a non-integer frequency dividing circuit that does not require a multiplier circuit in order to eliminate the above-mentioned drawbacks.

The details of the present invention will be explained below with reference to the drawings. The drawings show one embodiment of the present invention, and FIG. 3 is a frequency dividing circuit with a frequency division ratio of 7.5:1, and FIG. 4 is a timing chart of waveforms of various parts in FIG. 3.

In Fig. 3, f in2 is the input clock, f×
2 is the input of the first-stage flip-flop 12, and the respective waveforms are shown as input clock f in2 and input f×2 in FIG. The phase of input clock f in2 and input f×2 is the output of flip-flop 15.
When _Q9 is “H”, the phase is reversed. Further, in flip-flops 12 to 16, T or C is a clock input, R is a reset input, and D is a data input. The outputs are Q ₅ to _{Q 9} , and ₅ to ₉ are outputs obtained by inverting the levels of Q ₅ to _{Q 9} , respectively. The outputs of flip-flops 12-15 are clock input T.
It reverses at the falling edge of . Also, flip-flop 16
outputs the level of data input D at the falling edge of clock input C.

In FIG. 4, when the timing ta is set to the initial state, the output of the NOR gate 18 becomes "H" at the timing tb, and therefore the output ₈ of the flip-flop 16 becomes "L" at the timing tc. At this time, flip-flops 12-14 are reset, and outputs _Q5 - _Q7 become the same as their initial states. At the same time, the output _Q9 of the flip-flop 15 becomes "H", so the input fx2 becomes the inverted version of the input clock f in2, so the timing changes from timing tc to
Output Q ₅ of flip-flops 12-14 up to TD
~Q ₇ is the same as between timing ta and timing tb. That is, this frequency dividing circuit as a whole operates with 15 cycles of the input clock f in2 as one cycle, but by inverting the phase of the input f×2 every 7.5 cycles of the input clock f in2, the input clock f
For the frequency in2, an output f out2 of 7.5 to 1 is obtained.

As detailed above, since the non-integer frequency divider circuit according to the present invention does not require a multiplier circuit consisting of resistors, capacitors, etc., it has great effects such as reducing current consumption and improving the degree of integration when provided in an integrated circuit. It is something that you have.

[Brief explanation of the drawing]

Fig. 1 is a diagram of a conventional 1/7.5 frequency division circuit using a frequency multiplier circuit, Fig. 2 is a timing chart of waveforms of various parts in Fig. 1, and Fig. 3 is an embodiment of the present invention.
1/7.5 frequency division circuit diagram, FIG. 4 is a timing chart of waveforms of each part in FIG. 3. 1, 10, 20, 21... Inverter, 2, 1
7...EXOR gate, 7...AND gate, 8,
9,18...OR gate, 11,19...NAND
Gate, 3-6, 12-16...Flip-flop, Rd...Resistor, Cd...Capacitor.

Claims (1)

[Claims] 1. A frequency division stage in which a plurality of flip-flops are connected in cascade, and an internal state in which the outputs of each flip-flop in the frequency division stage are connected and an output is generated upon detecting that the internal state of the frequency division stage has reached a predetermined state. a detection circuit, a reset circuit that receives the output of the internal state detection circuit and generates a reset signal for setting the frequency dividing stage to an initial state; An inverting flip-flop that inverts the output, and an output of the inverting flip-flop and a clock signal to be divided are input, and when the logic level of the output of the inverting flip-flop is at a predetermined level, the phase of the clock signal to be divided is determined. and an inversion control circuit that inverts and outputs the clock signal and outputs the clock signal to be divided without inverting the phase when the logic level of the output of the inverting flip-flop is opposite to the predetermined level. , wherein the output of the inversion control circuit is connected to the input clock terminal of a predetermined flip-flop in the frequency dividing stage, and a divided output of a predetermined frequency division ratio is output from the output terminal of the predetermined flip-flop. frequency divider circuit.