WO2024016896A1

WO2024016896A1 - Multi-phase clock generation circuit and method

Info

Publication number: WO2024016896A1
Application number: PCT/CN2023/099787
Authority: WO
Inventors: 严波; 许强; 王悦
Original assignee: 普源精电科技股份有限公司
Priority date: 2022-07-19
Filing date: 2023-06-13
Publication date: 2024-01-25
Also published as: CN115296662A

Abstract

Disclosed in the present application are a multi-phase clock generation circuit and method. The circuit comprises: a frequency division module, wherein a signal input end of the frequency division module receives and connects to a clock source signal, and the frequency division module is configured to perform two divided-frequency on the clock source signal, so as to generate a first reference clock signal and a second reference clock signal, which intersect with each other; and a multi-phase clock generation module, which is connected to an output end of the frequency division module, wherein the multi-phase clock generation module is configured to receive the first reference clock signal and the second reference clock signal, and output a four-phase clock signal with a predetermined phase difference relationship.

Description

Multiphase clock generation circuit and method

This application claims priority to the Chinese patent application with application number 202210848272.1, which was submitted to the China Patent Office on July 19, 2022. The entire content of this application is incorporated into this application by reference.

Technical field

The present application belongs to the field of signal processing technology, and for example, relates to a multi-phase clock generation circuit and method.

Background technique

In signal processing systems, such as the design of time-interleaved analog-to-digital converter (TIADC), multi-channel time-to-digital converter (TDC), etc., it is necessary to Using multiple clocks with a fixed clock phase difference relationship, such multiple clocks are called polyphase clocks.

The generation of polyphase clocks in related technologies is mostly implemented using technologies such as Phase Locked Loops (PLL) or Delay Loop Lock (DLL). Both methods require the use of feedback loops and large areas. The loop filter and external reference clock have problems such as complex circuits and high power consumption.

Contents of the invention

Embodiments of the present application provide a multi-phase clock generation circuit and method, which can solve the problems of complex structure and high power consumption of existing multi-phase clock generation circuits.

An embodiment of the present application provides a multi-phase clock generation circuit. The circuit includes: a frequency dividing module. The signal input end of the frequency dividing module receives a connected clock source signal. The frequency dividing module is configured to The signal is frequency-divided by two to generate a first reference clock signal and a second reference clock signal that intersect with each other; a polyphase clock generation module is connected to the output end of the frequency division module, and the polyphase clock generation module is connected to the output end of the frequency division module. The clock generation module is configured to receive the first reference clock signal and the second reference clock signal and output a four-phase clock signal with a predetermined phase difference relationship.

Embodiments of the present application provide a multi-phase clock generation method, which method is applied to the above-mentioned multi-phase clock generation circuit. The method includes: dividing the clock source signal by two through a frequency division module to generate intersecting signals. The first reference clock signal and the second reference clock signal, wherein the signal input end of the frequency dividing module receives the clock source signal; the first reference clock signal and the second reference clock signal are received through the multi-phase clock generation module Referring to the clock signal, a four-phase clock signal with a predetermined phase difference relationship is output, wherein the multi-phase clock generation module is connected to the frequency dividing module.

An embodiment of the present application provides an electronic device. The electronic device includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor. The program or instructions are executed by the processor. When executed, the steps of the polyphase clock generation method are implemented as described.

Embodiments of the present application provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the programs or instructions are executed by a processor, the steps of the polyphase clock generation method as described above are implemented.

An embodiment of the present application provides a chip. The chip includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is configured to run a program or instructions to implement the multi-phase clock as described. Generate the steps of the method.

Description of drawings

Figure 1 is a schematic structural diagram of a multi-phase clock generation circuit provided by an embodiment of the present application;

Figure 2 is a schematic structural diagram of a multi-phase clock generation module of another multi-phase clock generation circuit provided by an embodiment of the present application;

Figure 3 is a schematic structural diagram of a multi-phase clock generation module of another multi-phase clock generation circuit provided by an embodiment of the present application;

Figure 4 is a schematic flow chart of a polyphase clock generation method provided by an embodiment of the present application;

Figure 5 is a schematic structural diagram of a multi-phase clock generation device provided by an embodiment of the present application;

Figure 6 is a schematic structural diagram of an electronic device provided by this application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

The terms "first", "second", etc. in the description and claims of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. It is to be understood that the figures so used are interchangeable under appropriate circumstances so that the embodiments of the present application can be practiced in orders other than those illustrated or described herein, and that "first,""second," etc. are distinguished Objects are usually of one type, and the number of objects is not limited. For example, the first object can be one or multiple. In addition, "and/or" in the description and claims indicates at least one of the connected objects, and the character "/" generally indicates that the related objects are in an "or" relationship.

The following describes a multi-phase clock generation circuit and method provided by embodiments of the present application through embodiments and application scenarios with reference to the accompanying drawings.

Figure 1 is a schematic structural diagram of a multi-phase clock generation circuit provided by an embodiment of the present application. The multi-phase clock generation circuit 100 includes: a frequency dividing module 110. The signal input end of the frequency dividing module 110 receives a clock source signal. The frequency dividing module 110 is configured to divide the clock source signal by two to generate The first reference clock signal and the second reference clock signal that intersect each other; the multi-phase clock generation module 120, the multi-phase clock generation module 120 is connected to the output end of the frequency dividing module 110, the multi-phase clock generation module 120 It is configured to receive the first reference clock signal and the second reference clock signal and output a four-phase clock signal with a predetermined phase difference relationship.

In one implementation, the multi-phase clock generation circuit 100 uses a differential method to transmit signals.

It should be noted that using differential signal transmission can enhance the circuit's ability to resist common mode and interference. To transmit signals in a differential manner, the transmitting end transmits electrical signals with equal amplitude and opposite phases on two signal lines, and the receiving end performs subtraction on the received signals of the two signal lines, thus obtaining a signal with doubled amplitude. The principle of anti-interference is: if two signal lines are subjected to the same (same phase, equal amplitude) interference signal, since the receiving end subtracts the received signals of the two signal lines, the interference signal is basically canceled.

As shown in Figure 1, the input terminal VIP and the input terminal VIN of the frequency dividing module 110 are used as the differential input terminals of the overall circuit, and the clock source signal CLKIN is input. The frequency dividing module 110 is configured to divide the clock source signal by two to generate The first reference clock signal Ref_CLK1 and the second reference clock signal Ref_CLK2 intersect each other, and their phase difference is 90°. The first reference clock signal Ref_CLK1 and the second reference clock signal Ref_CLK2 are respectively connected to two differential inputs of the multi-phase clock generation module 120 Terminals VIP_1/VIN_1 and VIP_2/VIN_2, the four pairs of differential output terminals A_VOP/A_VON, B_VOP/B_VON, C_VOP/C_VON, D_VOP/D_VON of the multi-phase clock generation module are the four-phase clock signal output terminals of the overall circuit, corresponding to the outputs respectively. Four channels of clock signals A_CLK, B_CLK, C_CLK, D_CLK.

The multi-phase clock generation circuit provided by this application can achieve the output of a four-phase clock through the combination of a frequency division module and a multi-phase clock generation module, without the need for feedback loops and circuits similar to those in multi-phase clock generation circuits based on PLL or DLL. The large-area loop filter and external reference clock have a simple structure, are easy to design and produce, and have great advantages in area and power consumption.

An embodiment of the present application provides a multi-phase clock generation circuit. Through a frequency dividing module, the signal input end of the frequency dividing module receives a clock source signal. The frequency dividing module is configured to divide the clock source signal by two. , generating a first reference clock signal and a second reference clock signal that intersect with each other; a multi-phase clock generation module, the multi-phase clock generation module is connected to the output end of the frequency dividing module, and the multi-phase clock generation module is configured as receiving the first reference clock signal and the second reference clock signal, and outputting The four-phase clock signal with a predetermined phase difference relationship can solve the problems of complex structure and high power consumption of multi-phase clock generation circuits in related technologies.

In one implementation, the polyphase clock generation module includes: multiple multiplexing modules, wherein each of the multiplexing modules is configured to directly output or invert the first reference clock signal to obtain The signal of at least one channel in the four-phase clock signal; and/or, each of the multiplexing modules is configured to directly output or invert the second reference clock signal to obtain one of the four-phase clock signals. signal of at least one channel.

In one implementation, each of the multiplexing modules includes a plurality of signal input terminals and a signal selection terminal, wherein each of the signal input terminals receives the first reference clock signal or the second reference clock signal. clock signal, the signals received by the plurality of signal input terminals are not exactly the same, and the signal selection terminal is configured to control the multiplexing module to select from the first reference clock signal and the second reference clock signal. One input obtains the signal of at least one channel of the four-phase clock signal.

The multi-phase clock generation module includes a mode selection terminal. The mode selection terminal receives a mode control signal. The mode control signal is used to control the generation of the four-phase clock signals in different modes, wherein the different modes correspond to different Describe the predetermined phase difference relationship.

In one implementation, the multi-phase clock generation module further includes: a buffer module configured to directly output the first reference clock signal to obtain at least one channel of the four-phase clock signal. Signal.

FIG. 2 is a schematic structural diagram of a multi-phase clock generation module of a multi-phase clock generation circuit provided by an embodiment of the present application. An embodiment of the present application provides a multi-phase clock generation circuit including: a frequency dividing module. The signal input end of the frequency dividing module receives a clock source signal. The frequency dividing module is configured to perform two operations on the clock source signal. Frequency division to generate a first reference clock signal and a second reference clock signal that intersect with each other; a polyphase clock generation module 220, which is connected to the output end of the frequency division module, and the polyphase clock The generation module 220 is configured to receive the first reference clock signal and the second reference clock signal and output a four-phase clock signal with a predetermined phase difference relationship, wherein, as shown in FIG. 2 , the multi-phase clock generation module 220 Includes: buffer module 221 and three multiplexing modules 222, 223 and 224. The differential input terminal VIP/VIN of the buffer module 221 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN. The differential output terminal VOP/VON of the buffer module 221 serves as the A-channel differential output terminal of the circuit, and the output signal A_CLK is shown in Figure 1 It can be seen that the output phase of the buffer module 221 is 0°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the multiplexing module 222 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; S<0>Terminal strobe signal MODE_SELECT<0>, you can select the phase of differential input channel 1 or differential input channel 2 for output; The differential output terminal VOP/VON of the multiplexing module 222 serves as the B-channel differential output terminal of the overall circuit and outputs the signal B_CLK. It can be seen from Figure 1 that the output phase of the multiplexing module 222 is 0° or 180°. .

The VIP_1/VIN_1 terminal of the differential input channel 1 of the multiplexing module 223 is connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; S<0 >Connect the strobe signal MODE_SELECT<1> to select the phase of differential input channel 1 or differential input channel 2 for output; the differential output terminal VOP/VON of the multiplexing module 223 serves as the C-channel differential output terminal of the overall circuit , the output signal C_CLK. It can be seen from Figure 1 that the output phase of the multiplexing module 223 is 90° or 0°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the multiplexing module 224 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the differential input The VIP_3/VIN_3 terminal of channel 3 is reversely connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; S<0> is connected to the strobe signal MODE_SELECT<2>, and the phase of differential input channel 1, differential input channel 2 or differential input channel 3 can be selected. Output, the differential output terminal VOP/VON of the multiplexing module 224 serves as the D-channel differential output terminal of the overall circuit, and outputs the signal D_CLK. It can be seen from Figure 1 that the output phase of the multiplexing module 224 is 0°, 180° or 270°.

In summary, through the selection of the control signal MODE_SELECT<2:0>, the main available outputs of this circuit are: 0°, 90°, 180°, 270°; 0°, 0°, 0°, 0°; 0°, Three output modes: 180°, 0°, and 180°.

In one implementation, the frequency division module includes a synchronization signal terminal, the synchronization signal terminal receives a synchronization control signal, and the synchronization control signal is used to compare the first reference clock signal and the second reference clock signal. The generation is controlled synchronously.

In the embodiment of the present application, the frequency division module with synchronization function can synchronize the four-phase clock, so that the timing relationship can be determined. At the same time, by connecting multiple multiplexing modules in parallel, the clock source signal can be converted and output to obtain a four-phase clock signal with a predetermined phase difference relationship while passing through fewer circuits. This circuit has a simple structure and low power consumption. Its design also has certain advantages in delay, temperature drift and phase noise.

An embodiment of the present application provides a multi-phase clock generation circuit. Through a frequency dividing module, the signal input end of the frequency dividing module receives a clock source signal. The frequency dividing module is configured to divide the clock source signal by two. , generating a first reference clock signal and a second reference clock signal that intersect with each other; a multi-phase clock generation module, the multi-phase clock generation module is connected to the output end of the frequency dividing module, and the multi-phase clock generation module is configured as Receive the first reference clock signal and the second reference clock signal and output a four-phase clock signal with a predetermined phase difference relationship, which can solve the problem of multi-phase clock generation circuits in related technologies. Problems of complex structure and high power consumption.

In the multi-phase clock generation circuit provided by the embodiment of the present application, the multi-phase clock generation module includes: a plurality of multiplexing modules, wherein each of the multiplexing modules is configured to generate the first reference clock signal Directly output or flip the output to obtain the signal of at least one channel of the four-phase clock signal; and/or, each of the multiplexing modules is configured to directly output or flip the second reference clock signal to obtain the signal. The signal of at least one channel in the four-phase clock signal, each of the multiplexing modules includes a plurality of signal input terminals and a signal selection terminal, wherein each signal input terminal receives the first reference clock signal or the The second reference clock signal, the signals received by the plurality of signal input terminals are not exactly the same, and the signal selection terminal is configured to control the multiplexing module to obtain the signal from the first reference clock signal and the second reference clock signal. Select one of the clock signals to be input to obtain the signal of at least one channel of the four-phase clock signals, which can solve the problems of complex structure and high power consumption of multi-phase clock generation circuits in related technologies.

In one implementation, the circuit further includes: a plurality of registers, wherein each register is connected to a signal selection end of a multiplexing module, and the number stored in each register is used to control the corresponding multiplexing module. The channel multiplexing module selects one input from the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signal; or a decoder, the decoder respectively Connected to a plurality of multiplexing modules, the decoder is configured to encode the mode control signal to obtain different numbers, wherein the different numbers are used to control the corresponding multiplexing module from the Select one of the first reference clock signal and the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.

In an implementation manner, the plurality of multiplexing modules include: a plurality of primary multiplexing modules and a plurality of secondary multiplexing modules, wherein each of the primary multiplexing modules The module is configured to select one of the first reference clock signal and the second reference clock signal to output a third reference clock signal or a fourth reference clock signal, and each of the two-level multiplexing modules is configured to output The third reference clock signal or the fourth reference clock signal is directly output or inverted to obtain a signal of at least one channel of the four-phase clock signal.

Figure 3 is a schematic structural diagram of a multi-phase clock generation module of another multi-phase clock generation circuit provided by an embodiment of the present application. Another embodiment of the present application provides a multi-phase clock generation circuit including: a frequency dividing module, the signal input end of the frequency dividing module receives a clock source signal, and the frequency dividing module is configured to perform a clock source signal on the clock source signal. Divide frequency by two to generate a first reference clock signal and a second reference clock signal that intersect with each other; a polyphase clock generation module 320, which is connected to the output end of the frequency division module, and the polyphase clock generation module 320 is connected to the output end of the frequency division module. The clock generation module 320 is configured to receive the first reference clock signal and the second reference clock signal and output a four-phase clock signal with a predetermined phase difference relationship. As shown in Figure 3, the polyphase clock generation module 320 includes: 6 multiplexing modules and a decoder 327, wherein the 6 multiplexing modules include 2 first-level multiplexing modules 321, 322 and 4 secondary multiplexing modules 323, 324, 325 and 326, the input terminal of the decoder 327 is connected to the control signal MODE_SELECT<2:0>, and the 6-bit control signal S<5:0> is output, and the 6-bit control signal S<5:0> is used to control each The multiplexing module selects one of the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signal.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the first-level multiplexing module 321 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; S<0 >The output signal S<0> of the terminal decoder 327 can be selected to output the phase of differential input channel 1 or differential input channel 2; the differential output terminal VOP/VON of the first-level multiplexing module 321 outputs the third reference The clock signal Ref_CLK3 is connected in parallel to the subsequent circuit, and the output phase of the first-level multiplexing module 321 is 0° or 90°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the first-level multiplexing module 322 is connected to the second reference clock signal Ref_CLK2_VIP/Ref_CLK2_VIN; the VIP_2/VIN_2 terminal of the differential input channel 2 is connected to the first reference clock signal Ref_CLK1_VIP/Ref_CLK1_VIN; S<0 >The output signal S<1> of the terminal is connected to the decoder, and the phase of differential input channel 1 or differential input channel 2 can be selected for output; the differential output terminal VOP/VON of the first-level multiplexing module 322 outputs differential signals and is connected in parallel The output phase of the downstream circuit and the first-level multiplexing module 322 is also 90° or 0°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 323 is directly connected to the output terminal VOP/VON of the primary multiplexing module 321; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexer Use the output terminal VOP/VON of module 321; S<0> to terminate the output signal S<2> of the decoder, and you can select the phase of differential input channel 1 or differential input channel 2 for output; two-level multiplexing module The differential output terminal VOP/VON of 323 serves as the A-channel differential output terminal of the circuit. The output phase of the secondary multiplexing module 323 can be any phase of 0°, 90°, 180° or 270°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 324 is connected to the output terminal VOP/VON of the primary multiplexing module 322; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexer The output terminal VOP/VON of the multiplexing module 322; S<0> is connected to the output signal S<3> of the decoder, and the phase of the differential input channel 1 or the differential input channel 2 can be selected for output; two-level multiplexing The differential output terminal VOP/VON of the module 324 serves as the B-channel differential output terminal of the circuit. The output phase of the secondary multiplexing module 324 can be any phase of 0°, 90°, 180° or 270°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 325 is directly connected to the output terminal VOP/VON of the primary multiplexing module 321; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexer Use the output terminal VOP/VON of module 321; S<0> to terminate the output signal S<4> of the decoder, and you can select the phase of differential input channel 1 or differential input channel 2 for output; two-level multiplexing module The differential output terminal VOP/VON of 325 serves as the C-channel differential output terminal of the circuit. The output phase of the secondary multiplexing module 325 can be any phase of 0°, 90°, 180° or 270°.

The VIP_1/VIN_1 terminal of the differential input channel 1 of the secondary multiplexing module 326 is directly connected to the output terminal VOP/VON of the primary multiplexing module 322; the VIP_2/VIN_2 terminal of the differential input channel 2 is reversely connected to the primary multiplexer Use the output terminal VOP/VON of module 322; S<0> to terminate the output signal S<5> of the decoder, and you can select the phase of differential input channel 1 or differential input channel 2 for output; two-level multiplexing module The differential output terminal VOP/VON of 326 serves as the D-channel differential output terminal of the circuit. The output phase of the secondary multiplexing module 326 can be any phase of 0°, 90°, 180° or 270°.

In summary, through reasonable control of the decoder 327, this circuit can generate a four-phase output clock with any phase combination of 0°, 90°, 180°, and 270°.

In this embodiment, multiple multiplexing modules are used in two-level cascade. The first-level multiplexing module realizes the output of one of the first reference clock signal and the second reference clock signal. The second-level multiplexing module realizes the output of one of the first reference clock signal and the second reference clock signal. The channel multiplexing module realizes the direct output or flipped output of the signal based on the first-level multiplexing module, so that it can output a four-phase output clock with any phase combination, thus achieving good circuit matching and inter-channel matching. good.

This application also provides a multi-phase clock generation method, which method is applied to the multi-phase clock generation circuit as shown in Figures 1 to 3, including: dividing the clock source signal by two through a frequency division module to generate intersecting The first reference clock signal and the second reference clock signal, wherein the signal input end of the frequency dividing module receives the clock source signal; the first reference clock signal and the second reference signal are received through the multi-phase clock generation module The clock signal outputs a four-phase clock signal with a predetermined phase difference relationship, wherein the multi-phase clock generation module is connected to the frequency dividing module, which can solve the problems of complex multi-phase clock generation circuit structure and high power consumption in related technologies. question.

The following describes a polyphase clock generation method provided by embodiments of the present application through embodiments and application scenarios with reference to the accompanying drawings.

Figure 4 shows a polyphase clock generation method provided by an embodiment of the present application. This method can be applied to the multi-phase clock generation circuit described above in FIGS. 1 to 3 , or the method can be performed by multiple functional modules in the above-mentioned multi-phase clock generation circuit. In other words, the method can be executed by software or hardware of a plurality of functional modules installed in the multi-phase clock generation circuit, and the method includes the following steps.

S401: Use the frequency division module to divide the clock source signal by two to generate a first reference clock signal and a second reference clock signal that intersect with each other.

The signal input end of the frequency dividing module receives the clock source signal.

S402: Receive the first reference clock signal and the second reference clock signal through a multi-phase clock generation module, and output a four-phase clock signal with a predetermined phase difference relationship.

The multi-phase clock generation module is connected with the frequency dividing module.

In one implementation, the above step S402 includes: passing each of the multiplexing modules The multiplexing module directly outputs or inverts the first reference clock signal to obtain at least one channel of the four-phase clock signal; and/or, through each of the multiple multiplexing modules Each of the multiplexing modules directly outputs or inverts the second reference clock signal to obtain at least one channel of the four-phase clock signal.

In one implementation, the above step S402 includes: receiving the first reference clock signal or the second reference clock signal through each signal input terminal, and controlling the multiplexing module from the Select one of the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signal, wherein each of the multiplexing modules includes a plurality of signal input terminals and A signal selection terminal, the signals received by the multiple signal input terminals are not exactly the same.

In one implementation, the above step S401 includes: using the frequency dividing module to include a synchronization signal terminal, the synchronization signal terminal receives a synchronization control signal, wherein the synchronization control signal is used to modify the first reference clock signal and perform synchronous control with the generation of the second reference clock signal.

In one implementation, the above-mentioned step S402 includes: the multi-phase clock generation module includes a mode selection terminal, and the mode selection terminal receives a mode control signal, wherein the mode control signal is used to control the generation of different modes. For the four-phase clock signal, the different modes correspond to different predetermined phase difference relationships.

In one implementation, the above-mentioned step S402 includes: connecting multiple registers to the signal selection terminals of multiple multiplexing modules, controlling the corresponding multiplexing module to obtain the signal from the first reference clock signal and the third Select one of the two reference clock signals to be input to obtain the signal of at least one channel of the four-phase clock signal, wherein each of the registers stores different numbers that control the corresponding multiplexing module.

In one implementation, the above-mentioned step S402 includes: connecting the decoder to multiple multiplexers respectively, and encoding the mode control signal to obtain different numbers, wherein the different numbers are used for The corresponding multiplexing module is controlled to select and input one of the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signal.

In one implementation, the polyphase clock generation method uses a differential method to transmit signals.

For the implementation of the above steps, please refer to the description of the relevant functional modules of the multi-phase clock generation circuit in Figures 1 to 3. To avoid repetition, they will not be described again here.

A polyphase clock generation method provided by an embodiment of the present application divides a clock source signal by two through a frequency division module to generate a first reference clock signal and a second reference clock signal that intersect with each other, wherein the frequency division module The signal input terminal receives the clock source signal; the multi-phase clock generation module receives the first reference clock signal and the second reference clock signal, and outputs a four-phase clock signal with a predetermined phase difference relationship, wherein, the The multi-phase clock generation module is connected to the frequency dividing module, which can solve the problems of complex structure and high power consumption of multi-phase clock generation circuits in related technologies.

It should be noted that, for the multi-phase clock generation method provided by the embodiments of the present application, the execution subject may be a multi-phase clock generation device, or a control module in the multi-phase clock generation device configured to execute the multi-phase clock generation method. In the embodiment of the present application, a multi-phase clock generation device performing a multi-phase clock generation method is used as an example to illustrate the multi-phase clock generation device provided by the embodiment of the present application.

FIG. 5 shows a schematic structural diagram of a multi-phase clock generation device provided by an embodiment of the present application. As shown in Figure 5, the polyphase clock generation device 500 includes: a frequency dividing module 510. The signal input end of the frequency dividing module 510 receives a clock source signal. The frequency dividing module is configured to divide the clock source signal into two. frequency to generate a first reference clock signal and a second reference clock signal that intersect with each other; a polyphase clock generation module 520, which is connected to the frequency division module, and is configured to receive The first reference clock signal and the second reference clock signal output a four-phase clock signal with a predetermined phase difference relationship.

In one implementation, the multi-phase clock generation device 500 uses a differential method to transmit signals.

In one implementation, the multi-phase clock generation module 520 includes: a plurality of multiplexing modules, wherein each of the multiplexing modules is configured to directly output or invert the first reference clock signal. Obtain the signal of at least one channel in the four-phase clock signal; and/or, each of the multiplexing modules is configured to directly output or invert the second reference clock signal to obtain the four-phase clock signal. signal from at least one channel.

In one implementation, each of the multiplexing modules includes a plurality of signal input terminals and a signal selection terminal, wherein each signal input terminal receives the first reference clock signal or the second reference clock signal. , the signals received by the multiple signal input terminals are not exactly the same, and the signal selection terminal is configured to control the multiplexing module to select one input from the first reference clock signal and the second reference clock signal. A signal of at least one channel among the four-phase clock signals is obtained.

The multi-phase clock generation module 520 includes a mode selection terminal. The mode selection terminal receives a mode control signal. The mode control signal is used to control the generation of the four-phase clock signals in different modes, wherein the different modes correspond to different the predetermined phase difference relationship.

In one implementation, the multi-phase clock generation module 520 further includes: a buffer module configured to directly output the first reference clock signal to obtain at least one channel of the four-phase clock signal. signal of.

In one implementation, the frequency division module 510 includes a synchronization signal terminal, the synchronization signal terminal receives a synchronization control signal, and the synchronization control signal is used to compare the first reference clock signal and the second reference clock. Signal generation is controlled synchronously.

In one implementation, the multi-phase clock generation device 500 further includes:

a plurality of registers, each of which is connected to a signal selection end of a multiplexing module, The number stored in each register is used to control the corresponding multiplexing module to select one of the first reference clock signal and the second reference clock signal to obtain at least one channel of the four-phase clock signal. signal of;

Or a decoder, the decoder is respectively connected to a plurality of the multiplexing modules, the decoder is configured to encode the mode control signal to obtain different digits, wherein the different digits are The corresponding multiplexing module is controlled to select one input from the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signal.

In one implementation, the plurality of multiplexing modules include: a plurality of primary multiplexing modules and a plurality of secondary multiplexing modules, wherein each of the primary multiplexing modules The module is configured to select one of the first reference clock signal and the second reference clock signal to output a third reference clock signal or a fourth reference clock signal, and each of the two-level multiplexing modules is configured to The third reference clock signal or the fourth reference clock signal is directly output or inverted to obtain a signal of at least one channel of the four-phase clock signal.

The multi-phase clock generating device in the embodiment of the present application may be a device, or may be a component, integrated circuit, or chip in a terminal.

The multi-phase clock generation device in the embodiment of the present application may be a device with an operating system, or may be other possible operating systems.

The multi-phase clock generation device provided by the embodiment of the present application can realize the functions of the corresponding multiple modules in the multi-phase clock generation circuit of Figures 1 to 3, or implement multiple processes implemented in the multi-phase clock generation method embodiment of Figure 4 , to avoid repetition, will not be repeated here.

Optionally, as shown in Figure 6, this embodiment of the present application also provides an electronic device 600, including a processor 601, a memory 602, and programs or instructions stored on the memory 602 and executable on the processor 601. When the program or instruction is executed by the processor 601, the clock source signal is divided by two through the frequency dividing module to generate a first reference clock signal and a second reference clock signal that intersect with each other, wherein the signal of the frequency dividing module The input terminal receives the clock source signal; receives the first reference clock signal and the second reference clock signal through a multi-phase clock generation module, and outputs a four-phase clock signal with a predetermined phase difference relationship, wherein the multi-phase The clock generation module is connected with the frequency dividing module.

It should be noted that the embodiments of the electronic equipment in this specification and the embodiments of the multi-phase clock generation circuit in this specification are based on the same inventive concept. Therefore, the implementation of this embodiment can refer to the implementation of the corresponding multi-phase clock generation circuit mentioned above. , the repetitive parts will not be repeated.

Embodiments of the present application also provide a readable storage medium. Programs or instructions are stored on the readable storage medium. When the program or instructions are executed by a processor, the multiple processes of the above multi-phase clock generation method embodiment are implemented, as To avoid repetition, we will not go into details here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage media includes computer-readable storage media, such as computer read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disks or optical disks, etc.

An embodiment of the present application also provides a chip. The chip includes a processor and a communication interface. The communication interface is coupled to the processor. The processor is configured to run a program or instructions to implement the above polyphase clock generation method. To avoid duplication, the multiple processes of the embodiment, or the functions of multiple modules that implement the above-mentioned multi-phase clock generation circuit or multi-phase clock generation device embodiment, will not be described in detail here.

It should be understood that the chips mentioned in the embodiments of this application may also be called system-on-chip, system-on-a-chip, system-on-a-chip or system-on-chip, etc.

Those skilled in the art should understand that embodiments of the present application may be provided as methods, devices, or computer program products. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment that combines software and hardware aspects. Moreover, this application may use one or more computer-usable storage media (including but not limited to magnetic disk storage, read-only compact disc read-only memory (Compact Disc Read-Only Memory, CD-ROM), optical memory) containing computer-usable program code. etc.) in the form of a computer program product implemented on.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each process and/or block in the flowchart illustrations and/or block diagrams, and combinations of processes and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device produce the settings Means for implementing the functions specified in a process or processes of a flowchart and/or a block or blocks of a block diagram.

These computer program instructions may also be stored in a computer-readable memory that causes a computer or other programmable data processing apparatus to operate in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including the instruction means, the instructions The device implements the functions specified in a process or processes of the flowchart and/or a block or blocks of the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device, causing a series of operating steps to be performed on the computer or other programmable device to produce computer-implemented processing, thereby executing on the computer or other programmable device. Instructions provide steps for implementing the functions specified in a process or processes of a flowchart diagram and/or a block or blocks of a block diagram.

In a typical configuration, the electronic device includes one or more central processing units (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include non-volatile storage in computer-readable media, RAM and/or non-volatile memory storage form, such as ROM or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer-readable media includes both persistent and non-volatile, removable and non-removable media that can be implemented by any method or technology for storage of information. Information may be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, Phase-change Random Access Memory (PRAM), Static Random Access Memory (Static Random Access Memory, SRAM), Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM), other types of RAM, ROM, Electrically-Erasable Programmable Read-Only Memory (EEPROM), flash memory or other memory technology, CD-ROM, digital versatile disc ( Digital Video Disc, DVD) or other optical storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device or any other non-transmission medium may be used to store information that can be accessed by a computing device. As defined in this article, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises,""comprises," or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements not only includes those elements, but also includes Other elements are not expressly listed or are inherent to the process, method, article or equipment. An element defined by the statement "comprises a..." does not exclude the presence of additional identical elements in a process, method, article, or device that includes the stated element.

Claims

A multi-phase clock generation circuit including:

A frequency dividing module. The signal input end of the frequency dividing module receives a clock source signal. The frequency dividing module is configured to divide the clock source signal by two to generate a first reference clock signal and a second reference clock that intersect with each other. Signal;

A multi-phase clock generation module, the multi-phase clock generation module is connected to the frequency division module, the multi-phase clock generation module is configured to receive the first reference clock signal and the second reference clock signal, and output a predetermined Four-phase clock signal with phase difference relationship.
The circuit of claim 1, wherein the polyphase clock generation module includes:

A plurality of multiplexing modules, wherein each multiplexing module is configured to at least one of the following: directly outputting the first reference clock signal or inverting the output to obtain at least one channel of the four-phase clock signal. signal; directly output or invert the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.
The circuit of claim 1, wherein the multi-phase clock generation module further comprises:

A buffer module, the buffer module is configured to directly output the first reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.
The circuit of claim 2, wherein each multiplexing module includes a plurality of signal input terminals and a signal selection terminal, wherein each signal input terminal receives the first reference clock signal or the second reference clock signal. clock signal, the signals received by the plurality of signal input terminals are not exactly the same, and the signal selection terminal is configured to control each of the multiplexing modules to obtain the signal from the first reference clock signal and the second reference clock signal. Select one of the clock signals to be input to obtain a signal of at least one channel of the four-phase clock signals.
The circuit according to claim 1, wherein the frequency division module includes a synchronization signal terminal, the synchronization signal terminal receives a synchronization control signal, the synchronization control signal is used to compare the first reference clock signal and the third The generation of two reference clock signals is controlled synchronously.
The circuit according to claim 1, wherein the multi-phase clock generation module includes a mode selection terminal, the mode selection terminal receives a mode control signal, the mode control signal is used to control the generation of the four-phase clock in different modes. signal, wherein the different modes correspond to different predetermined phase difference relationships.
The circuit of claim 4 or 6, further comprising:

A plurality of registers, wherein each register is connected to the signal selection end of a multiplexing module, and the number stored in each register is used to control the multiplexing module corresponding to each register to obtain the signal from the first reference Select one of the clock signal and the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal; or

Decoder, the decoder is respectively connected to the multiplexing modules, the decoder is configured In order to encode the mode control signal to obtain different numbers, wherein the different numbers are used to control the multiplexing module corresponding to the different numbers to obtain the signal from the first reference clock signal and the second reference clock. Select one of the signals to be input to obtain a signal of at least one channel of the four-phase clock signal.
The circuit of claim 1, wherein the multi-phase clock generation circuit transmits signals in a differential manner.
A multi-phase clock generation method, applied to the multi-phase clock generation circuit according to any one of claims 1-8, including:

The clock source signal is divided by two by a frequency dividing module to generate a first reference clock signal and a second reference clock signal that intersect with each other, wherein the signal input end of the frequency dividing module receives the clock source signal;

The first reference clock signal and the second reference clock signal are received through a multi-phase clock generation module, and a four-phase clock signal with a predetermined phase difference relationship is output, wherein the multi-phase clock generation module and the frequency dividing module connect.
The method according to claim 9, wherein receiving the first reference clock signal and the second reference clock signal through a multi-phase clock generation module and outputting a four-phase clock signal with a predetermined phase difference relationship includes the following: At least one of:

The first reference clock signal is directly output or flipped and output through each multiplexing module in a plurality of multiplexing modules to obtain at least one channel of the four-phase clock signal; through multiple multiplexing modules Each multiplexing module in the multiplexing module directly outputs or inverts the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signal.