CN114301454A - Fractional frequency divider, numerically controlled oscillator and phase-locked loop circuit - Google Patents
Fractional frequency divider, numerically controlled oscillator and phase-locked loop circuit Download PDFInfo
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Abstract
A fractional frequency divider, a digitally controlled oscillator, and a phase locked loop circuit are provided. The fractional frequency divider includes: a multi-modulus divider to generate a first division clock based on an input clock and a sequence of division coefficients; a first flip-flop to generate a second divided clock based on the first divided clock; a second flip-flop to generate a third divided clock based on the first divided clock; a first multiplexer for selecting one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer for selecting one of the second divided clock and the third divided clock as a second output divided clock.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a fractional frequency divider, a digitally controlled oscillator, and a phase-locked loop circuit.
Background
In modern electronic system design, a frequency divider circuit is a very important circuit block. The divider circuit may divide a higher frequency signal to obtain a desired low frequency signal and may be divided into integer dividers or fractional dividers depending on the division factor. The frequency divider circuit has a wide application range, and can be applied to a numerically controlled oscillator circuit, a phase-locked loop circuit and the like.
Disclosure of Invention
According to an aspect of the present disclosure, there is provided a fractional frequency divider, including: a multi-modulus divider to generate a first division clock based on an input clock and a sequence of division coefficients; a first flip-flop to generate a second divided clock based on the first divided clock; a second flip-flop to generate a third divided clock based on the first divided clock; a first multiplexer to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer to select one of the second divided clock and the third divided clock as a second output divided clock.
According to another aspect of the present disclosure, there is provided a digitally controlled oscillator including: a fractional frequency divider, the fractional frequency divider comprising: a multi-modulus divider to generate a first division clock based on an input clock and a sequence of division coefficients; a first flip-flop to generate a second divided clock based on the first divided clock; a second flip-flop to generate a third divided clock based on the first divided clock; a first multiplexer to select one of the first divided clock and the second divided clock as a first output divided clock; and a second multiplexer for selecting one of the second divided-down clock and the third divided-down clock as a second output divided-down clock; a digital-to-time converter to generate an output clock based on the first output divided clock and the second output divided clock and to phase error correct the output clock according to a phase error signal; a modulator for generating the sequence of division coefficients and a frequency error signal; and an accumulator for accumulating the frequency error signal to obtain the phase error signal.
According to still another aspect of the present disclosure, there is provided a phase-locked loop circuit including: a phase comparator for outputting an error signal based on a reference clock and a feedback clock, the error signal indicating a phase difference between the reference clock and the feedback clock; a loop filter for loop filtering the error signal; a voltage controlled oscillator to generate a voltage controlled oscillation signal based on the loop filtered error signal; and a digitally controlled oscillator according to an embodiment of the present disclosure, the digitally controlled oscillator being configured to receive the voltage controlled oscillating signal as the input clock and to generate the output clock as the feedback clock.
These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.
Drawings
Further details, features and advantages of the disclosure are disclosed in the following description of exemplary embodiments, taken in conjunction with the accompanying drawings, in which:
fig. 1A shows a schematic circuit diagram of a numerically controlled oscillator in the related art.
Fig. 1B to 1D show schematic diagrams of a digital-to-time converter in the related art.
Fig. 2A illustrates an example fractional divider in accordance with an embodiment of the present disclosure.
Fig. 2B illustrates an example timing diagram of a divide clock in a fractional divider in accordance with an embodiment of the disclosure.
Fig. 3 illustrates an example digitally controlled oscillator according to an embodiment of the present disclosure.
Fig. 4 illustrates an example phase-locked loop circuit in accordance with an embodiment of the present disclosure.
Detailed Description
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items, and the phrase "at least one of a and B" includes a alone, B alone, and both a and B.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Fig. 1A shows a schematic circuit diagram of a numerically controlled oscillator 100 in the related art. A Digitally Controlled Oscillator (DCO) may also be referred to as a numerically controlled oscillator (DCO) and may be capable of generating a controlled oscillating waveform, such as a sine wave or a cosine wave. As shown in fig. 1A, the digitally controlled oscillator 100 may include a fractional divider 101, a digital-to-time converter 102, a modulator 103, and an accumulator 104. A digitally controlled oscillator may be used to generate an output clock 106 based on the input clock 105. Modulator 103 may be a Sigma-Delta modulator. The inputs to the digitally controlled oscillator 100 may include an input clock (ckin)105 and a division factor (Div _ ratio) 107. In the case where the numerically controlled oscillator is a fractional divider, the division coefficient Div _ ratio may be an integer plus a fractional number, e.g., 1.3, 4.4, 5.7, etc., and the disclosure is not limited thereto. The modulator 103 may convert the division coefficient 107 into a sequence of integer division coefficients 107' whose average sum is equal to the division coefficient 107. For example, in an example where the division factor is 4.25, the sequence of integer division factors may be [4,4,4,5,4 … ], or the like, such that the sequence of integer division factors is equal to or approximately equal to 4.25 during a predetermined period or desired time. In such an example, the output of the fractional divider 101, alternatively referred to as the average frequency of the divided down clock (ckdiv)110, may be Fckin/Div _ ratio, where Fckin is the frequency of the input clock ckin 105, and Div _ ratio is the desired division coefficient that may contain a fractional number. The accumulator 104 may accumulate the frequency error 108 in the fractional divider 101 into a phase error 108' to be input to the digital-to-time converter 102. In this way, the digital-to-time converter 102 may correct phase errors in the cycle based on the phase errors 108' such that jitter of the final output clock 106 is reduced.
Fig. 1B to 1D show some examples of digital-to-time converters or digital-to- time dividers 112, 122 and 132 in the related art, wherein the digital-to- time converters 112, 122 and 132 can be used as the digital-to-time converter 102 in the digitally controlled oscillator 100 of fig. 1A.
As shown in fig. 1B, the digital-to-time converter 112 includes a capacitor array 113 and Schmitt triggers 114 to convert an input divided clock ckdiv to an output clock ckout. It will be appreciated that the input divided clock ckdiv here may correspond to the divided clock 110 when applied to the digitally controlled oscillator shown in fig. 1A. In other cases, the input clock may correspond to the input clock 105, etc. The RC constant can be adjusted by adjusting the capacitor array 113, and the phase can be adjusted by adjusting the rise time of the inverter by the RC constant. The digital-to-time converter 112 may include a schmitt trigger 114 to ensure that no meta-stability occurs during the flip-flop. The schmitt trigger may compare the input voltage Vs to the threshold voltage Vt and toggle each time the input voltage reaches the threshold voltage. Since the phase adjustment is caused by the delay of the RC constant, this structure naturally brings about an undesirable Integral nonlinearity ((INL).
As shown in fig. 1C, digital-to-time converter 122 may include a capacitive array 123, a digital-to-analog converter (DAC)125, and a schmitt trigger 124. The digital-to-analog converter 125 may be used to obtain the voltage V by deriving the voltage before the input clock ckdiv of the digital-to-time converter 122 arrivesDAC. The capacitor is then charged through the current mirror to a threshold voltage so that the schmitt trigger 124 can toggle.
In such a case, the time delay td may be expressed as the following formula
Where C is the capacitance and I is the current value. The time delay td thus obtained has a relatively good linearity, but in this case the resolution of the digital-to-time converter 122 needs to be guaranteed by a numerical-to-analog converter (DAC)125, and is therefore more difficult to achieve for a larger dynamic range.
Referring to fig. 1D, the digital-to-time converter 132 may include a capacitor array 133 and a schmitt trigger 134, among others. The digital-to-time converter 132 may have as inputs two clocks, clock a (ckdiv _ a) and clock B (ckdiv _ B). The rising edges of clock a and clock B dictate the full amplitude of the digital-to-time converter. In general, clock A and clock B may be separated by one period of the input clock (T)ckin) I.e. clock A and clock B may be separated by 1 x Tckin。
Returning to the digitally controlled oscillator 100 of FIG. 1A, in the related art, the number isThe full amplitude of the time converter 102 is the period 1 x T of one input clockckinThe jitter of the output clock of the dco 100 is determined by the minimum resolution (LSB) of the dac 102. I.e. Jitter can be expressed as
Where N is the number of bits of the digital-to-time converter 102. Therefore, a larger number of bits N is required to obtain a smaller jitter. However, increasing the number of bits N of the digital-to-time converter 102 by one bit often means doubling the area of the capacitor array or current mirror array and doubling the wiring complexity, thereby greatly increasing the design complexity. In addition, if 1 × T can be combinedckinReduced to 1/2 × TckinJitter will be reduced more effectively.
Exemplary embodiments of the present disclosure will be described in detail below, which may be used to advantage for a number of reasons, such as to mitigate or alleviate these undesirable side effects.
A fractional divider 201 according to an embodiment of the present disclosure is described with reference to fig. 2A. The fractional divider 201 includes a multi-modulus divider 211, a first flip-flop 212, a second flip-flop 213, a first multiplexer 214, and a second multiplexer 215.
The multi-modulus divider 211 is operable to generate a first division clock ckdiv1 based on the input clock ckin and the division coefficient sequence 207'. The division coefficient sequence 207 'may be similar to the aforementioned integer division coefficient sequence 107', for example, an integer signal sequence for characterizing a desired fractional division coefficient by an average value. The multi-modulus divider 211 may be implemented using a counter chip, a programmable logic device design, and the like, including but not limited to implementations that will occur to those of skill in the art, and the disclosure is not limited thereto.
The first flip-flop 212 is used to generate a second divided clock ckdiv2 based on the first divided clock ckdiv 1. The flip-flop receives an input signal and a clock pulse, is sensitive to the pulse edge, and changes its state only at the instant of the rising or falling edge of the clock pulse. The flip-flops may be D flip-flops, where the clock is active later than the data, meaning that the data signal is asserted first and the clock signal is asserted later, striking the corresponding flip-flop at the active edge of the CP pulse.
The second flip-flop 213 is configured to generate a third divided clock ckdiv3 based on the first divided clock ckdiv 1. Similarly, the second flip-flop 213 may also be a D flip-flop, or other types of flip-flops that can be selected by one skilled in the art, and the disclosure is not limited thereto.
The first multiplexer 214 is used to select one of the first divided clock ckdiv1 and the second divided clock ckdiv2 as the first output divided clock ckdiv-a. A multiplexer (multiplexer or mux), which may also be referred to as a data selector, may select and forward a signal from a plurality of analog or digital input signals, thereby outputting different selected signals into the same output line. The first multiplexer 214 may be a double multiplexer, i.e., one of two clock signals, a first divided clock ckdiv1 and a second divided clock ckdiv2, is selected as an output ckdiv-a. The second multiplexer 215 is used to select one of the second divided clock ckdiv2 and the third divided clock ckdiv3 as the second output divided clock ckdiv-B. Similarly, the second multiplexer 215 may be a dual multiplexer. For example, 1/2 × T is generated by the three frequency-divided clocksckinThe digital-to-time converter shown in fig. 1D can be effectively assisted in reducing the full scale, thereby improving accuracy.
According to some alternative embodiments, the first multiplexer 214 and the second multiplexer 215 may be used for clock selection based on the same clock selection signal 209. For example, as shown in FIG. 2A, the clock select signal may come from a modulator 203, such as a modulator similar to the Sigma-Delta modulator 103 described above, or may be another type of modulator as will occur to those of skill in the art. Alternatively, the clock select signal may come from another unit for generating the clock select signal.
According to some alternative embodiments, the first flip-flop 212 and the second flip-flop 213 may be triggered by a pair of clocks of opposite phase.Fig. 2B illustrates an example timing diagram of the first, second, and third divided clocks ckdiv1, ckdiv2, ckdiv3 in such an embodiment. As can be seen in FIG. 2B, the rising edges of the two clock pairs (ckdiv1 and ckdiv2, ckdiv2 and ckdiv3) differ by 0.5T, respectivelyckinWherein T isckinIs the period of the input clock signal ckin. By controlling the multiplexer to trigger the clock signals ckdiv1 and ckdiv2, or the clock signals ckdiv2 and ckdiv3, respectively, 0.5T can be achievedckinFiner resolution.
According to some alternative embodiments, the first flip-flop 212 may be configured to receive an inverted signal of the input clock ckin
As a clock control signal, the second flip-flop 213 may be configured to receive the input clock ckin as a clock control signal.
It is to be appreciated that the fractional divider 201 according to one or more embodiments of the present disclosure may be used with the digital-to-time converter 132 of fig. 1D, and the present disclosure is not limited thereto.
A digitally controlled oscillator 300 according to some embodiments of the present disclosure is described below with reference to fig. 3. As shown in fig. 3, the digitally controlled oscillator 300 may include a fractional divider 301, a digital-to-time converter 302, a modulator 303, and an accumulator 304. Digitally controlled oscillator 300 may generate an output clock (ckout)306 based on an input clock (ckin)305 and a division factor (Div _ ratio) 307. The division factor Div _ ratio may be a non-integer value, for example, a sum of an integer and a fractional.
The fractional divider 301 may be the fractional divider described with reference to embodiments of the present disclosure. For example, the fractional divider 301 may be similar to the fractional divider 201 described with reference to fig. 2B or a variation thereof. The fractional divider 301 may include a multi-modulus divider 311, a first flip-flop 312, a second flip-flop 313, a first multiplexer 314, and a second multiplexer 315. The multi-modulus divider 311 may be configured to generate a first divided clock based on the input clock 305(ckin) and the division coefficient sequence 307'. The first flip-flop 312 may be used to generate a second divided-frequency clock ckdiv2 based on the first divided-frequency clock ckdiv 1. The second flip-flop 313 may be used to generate a third divided clock ckdiv3 based on the first divided clock ckdiv 1. The first multiplexer 314 may be used to select one of the first divided clock ckdiv1 and the second divided clock ckdiv2 as the first output divided clock ckdiv-a. The second multiplexer 315 may be used to select one of the second divided clock ckdiv2 and the third divided clock ckdiv3 as the second output divided clock ckdiv-B. As shown in FIG. 3, the first output divided clock ckdiv-A and the second output divided clock ckdiv-B are then output to the digital-to-time converter 302.
The digital-to-time converter 302 may be used to generate an output clock 306(ckout) based on the first output divided clock ckdiv-A and the second output divided clock ckdiv-B. The digital-to-time converter 302 may also be used to perform phase error correction on the output clock 306 based on the phase error signal 308' from the accumulator 304.
The modulator 303 may be used to generate a division coefficient sequence 307' and a frequency error signal. Specifically, the modulator 303 may convert the division coefficient 307 into a sequence 307' of integer division coefficients, each division value in the sequence being an integer to control the division operation of the multi-modulus divider, and an average value of the integers is equal to the division coefficient 307 over a period of time. The modulator 303 may be a first order Sigma Delta modulator or may be or include any other modulator or modulation circuit as will occur to those of skill in the art.
According to some alternative embodiments, the modulator 303 is further configured to generate a clock select signal 309. In such embodiments, the first multiplexer 314 and the second multiplexer 315 may be configured to perform clock selection based on the clock selection signal 309. For example, the first multiplexer 314 and the second multiplexer 315 may be selected based on the same or identical clock signal such that the outputs of the two multiplexers are coordinated, e.g., the second multiplexer 315 may select to output the second divided clock ckdiv2 as the second output divided clock ckdiv-B when the first multiplexer 314 selects to output the first divided clock ckdiv1 as the first output divided clock ckdiv-a, and the second multiplexer 315 may select to output the third divided clock ckdiv3 as the second output divided clock ckdiv-B when the first multiplexer 314 selects to output the second divided clock ckdiv2 as the first output divided clock ckdiv-a. It will be appreciated that the above are merely examples, and that the disclosure is not limited thereto.
According to some alternative embodiments, the digital-to-time converter 302 may be a phase interpolator based digital-to-time converter as shown in fig. 1D.
According to some embodiments, the first flip-flop 312 is configured to receive an inverted signal of the input clock as a clock control signal, and the second flip-flop 313 is configured to receive the input clock as a clock control signal.
According to one or more embodiments of the present disclosure, the digitally controlled oscillator 300 is capable of achieving a full amplitude of 0.5TckinWherein T isckinIs the period of the input clock ckin. In other words, the output clock may have a resolution of 0.5 times the input clock period. Thus, less jitter can be achieved without increasing circuit complexity.
Additional aspects in accordance with the present disclosure are described below with reference to fig. 4.
The fractional divider may be calibrated using a phase locked loop circuit. A Phase Locked Loop (PLL) may also be called a Phase Locked Loop or a Phase Locked Loop, and is a feedback control circuit capable of controlling the frequency and Phase of an oscillation signal inside a Loop by using an externally input reference signal. Fig. 4 illustrates a phase-locked loop circuit 400 according to an embodiment of the disclosure. As shown in fig. 4, the phase-locked loop circuit 400 may include: a phase comparator 401, a loop filter 402, a voltage controlled oscillator 403 and a digital controlled oscillator 404.
The digitally controlled oscillator 404 may be an oscillator according to embodiments of the present disclosure, and in particular may be similar to the digitally controlled oscillator 300 described with reference to fig. 3, the composition of which is not repeated here. The digitally controlled oscillator 404 may include a fractional divider, a digital-to-time converter, a modulator, and an accumulator.
The phase comparator 401, which may also be referred to as a phase detector or phase discriminator, etc., may be used to output an error signal 413 based on the reference clock 411 and the feedback clock 412. The error signal 413 may be in the form of a charge, a voltage, a digital signal, etc., and the present disclosure is not limited thereto. The error signal 413 is used to indicate the phase difference between the reference clock 411 and the feedback clock 412. The error signal 413 may then be output to the loop filter 402 and used to loop filter the error signal 413 by the loop filter 402 to generate a loop filtered error signal 414. The voltage controlled oscillator 403 may be used to generate a voltage controlled oscillation signal 415 based on the loop filtered error signal 414. The digitally controlled oscillator 404 may be configured to receive a voltage controlled oscillation signal 415 as an input clock, such as the input clock ckin according to embodiments of the present disclosure, and to generate an output clock as the feedback clock 412, such as ckout as described above with reference to the preceding. It will be appreciated that according to such a phase locked loop circuit 400, the fractional divider in the digitally controlled oscillator 404 can be calibrated to achieve an accurate 0.5TckinAnd (6) outputting.
According to some optional embodiments, the phase-locked loop circuit 400 may further include a calibration circuit 410. The calibration circuit 410 may include a first error estimation circuit 405, a first multiplier 406, a second error estimation circuit 407, a first adder 408, and a second multiplier 409. Calibration circuit 410 may be used to calibrate the instrument for errors due to transistor errors, line asymmetries, etc. to achieve more accurate circuit resolution (e.g., 0.5T)ckinThe resolution of (d). In such embodiments, the phase comparator 401 may also be used to output a late signal 416 based on the reference clock 411 and the feedback clock 412. The late signal 416 indicates the temporal order of the reference clock 411 and the feedback clock 412 relative to each other. In such an embodiment, the modulator of the digitally controlled oscillator 404 may also be used to generate a clock select signal 417, which may be, for example, a clock select signal used to select the output of a multiplexer in the digitally controlled oscillator, as already described above.
The first error estimation circuit 405 may be used to determine a clock phase error 418 based on the late signal 416 and a clock select signal 417. The first multiplier 406 may be used to multiply the clock phase error 418 with the clock select signal 417 to obtain a clock error signal 419. The second error estimation circuit 407 may be used to determine the gain error 421 based on the late signal 416 and the phase error signal 420. As previously described, the phase error signal 420 may be derived from the digitally controlled oscillator 404, for example, may be obtained by an accumulator of the digitally controlled oscillator 404 accumulating frequency error signals, etc., and may be similar to the phase error signal 308' described in connection with fig. 3. The first adder 408 may be used to add the clock error signal 419 and the phase error signal 420 to obtain an added error signal 422. For example, clock phase errors may be added to phase errors when used in open loop. The second multiplier 409 may be used to multiply the gain error 421 with the added error signal 422 to obtain a full-amplitude error correction signal 423, and the full-amplitude error correction signal 423 may be output to the digitally controlled oscillator 404 (specifically, to a digital-to-time converter (not shown) in the digitally controlled oscillator 404) for full-amplitude error correction by the digital-to-time converter.
According to such an alternative embodiment, the gain calibration and 1/2T may also be performed by a digital-to-time converterckinThe calibration of the output clock ckout of the digital controlled oscillator 404 is realized, and the output clock error due to the error of the transistor and the line asymmetry can also be reduced.
The first multiplier 406, the first adder 408, and the second multiplier 409 according to embodiments of the present disclosure may be implemented in any manner as will occur to those of skill in the art, including but not limited to common adder and multiplier circuits. Similarly, the first and second error estimation circuits 405, 407 according to embodiments of the present disclosure may be implemented in any manner as would occur to one of skill in the art, including but not limited to using circuits capable of implementing least mean square error (LMS) estimation, or other circuits as would occur to one of skill in the art.
While the disclosure has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the present disclosure is not limited to the disclosed embodiments. Variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed subject matter, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps than those listed and the words "a" or "an" do not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Claims (10)
1. A fractional frequency divider, comprising:
a multi-modulus divider to generate a first division clock based on an input clock and a sequence of division coefficients;
a first flip-flop to generate a second divided clock based on the first divided clock;
a second flip-flop to generate a third divided clock based on the first divided clock;
a first multiplexer to select one of the first divided clock and the second divided clock as a first output divided clock; and
a second multiplexer to select one of the second divided clock and the third divided clock as a second output divided clock.
2. The fractional divider of claim 1, wherein the first multiplexer and the second multiplexer are to clock select based on a same clock select signal.
3. The fractional divider according to claim 1 or 2, wherein the first flip-flop is configured to receive an inverted signal of the input clock as a clock control signal, and the second flip-flop is configured to receive the input clock as a clock control signal.
4. A digitally controlled oscillator, comprising:
a fractional frequency divider, the fractional frequency divider comprising:
a multi-modulus divider to generate a first division clock based on an input clock and a sequence of division coefficients;
a first flip-flop to generate a second divided clock based on the first divided clock;
a second flip-flop to generate a third divided clock based on the first divided clock;
a first multiplexer to select one of the first divided clock and the second divided clock as a first output divided clock; and
a second multiplexer to select one of the second divided clock and the third divided clock as a second output divided clock;
a digital-to-time converter to generate an output clock based on the first output divided clock and the second output divided clock and to phase error correct the output clock according to a phase error signal;
a modulator for generating the sequence of division coefficients and a frequency error signal; and
an accumulator to accumulate the frequency error signal to obtain the phase error signal.
5. The digitally controlled oscillator of claim 4, wherein the modulator is further to generate a clock select signal and the first and second multiplexers are to perform clock selection based on the clock select signal.
6. The digitally controlled oscillator of claim 4, wherein the digital to time converter is a phase interpolator based digital to time converter.
7. The digitally controlled oscillator of any one of claims 4 to 6, wherein the first flip-flop is to receive an inverted signal of the input clock as a clock control signal, and wherein the second flip-flop is to receive the input clock as a clock control signal.
8. The digitally controlled oscillator of any of claims 4 to 6, wherein the output clock has a period resolution of 0.5 times the input clock.
9. A phase-locked loop circuit comprising:
a phase comparator for outputting an error signal based on a reference clock and a feedback clock, the error signal indicating a phase difference between the reference clock and the feedback clock;
a loop filter for loop filtering the error signal;
a voltage controlled oscillator to generate a voltage controlled oscillation signal based on the loop filtered error signal; and
the digitally controlled oscillator of any of claims 5 to 8, the digitally controlled oscillator to receive the voltage controlled oscillating signal as the input clock and to generate the output clock as the feedback clock.
10. The phase-locked loop circuit of claim 9, wherein the phase comparator is further configured to output a tardy signal based on the reference clock and the feedback clock, the tardy signal indicating a temporal order of the reference clock and the feedback clock relative to each other, wherein the modulator is further configured to generate a clock selection signal, and wherein the phase-locked loop circuit further comprises:
a first error estimation circuit to determine a clock phase error based on the late signal and the clock select signal;
a first multiplier for multiplying the clock phase error by the clock select signal to obtain a clock error signal;
a second error estimation circuit to determine a gain error based on the late signal and the phase error signal;
a first adder to add the clock error signal and the phase error signal to obtain an added error signal; and
a second multiplier to multiply the gain error and the added error signal for output to the digital-to-time converter for full amplitude error correction by the digital-to-time converter.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114696821A (en) * | 2022-06-02 | 2022-07-01 | 绍兴圆方半导体有限公司 | Open loop fractional frequency divider and clock system based on period-period gain correction |
| WO2024016896A1 (en) * | 2022-07-19 | 2024-01-25 | 普源精电科技股份有限公司 | Multi-phase clock generation circuit and method |
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2021
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114696821A (en) * | 2022-06-02 | 2022-07-01 | 绍兴圆方半导体有限公司 | Open loop fractional frequency divider and clock system based on period-period gain correction |
| WO2024016896A1 (en) * | 2022-07-19 | 2024-01-25 | 普源精电科技股份有限公司 | Multi-phase clock generation circuit and method |
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