WO2024060317A1 - Command decoding circuit and method thereof, and semiconductor memory - Google Patents

Abstract

Embodiments of the present disclosure provide a command decoding circuit and a method thereof, and a semiconductor memory. The command decoding circuit comprises: a clock processing module, which is configured to receive an initial clock signal, perform frequency division and phase division on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; a command sampling module, which is configured to receive a command address signal, sample the command address signal by using the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, and output a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal; and a decoding module, which is configured to decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal on the basis of the first clock signal and the third clock signal, and output a target decoded signal.

Description

A command decoding circuit and method thereof, and semiconductor memory

Cross-references to related applications

This disclosure is based on the Chinese patent application with the application number 202211139070.6, the filing date is September 19, 2022, and the invention name is "A command decoding circuit and method thereof, and semiconductor memory", and claims the priority of the Chinese patent application, The entire content of this Chinese patent application is hereby incorporated by reference into this disclosure.

Technical field

The present disclosure relates to the field of integrated circuit technology, and in particular, to a command decoding circuit and method thereof, and a semiconductor memory.

Background technique

With the continuous development of semiconductor technology, the design principles and working details of memory are also updated. Various circuits inside the memory need to be improved according to new needs to meet design requirements and achieve better storage performance.

Contents of the invention

The present disclosure provides a command decoding circuit, a method thereof, and a semiconductor memory, which can achieve correct decoding of command address signals.

In a first aspect, an embodiment of the present disclosure provides a command decoding circuit, where the command decoding circuit includes:

A clock processing module, configured to receive an initial clock signal, perform frequency division and phase division processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; wherein the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are a group of signals with the same clock period and phases that differ by 90 degrees in sequence, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal, and the clock period of the first clock signal is twice the clock period of the initial clock signal;

A command sampling module, connected to the clock processing module, is configured to receive a command address signal; use the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to respectively The command address signal is sampled, and the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are output;

a decoding module, connected to the clock processing module and the command sampling module, and configured to decode the first sampling signal, the second sampling signal, and the The third sampling signal and the fourth sampling signal are decoded and sampled, and a target decoded signal is output.

In some embodiments, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in odd clock cycles, and the rising edge of the second clock signal is aligned with the rising edge of the initial clock signal in odd clock cycles. Falling edge alignment, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in even-numbered clock cycles, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in even-numbered clock cycles. Alignment.

In some embodiments, the command decoding circuit further includes: a chip select sampling module, connected to the clock processing module and configured to receive a chip select signal; using the first clock signal and the third clock signal to respectively The chip select signal is sampled, and a first chip select sampling signal and a second chip select sampling signal are output; wherein the chip select signal is used to indicate whether the command address signal is valid or invalid.

In some embodiments, the command address signal, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal each include N-bit sub-signals, and the command sampling module It includes N command sampling units; the i-th command sampling unit is connected to the clock processing module and is configured to delay processing the i-th sub-signal of the command address signal to obtain a signal to be processed; using the i-th command sampling unit A clock signal is used to sample the signal to be processed, and the i-th sub-signal of the first sampling signal is output; the second clock signal is used to sample the signal to be processed, and the second sampling signal is output. The i-th sub-signal of the third sampling signal is used to sample the signal to be processed, the i-th sub-signal of the third sampling signal is output, and the fourth clock signal is used to perform sampling processing on the signal to be processed. Sampling process: output the i-th sub-signal of the fourth sampling signal, where i and N are positive integers, and i is less than or equal to N.

In some embodiments, the i-th command sampling unit includes a first delay unit, a first trigger, a second trigger, a third trigger and a fourth trigger; wherein the input end of the first delay unit receives the i-th sub-signal of the command address signal, and the output end of the first delay unit outputs the signal to be processed; the input end of the first trigger receives the signal to be processed, the clock end of the first trigger receives the first clock signal, and the output end of the first trigger outputs the i-th sub-signal of the first sampling signal; the input end of the second trigger receives the signal to be processed, the clock end of the second trigger receives the second clock signal, and the output end of the second trigger outputs the i-th sub-signal of the second sampling signal; the input end of the third trigger receives the signal to be processed, the clock end of the third trigger receives the third clock signal, and the output end of the third trigger outputs the i-th sub-signal of the third sampling signal; the input end of the fourth trigger receives the signal to be processed, the clock end of the fourth trigger receives the fourth clock signal, and the output end of the fourth trigger outputs the i-th sub-signal of the fourth sampling signal.

In some embodiments, the decoding module includes: a second delay unit connected to the clock processing module and configured to receive the first clock signal, delay the first clock signal, and output a first delayed clock signal; a third delay unit, connected to the clock processing module, configured to receive the third clock signal, delay the third clock signal, and output a third delayed clock signal; a decoding processing unit, connected to the command The sampling module, the second delay unit and the third delay unit are all connected, and are configured to compare the N-bit sub-signal of the first sampling signal and the N-bit sub-signal of the second sampling signal based on the third delayed clock signal. The signal is decoded and sampled, and a first decoded signal is output; the N-bit sub-signal of the third sampling signal and the N-bit sub-signal of the fourth sampling signal are decoded and sampled based on the first delayed clock signal, and output a second decoded signal; wherein the first decoded signal and the second decoded signal constitute the target decoded signal, and the first decoded signal indicates the content of the command address signal in the first initial clock cycle; the The second decoded signal indicates the content of the command address signal in the second initial clock cycle, and the initial clock cycle refers to the clock cycle of the initial clock signal.

In some embodiments, the decoding processing unit includes: a first decoding unit, connected to the command sampling module and the third delay unit, configured to process the N-bit sub-signal of the first sampling signal and the third delay unit. Perform logical operations on the N-bit sub-signals of the two sampled signals to output a first intermediate signal; use the third delayed clock signal to perform sampling processing on the first intermediate signal and output the first decoded signal; a second decoding unit, and The command sampling module is connected to the second delay unit, and is configured to perform logical operations on the N-bit sub-signal of the third sampling signal and the N-bit sub-signal of the fourth sampling signal, and output a second intermediate signal; using the The first delayed clock signal performs sampling processing on the second intermediate signal and outputs the second decoded signal.

In some embodiments, N=4; the first decoding unit includes a first logic unit and a fifth flip-flop; wherein the input end of the first logic unit receives the 4-bit sub-signal of the first sampling signal and The 4-bit sub-signal of the second sampling signal, the output terminal of the first logic unit outputs the first intermediate signal; the input terminal of the fifth flip-flop receives the first intermediate signal, and the input terminal of the fifth flip-flop receives the first intermediate signal. The clock terminal receives the third delayed clock signal, and the output terminal of the fifth flip-flop outputs the first decoded signal.

In some embodiments, N=4; the second decoding unit includes a second logic unit and a sixth flip-flop; the input end of the second logic unit receives the 4-bit sub-signal of the third sampling signal and the The 4-bit sub-signal of the fourth sampling signal, the output terminal of the second logic unit outputs the second intermediate signal; the input terminal of the sixth flip-flop receives the second intermediate signal, and the clock terminal of the sixth flip-flop After receiving the first delayed clock signal, the output terminal of the sixth flip-flop outputs the second decoded signal.

In some embodiments, the chip select sampling module includes a fourth delay unit, a seventh flip-flop and an eighth flip-flop; wherein the input end of the fourth delay unit receives the chip select signal, and the fourth delay unit receives the chip select signal. The output terminal of the delay unit outputs a chip select delay signal; the input terminal of the seventh flip-flop receives the chip select delay signal, the clock terminal of the seventh flip-flop receives the first clock signal, and the seventh flip-flop receives the chip select delay signal. The output terminal of the flip-flop outputs the first chip select sampling signal; the input terminal of the eighth flip-flop receives the chip select delay signal, and the clock terminal of the eighth flip-flop receives the third clock signal. The output terminal of the eighth flip-flop outputs the second chip select sampling signal.

In a second aspect, an embodiment of the present disclosure provides a command decoding method, the method comprising:

The initial clock signal is subjected to frequency division and phase separation processing to output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; wherein the first clock signal, the second clock signal, the The third clock signal and the fourth clock signal are a set of signals with the same clock period and a phase difference of 90 degrees. The rising edge of the first clock signal is aligned with the rising edge of the initial clock signal. The clock period of a clock signal is twice the clock period of the initial clock signal;

Use the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to sample the command address signal respectively, and output the first sampling signal, the second sampling signal and the third sampling signal. signal and the fourth sampled signal;

The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are decoded and sampled based on the first clock signal and the third clock signal to output a target Decode the signal.

In some embodiments, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in odd periods, and the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in odd periods. Alignment: the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in even-numbered periods, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in even-numbered periods.

In some embodiments, the method further includes: using the first clock signal and the third clock signal to respectively sample a chip select signal, and outputting a first chip select sampling signal and a second chip select sampling signal; wherein , the chip select signal is used to indicate whether the command address signal is valid or invalid.

In a third aspect, an embodiment of the present disclosure provides a semiconductor memory, comprising a command decoding circuit as described in any one of the first aspects.

In some embodiments, the semiconductor memory is a dynamic random access memory (DRAM), and the semiconductor memory complies with LPDDR6 memory specifications.

Embodiments of the present disclosure provide a command decoding circuit, a method thereof, and a semiconductor memory. The initial clock signal is frequency-divided and phase-divided to generate a first clock signal to a fourth clock signal, and the first clock signal to the fourth clock signal are used. The signal samples and decodes the command address signal to achieve correct decoding of the command address signal.

Description of the drawings

Figure 1 is a schematic structural diagram of a command decoding circuit provided by an embodiment of the present disclosure;

Figure 2 is a schematic diagram of a partial structure of a command decoding circuit provided by an embodiment of the present disclosure;

Figure 3 is a schematic diagram 2 of a partial structure of a command decoding circuit provided by an embodiment of the present disclosure;

Figure 4 is a schematic diagram 3 of a partial structure of a command decoding circuit provided by an embodiment of the present disclosure;

Figure 5 is a schematic structural diagram of another command decoding circuit provided by an embodiment of the present disclosure;

FIG6 is a fourth partial structural diagram of a command decoding circuit provided in an embodiment of the present disclosure;

Figure 7 is a signal timing diagram provided by an embodiment of the present disclosure;

Figure 8 is a schematic flowchart of a command decoding method provided by an embodiment of the present disclosure;

FIG. 9 is a schematic structural diagram of a semiconductor memory provided by an embodiment of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described here are only used to explain the relevant application, but not to limit the application. It should also be noted that, for convenience of description, only parts relevant to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the disclosure only and is not intended to limit the disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is understood that "some embodiments" may be the same subset or a different subset of all possible embodiments, and Can be combined with each other without conflict.

It should be noted that the terms "first\second\third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understandable that "first\second\third" Where permitted, the specific order or sequence may be interchanged so that the disclosed embodiments described herein can be practiced in an order other than that illustrated or described herein.

The following is an explanation of the professional terms involved in the embodiments of the present disclosure and the corresponding relationships of some terms:

Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM);

Synchronous Dynamic Random Access Memory (SDRAM);

Double Data Rate (DDR);

Low Power DDR (Low Power DDR, LPDDR)

Sixth generation LPDDR (6th LPDDR, LPDDR6)

D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF)

Command address input (Command/Address, CMD/ADD or CA for short)

Chip Select Input (CS)

Each embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings.

During the operation of the memory, the CA input and CS input need to be sampled and decoded according to the initial clock signal Clk. According to the regulations of LPDDR6, the command part of the CA input (hereinafter referred to as CA Command) lasts for 2 initial clock cycles, on the rising edge and falling edge of the first initial clock cycle and on the rising edge and falling edge of the second initial clock cycle. CA Command needs to be sampled; the CS input lasts for 2 initial clock cycles, and the CS input needs to be sampled on the rising edge of the first initial clock cycle and the rising edge of the second initial clock cycle. Here, the initial clock cycle refers to the clock cycle of the initial clock signal Clk.

Specifically, CA Command is a set of signals composed of 4 sub-signals, whose sub-signals are represented as CA0, CA1, CA2 and CA3 respectively. See Table 1, which shows a partial command truth table for LPDDR6. In Table 1, both the CA Command and CS inputs last for 2 initial clock cycles, R1 refers to the rising edge of the first initial clock cycle, F1 refers to the falling edge of the first initial clock cycle, and R2 refers to the second The rising edge of the first initial clock cycle, F2 refers to the falling edge of the second initial clock cycle, for CS, CA0 ~ CA3, "H" means high level state, "L" means low level state, "X ” indicates that the level status is not concerned. It should be understood that Table 1 comes from the industry standard document LPDDR6SPEC. Those skilled in the art can refer to LPDDR6SPEC to understand the meanings of various nouns and abbreviations involved. This part of the content does not affect the understanding of the embodiments of the present disclosure, so it will not be described in detail here.

Table 1

As shown in Table 1, the command decoding circuit in the semiconductor memory needs to be based on the R1 sampling result of CS input, the R2 sampling result of CS input, the R1 sampling result of CA Command, the F1 sampling result of CA Command, the R2 sampling result of CA Command, The F2 sampling result of CA Command is decoded to obtain the specific command of this CA Command (such as DES, NOP, PDE, SRE, ACT-1, ACT-2...).

In an embodiment of the present disclosure, refer to FIG. 1 , which shows a schematic structural diagram of a command decoding circuit 10 provided by an embodiment of the present disclosure. As shown in Figure 1, the command decoding circuit 10 includes:

The clock processing module 11 is configured to receive the initial clock signal Clk, perform frequency division and phase division processing on the initial clock signal Clk, and output the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1. ; Among them, the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1 are a group of signals with the same clock cycle and a phase difference of 90 degrees in sequence. The rising edge of the first clock signal Clk_R0 is the same as The rising edge of the initial clock signal Clk is aligned, and the clock period of the first clock signal Clk_R0 is twice the clock period of the initial clock signal Clk;

The command sampling module 12 is connected to the clock processing module 11 and is configured to receive the command address signal CA Command, and use the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1 to respectively analyze the command address. The signal CA Command is sampled and outputs the first sampling signal CA<N:0>_R0, the second sampling signal CA<N:0>_F0, the third sampling signal CA<N:0>_R1 and the fourth sampling signal CA<N :0>_F1;

The decoding module 13 is connected to the clock processing module 11 and the command sampling module 12, and is configured to process the first sampling signal CA<N:0>_R0 and the second sampling signal CA<N based on the first clock signal Clk_R0 and the third clock signal Clk_R1. :0>_F0, the third sampling signal CA<N:0>_R1 and the fourth sampling signal CA<N:0>_F1 are decoded and sampled, and a target decoded signal is output.

It should be noted that the command decoding circuit 10 of the embodiment of the present disclosure is applied to a semiconductor memory to realize the decoding requirements of the command address signal CA Command in LPDDR6. In addition, the command decoding circuit 10 can also be applied in a variety of circuit scenarios with similar requirements. The embodiments of the present disclosure will be explained and illustrated later with the decoding of the command address signal CA Command, but this does not constitute a relevant limitation.

As mentioned above, the command address signal CA Command lasts for 2 initial clock cycles, and the initial clock cycle refers to the clock cycle of the initial clock signal Clk. Please note that for Figures 1 to 7 and their corresponding text parts, the rising edge of the first initial clock cycle is represented by R0, the falling edge of the first initial clock cycle is represented by F0, and the rising edge of the second initial clock cycle is represented by F0. The edge is represented by R1, and the falling edge of the second initial clock cycle is represented by F1. This part is different from Table 1.

It should be noted that the rising edge of the first clock signal Clk_R0 is aligned with the rising edge of the initial clock signal Clk in odd clock cycles, and the rising edge of the second clock signal Clk_F0 is aligned with the falling edge of the initial clock signal Clk in odd clock cycles. The rising edge of the third clock signal Clk_R1 is aligned with the rising edge of the initial clock signal Clk in even-numbered clock cycles, and the rising edge of the fourth clock signal Clk_F1 is aligned with the falling edge of the initial clock signal Clk in even-numbered clock cycles.

In this way, the rising edges of the first clock signal Clk_R0 and the third clock signal Clk_R1 are alternately aligned with the rising edges of the initial clock signal Clk, and the rising edges of the second clock signal Clk_F0 and the fourth clock signal Clk_F1 are alternately aligned with the rising edges of the initial clock signal Clk. The falling edge of the clock signal Clk is aligned. Therefore, the first sampling signal can indicate the sampling result of the command address signal CA Command at the rising edge of the first initial clock cycle, and the second sampling signal can indicate the sampling result of the command address signal CA Command at the falling edge of the first initial clock cycle. As a result, the third sampling signal can indicate the sampling result of the command address signal CA Command at the rising edge of the second initial clock cycle, and the fourth sampling signal can indicate the sampling result of the command address signal CA Command at the falling edge of the second initial clock cycle. As a result, subsequent decoding processing can meet the decoding requirements of LPDDR6, allowing the semiconductor memory to work correctly.

It should be noted that the clock processing module 11 may include a frequency dividing module and a phase dividing module; where,

The frequency dividing module is configured to receive the initial clock signal Clk, divide the initial clock signal Clk, and output the divided clock signal; the clock period of the divided clock signal is twice the clock period of the initial clock signal Clk;

The phase separation module is connected to the frequency division module and is configured to receive the frequency division clock signal, perform phase separation processing on the frequency division clock signal, and output the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock Signal Clk_F1.

It should be noted that the frequency dividing module can be implemented using a two-frequency dividing component composed of a NOT gate and a D-type flip-flop; the phase splitting module can be implemented using multiple D-type flip-flops and delay devices.

In some embodiments, the command address signal CA Command, the first sampling signal CA<N:0>_R0, the second sampling signal CA<N:0>_F0, the third sampling signal CA<N:0>_R1 and the fourth The sampling signals CA<N:0>_F1 each include N-bit sub-signals.

Taking N=4 as an example, the command address signal CA Command can include four sub-signals CA0, CA1, CA2, and CA3, and the first sampling signal CA<N:0>_R0 can include four sub-signals CA0_R0, CA1_R0, CA2_R0, and CA3_R0. ;The second sampling signal CA<N:0>_F0 may include the four sub-signals CA0_F0, CA1_F0, CA2_F0, and CA3_F0; the third sampling signal CA<N:0>_R1 may include the four sub-signals CA0_R1, CA1_R1, CA2_R1, and CA3_R1 ; The fourth sampling signal may include four sub-signals: CA0_F1, CA1_F1, CA2_F1, and CA3_F1. The embodiments of this disclosure will be explained later using N=4 as an example, but the value of N can be adjusted according to the needs of the actual scenario.

Correspondingly, see FIG. 2 , which shows a schematic diagram 1 of a partial structure of a command decoding circuit 10 provided by an embodiment of the present disclosure. As shown in Figure 2, the command sampling module 12 includes N command sampling units (Figure 2 takes N=4 as an example). The i-th command sampling unit is connected to the clock processing module 11 and is configured to delay processing the i-th sub-signal of the command address signal CA Command to obtain a signal to be processed; use the first clock signal Clk_R0 to sample the signal to be processed and output The i-th sub-signal of the first sampling signal CA<N:0>_R0; the second clock signal Clk_F0 is used to sample the signal to be processed, and the i-th sub-signal of the second sampling signal CA<N:0>_F0 is output. The third clock signal Clk_R1 samples the signal to be processed and outputs the i-th sub-signal of the third sampling signal CA<N:0>_R1. The fourth clock signal Clk_F1 is used to sample the signal to be processed and outputs the fourth sampling signal CA<N :0>_F1's i-th sub-signal, where i and N are positive integers, and i is less than or equal to N.

In some embodiments, as shown in FIG. 2 , the i-th command sampling unit includes a first delay unit 121, a first flip-flop 122, a second flip-flop 123, a third flip-flop 124 and a fourth flip-flop 125. In Figure 2, only the devices in the first command sampling unit are labeled, others can be understood by reference.

The input terminal of the first delay unit 121 receives the i-th sub-signal CAi of the command address signal, and the output terminal of the first delay unit 121 outputs the signal to be processed CAi_D; the input terminal of the first flip-flop 122 receives the signal to be processed CAi_D, and the first trigger The clock terminal of the circuit breaker 122 receives the first clock signal Clk_R0, and the output terminal of the first flip-flop 122 outputs the i-th sub-signal CAi_R0 of the first sampling signal; the input terminal of the second flip-flop 123 receives the signal to be processed CAi_D, and the second flip-flop 123 The clock terminal of 123 receives the second clock signal Clk_F0, and the output terminal of the second flip-flop 123 outputs the i-th sub-signal CAi_F0 of the second sampling signal; the input terminal of the third flip-flop 124 receives the signal to be processed CAi_D, and the third flip-flop 124 The clock terminal receives the third clock signal Clk_R1, the output terminal of the third flip-flop 124 outputs the i-th sub-signal CAi_R1 of the third sampling signal; the input terminal of the fourth flip-flop 125 receives the signal to be processed CAi_D, and the input terminal of the fourth flip-flop 125 The clock terminal receives the fourth clock signal Clk_F1, and the output terminal of the fourth flip-flop 125 outputs the i-th sub-signal CAi_F1 of the fourth sampling signal.

It should be noted that each command sampling unit has its own first delay unit, first flip-flop, second flip-flop, third flip-flop and fourth flip-flop.

Taking N=4 as an example, for the first command sampling unit, the first delay unit 121 delays CA0 to output CA0_D, and uses the first clock signal Clk_R0 to sample CA0_D through the first flip-flop 122 to output CA0_R0. 123 uses the second clock signal Clk_F0 to sample CA0_D to output CA0_F0, uses the third flip-flop 124 to use the third clock signal Clk_R1 to sample CA0_D to output CA0_R1, and uses the fourth flip-flop 125 to use the fourth clock signal Clk_F1 to sample CA0_D to output CA0_F1.

For the second command sampling unit, the first delay unit delays CA1 to output CA1_D, uses the first clock signal Clk_R0 to sample CA1_D through the first flip-flop to output CA1_R0, and uses the second clock signal Clk_F0 to sample CA1_D through the second flip-flop. Output CA1_F0, sample CA1_D using the third clock signal Clk_R1 through the third flip-flop to output CA1_R1, and sample CA1_D using the fourth clock signal Clk_F1 through the fourth flip-flop to output CA1_F1.

For the third command sampling unit, the first delay unit delays CA2 to output CA2_D, uses the first clock signal Clk_R0 to sample CA2_D through the first flip-flop to output CA2_R0, and uses the second flip-flop to sample CA2_D using the second clock signal Clk_F0 to output CA2_D. Output CA2_F0, sample CA2_D using the third clock signal Clk_R1 through the third flip-flop to output CA2_R1, and sample CA2_D using the fourth clock signal Clk_F1 through the fourth flip-flop to output CA2_F1.

For the fourth command sampling unit, the first delay unit delays CA3 to output CA3_D, uses the first clock signal Clk_R0 to sample CA3_D through the first flip-flop to output CA3_R0, and uses the second flip-flop to sample CA3_D using the second clock signal Clk_F0 to output CA3_D. Output CA3_F0, sample CA3_D using the third clock signal Clk_R1 through the third flip-flop to output CA3_R1, and sample CA3_D using the fourth clock signal Clk_F1 through the fourth flip-flop to output CA3_F1.

In this way, CA0_R0, CA1_R0, CA2_R0, and CA3_R0 together form the aforementioned first sampling signal CA<N:0>_R0, and CA0_F0, CA1_F0, CA2_F0, and CA3_F0 together form the aforementioned second sampling signal CA<N:0>_F0, CA0_R1, CA1_R1, CA2_R1, and CA3_R1 together constitute the aforementioned third sampling signal CA<N:0>_R1, and CA0_F1, CA1_F1, CA2_F1, and CA3_F1 together constitute the aforementioned fourth sampling signal CA<N:0>_F1.

Here, the aforementioned first delay unit (or DlyTrim) can be formed by conventional delay devices. Further, the first delay unit can be designed as a circuit with adjustable delay parameters or a circuit with non-adjustable delay parameters, and its function is to delay the command address signal to achieve delay matching between the command address signal and the four clock signals (the first clock signal to the fourth clock signal).

In some embodiments, as shown in Figure 3 (Figure 3 takes N=4 as an example), the decoding module 13 includes:

The second delay unit 131 is connected to the clock processing module 11 and is configured to receive the first clock signal Clk_R0, delay the first clock signal Clk_R0, and output the first delayed clock signal Clk_R0d;

The third delay unit 132 is connected to the clock processing module 11 and is configured to receive the third clock signal Clk_R1, delay the third clock signal Clk_R1, and output the third delayed clock signal Clk_R1d;

The decoding processing unit 133 is connected to the command sampling module 12, the second delay unit 131 and the third delay unit 132, and is configured to decode and sample the N-bit sub-signal of the first sampling signal CA<N:0>_R0 and the N-bit sub-signal of the second sampling signal CA<N:0>_F0 based on the third delayed clock signal Clk_R1d, and output a first decoded signal CmdR1; decode and sample the N-bit sub-signal of the third sampling signal CA<N:0>_R1 and the N-bit sub-signal of the fourth sampling signal based on the first delayed clock signal Clk_R0d, and output a second decoded signal CmdR0.

It should be noted that the first decoded signal CmdR1 and the second decoded signal CmdR0 constitute the target decoded signal. The first decoding signal CmdR1 indicates the content of the command address signal CA Command in the first initial clock cycle; the second decoding signal CmdR0 indicates the content of the command address signal CA Command in the second initial clock cycle. As mentioned above, the initial clock cycle refers to the clock cycle of the initial clock signal Clk.

It should be noted that the second delay unit 131 and the third delay unit 132 may have the same or different principles as the first delay unit. Specifically, the second delay unit 131 and the third delay unit 132 may also be called ClkDly, and are also composed of conventional delay devices. Further, the second delay unit 131 (or the third delay unit 132) may be designed as a circuit with adjustable delay parameters, or may be designed as a circuit with unadjustable delay parameters. The function of the second delay unit 131 is to delay the first clock signal Clk_R0 to achieve delay matching between the first clock signal Clk_R0 and the first intermediate signal. The function of the second delay unit 131 is to delay the third clock signal Clk_R1 To achieve delay matching between the third clock signal Clk_R1 and the second intermediate signal.

In some embodiments, as shown in FIG. 4 ( FIG. 4 is shown by taking N=4 as an example), the decoding processing unit 133 includes:

The first decoding unit 21 is connected to the command sampling module 12 and the third delay unit 132, and is configured to decode the N-bit sub-signal of the first sampling signal CA<N:0>_R0 and the second sampling signal CA<N:0>_F0. Perform logical operations on the N-bit sub-signals and output the first intermediate signal; use the third delayed clock signal Clk_R1d to sample the first intermediate signal and output the first decoded signal CmdR1;

The second decoding unit 22 is connected to the command sampling module 12 and the second delay unit 131, and is configured to decode the N-bit sub-signal of the third sampling signal CA<N:0>_R1 and the fourth sampling signal CA<N:0>_F1. The N-bit sub-signals perform logical operations and output the second intermediate signal; the first delayed clock signal Clk_R0d is used to sample the second intermediate signal and output the second decoded signal CmdR0.

In a specific embodiment, taking N=4 as an example, as shown in Figure 5, the first decoding unit 21 includes a first logic unit 211 and a fifth flip-flop 212; wherein, the input terminal of the first logic unit 211 After receiving the 4-bit sub-signals of the first sampling signal (i.e., CA0_R0, CA1_R0, CA2_R0, CA3_R0) and the 4-bit sub-signals of the second sampling signal (i.e., CA0_F0, CA1_F0, CA2_F0, CA3_F0), the output end of the first logic unit 211 outputs the first Intermediate signal; the input terminal of the fifth flip-flop 212 receives the first intermediate signal, the clock terminal of the fifth flip-flop 212 receives the third delayed clock signal Clk_R1d, and the output terminal of the fifth flip-flop 212 outputs the first decoded signal CmdR1.

Similarly, as shown in Figure 4, the second decoding unit 22 includes a second logic unit 221 and a sixth flip-flop 222; the input end of the second logic unit 221 receives the 4-bit sub-signals of the third sampling signal (i.e., CA0_R1, CA1_R1, CA2_R1, CA3_R1) and the 4-bit sub-signal of the fourth sampling signal (i.e., CA0_F1, CA1_F1, CA2_F1, CA3_F1), the output terminal of the second logic unit 221 outputs the second intermediate signal; the input terminal of the sixth flip-flop 222 receives the second intermediate signal signal, the clock terminal of the sixth flip-flop 222 receives the first delayed clock signal Clk_R1d, and the output terminal of the sixth flip-flop 222 outputs the second decoded signal CmdR0.

It should be noted that the first logic unit 211 (or the second logic unit 221) can be implemented by a variety of logic devices, such as NAND gates, NOT gates, XOR gates, etc., and specific decoding rules (or so-called Decoding rules), which are not limited by the embodiments of this disclosure.

In this way, the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1 are used to sample the command address signal CA Command, and the values of the command address signal CA Command in the first initial clock cycle are obtained respectively. The sampling result of the rising edge, the sampling result of the command address signal CA Command on the falling edge of the first initial clock cycle, the sampling result of the command address signal CA Command on the rising edge of the second initial clock cycle and the command address signal CA Command on The sampling result of the falling edge of the second initial clock cycle is used for subsequent decoding processing, which can achieve the correct decoding of the command address signal in LPDDR6 and ensure the normal operation of the memory.

In addition, according to the regulations of LPDDR6, the chip select signal CS also lasts for 2 initial clock cycles, and the chip select signal CS needs to be sampled on the rising edge of the first initial clock cycle and the rising edge of the second initial clock cycle.

Therefore, in some embodiments, as shown in Figure 5, the command decoding circuit 10 further includes:

The chip select sampling module 14 is connected to the clock processing module 11 and configured to receive the chip select signal CS; and use the first clock signal Clk_R0 and the third clock signal Clk_R1 to sample the chip select signal CS respectively, and output the first chip select sampling signal CS_R0 and the second chip select sampling signal CS_R1.

It should be noted that the chip select signal CS is used to indicate whether the command address signal CA Command is valid or invalid. Here, the command decoding circuit 10 is applied to a semiconductor memory. If the semiconductor memory is selected, the waveform of the chip select signal CS meets the first condition at this time, and the command address signal CA Command is valid; if the memory is not selected, at this time The waveform of the chip select signal CS does not meet the first condition, and the command address signal CA Command is invalid.

Exemplarily, on the basis of Figure 2, as shown in Figure 6, the chip select sampling module 14 includes a fourth delay unit 141, a seventh flip-flop 142 and an eighth flip-flop 143; wherein, the input of the fourth delay unit 141 The terminal receives the chip select signal CS, the output terminal of the fourth delay unit 141 outputs the chip select delay signal CS_D; the input terminal of the seventh flip-flop 142 receives the chip select delay signal CS_D, and the clock terminal of the seventh flip-flop 142 receives the first clock signal Clk_R0, the output terminal of the seventh flip-flop 142 outputs the first chip select sampling signal CS_R0; the input terminal of the eighth flip-flop 143 receives the chip select delay signal CS_D, and the clock terminal of the eighth flip-flop 143 receives the third clock signal Clk_R1. The output terminal of the eight flip-flop 143 outputs the second chip select sampling signal CS_R1.

It should be noted that the fourth delay unit 141 and the first delay unit 121 have the same structure, that is, the fourth delay unit 141 can also be implemented by a variety of delay devices.

The aforementioned first to eighth flip-flops can all be implemented by D-type flip-flops, which can use the rising edge of the clock signal (i.e., the signal received at the clock terminal) to sample the input signal (i.e., the signal received at the input terminal). , get the output signal (that is, the signal at the output end). In addition, the first to sixth flip-flops 222 each also have a reset terminal, which receives a corresponding reset signal to implement reset processing.

Specifically, a specific explanation of signal timing changes is provided by taking the command address signal CA Command including 4-bit sub-signals as an example. Please refer to FIG. 7 , which shows a signal timing diagram provided by an embodiment of the present disclosure. In Figure 7, the command address signal is represented by CA<3:0>, the first sampling signal is represented by CA<3:0>_R0, the second sampling signal is represented by CA<3:0>_F0, and the third sampling signal is represented by is CA<3:0>_R1, and the fourth sampling signal is represented as CA<3:0>_F1. As shown in Figure 7, the initial clock signal Clk generates the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1 after frequency division and phase division. The first clock signal Clk_R0 sampling command address The signal CA<3:0> generates the first sampling signal CA<3:0>_R0, the second clock signal Clk_F0 samples the command address signal CA<3:0> to generate the second sampling signal CA<3:0>_F0, and the third The clock signal Clk_R1 samples the command address signal CA<3:0> to generate the third sampling signal CA<3:0>_R1, and the fourth clock signal Clk_F1 samples the command address signal CA<3:0> to generate the fourth sampling signal CA<3: 0>_F1; then, the first sampling signal CA<3:0>_R0, the second sampling signal CA<3:0>_F0, the third sampling signal CA<3:0>_R1 and the fourth sampling signal CA<3: 0>_F1 is decoded to obtain the first decoded signal Cmd_R1 and the second decoded signal Cmd_R0 (not shown in Figure 7); at the same time, the first clock signal Clk_R0 samples the initial chip select signal CS to generate the first chip select sampling signal CS_R0. The second clock signal Clk_R1 samples the initial chip select signal CS to generate the first chip select sampling signal CS_R1 (not shown in Figure 7); finally, the first decoded signal Cmd_R0, the second decoded signal Cmd_R1, the first chip select sampled signal CS_R0 and the second The chip select sampling signal CS_R1 is then jointly decoded, and the decoding result is sampled through the command sampling clock signal ClkCmd_R1 to obtain the final target command signal Command. Here, the target command signal Command can indicate the specific content of this CA Command, such as PDE, SRE, ACT-1, ACT-2... in Table 1...

In addition, as shown in Figure 7, the initial state of the initial chip select signal CS is a low level. When the initial chip select signal CS generates two consecutive pulses, it indicates that the semiconductor memory is selected, that is, the current CA Command is valid.

The embodiment of the present disclosure provides a command decoding circuit, which divides the frequency and phase of the initial clock signal to generate four clock signals (i.e., the first clock signal to the fourth clock signal), and uses the four clock signals to decode the command address signal. Sampling is performed, and the first clock signal and the third clock signal are used to sample the chip select signal, so as to subsequently decode the target command signal Command. In this way, the command decoding circuit can sample and decode the command address signal that lasts for 2 initial clock cycles and the chip select signal that lasts for 2 initial clock cycles to achieve correct analysis of the command.

In another embodiment of the present disclosure, see FIG. 8 , which shows a schematic flowchart of a command decoding method provided by an embodiment of the present disclosure. As shown in Figure 8, the method includes:

S301: Perform frequency division and phase division processing on the initial clock signal, and output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal; wherein, the first clock signal, the second clock signal, the third clock signal are The signal and the fourth clock signal are a set of signals with the same clock period and a phase difference of 90 degrees in sequence. The rising edge of the first clock signal is aligned with the rising edge of the initial clock signal. The clock period of the first clock signal is the clock of the initial clock signal. 2 times the period.

S302: Use the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to sample the command address signal respectively, and output the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal. .

S303: Decode and sample the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal based on the first clock signal and the third clock signal, and output the target decoded signal.

In some embodiments, the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in odd cycles, the rising edge of the second clock signal is aligned with the falling edge of the initial clock signal in odd cycles, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal in even cycles, and the rising edge of the fourth clock signal is aligned with the falling edge of the initial clock signal in even cycles.

In some embodiments, the first clock signal and the third clock signal are used to sample the chip select signal respectively, and the first chip select sampling signal and the second chip select sampling signal are output; wherein the chip select signal is used to indicate the command address signal. Valid or invalid.

The embodiment of the present disclosure provides a command decoding circuit, which divides the frequency and phase of the initial clock signal to generate four clock signals (i.e., the first clock signal to the fourth clock signal), and uses the four clock signals to decode the command address signal. Sampling is performed, and the first clock signal and the third clock signal are used to sample the chip select signal, so as to subsequently decode the target command signal Command. In this way, the command decoding circuit can sample and decode the command address signal that lasts for 2 initial clock cycles and the chip select signal that lasts for 2 initial clock cycles to achieve correct analysis of the command.

In yet another embodiment of the present disclosure, see FIG. 9 , which shows a schematic structural diagram of a semiconductor memory 40 provided by an embodiment of the present disclosure. As shown in FIG. 9 , the semiconductor memory 40 may include the command decoding circuit 10 described in any of the previous embodiments.

In the embodiment of the present disclosure, the semiconductor memory 40 may be a dynamic random access memory DRAM, and the semiconductor memory complies with the regulations of LPDDR6.

The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of the present disclosure.

It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field of the present disclosure can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Industrial applicability

Embodiments of the present disclosure provide a command decoding circuit, a method thereof, and a semiconductor memory. The initial clock signal is frequency-divided and phase-divided to generate a first clock signal to a fourth clock signal, and the first clock signal to the fourth clock signal are used. The signal samples and decodes the command address signal to achieve correct decoding of the command address signal.

Claims (15)

1. A command decoding circuit, the command decoding circuit comprising:

   A clock processing module configured to receive an initial clock signal, perform frequency division and phase division processing on the initial clock signal, and output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; wherein, the The first clock signal, the second clock signal, the third clock signal and the fourth clock signal are a group of signals with the same clock cycle and a phase difference of 90 degrees in sequence. The rising edge of the first clock signal is the same as the rising edge of the first clock signal. The rising edges of the initial clock signal are aligned, and the clock period of the first clock signal is twice the clock period of the initial clock signal;

   a command sampling module, connected to the clock processing module, configured to receive a command address signal; sample the command address signal using the first clock signal, the second clock signal, the third clock signal and the fourth clock signal, respectively, and output a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal;

   a decoding module, connected to the clock processing module and the command sampling module, and configured to decode the first sampling signal, the second sampling signal, and the The third sampling signal and the fourth sampling signal are decoded and sampled, and a target decoded signal is output.
2. The command decoding circuit according to claim 1, wherein the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in odd clock cycles, and the rising edge of the second clock signal is aligned with the initial The clock signal is aligned on the falling edge of the odd clock period, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal on the even clock period, and the rising edge of the fourth clock signal is aligned with the initial clock signal. Aligned on the falling edge of even clock cycles.
3. The command decoding circuit according to any one of claims 1-2, wherein the command decoding circuit further includes:

   a chip select sampling module, connected to the clock processing module and configured to receive a chip select signal; use the first clock signal and the third clock signal to respectively sample the chip select signal and output a first chip select sample signal and the second chip select sampling signal;

   Wherein, the chip select signal is used to indicate whether the command address signal is valid or invalid.
4. The command decoding circuit according to claim 1, wherein the command address signal, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal each include N-bit sub-signals, and the command sampling module includes N command sampling units;

   The i-th command sampling unit is connected to the clock processing module and configured to perform delay processing on the i-th sub-signal of the command address signal to obtain a signal to be processed; using the first clock signal to process the signal to be processed The processed signal is subjected to sampling processing, and the i-th sub-signal of the first sampling signal is output; the signal to be processed is sampled using the second clock signal, and the i-th sub-signal of the second sampling signal is output, using The third clock signal samples the signal to be processed and outputs the i-th sub-signal of the third sampling signal. The fourth clock signal is used to sample the signal to be processed and outputs the i-th sub-signal. The i-th sub-signal of the four-sampled signal,

   Wherein, i and N are positive integers, and i is less than or equal to N.
5. The command decoding circuit according to claim 4, wherein the i-th command sampling unit comprises a first delay unit, a first trigger, a second trigger, a third trigger and a fourth trigger; wherein,

   The input terminal of the first delay unit receives the i-th sub-signal of the command address signal, and the output terminal of the first delay unit outputs the signal to be processed;

   The input terminal of the first flip-flop receives the signal to be processed, the clock terminal of the first flip-flop receives the first clock signal, and the output terminal of the first flip-flop outputs the first sampling signal. i-th sub-signal;

   The input terminal of the second flip-flop receives the signal to be processed, the clock terminal of the second flip-flop receives the second clock signal, and the output terminal of the second flip-flop outputs the second sampling signal. i-th sub-signal;

   The input terminal of the third flip-flop receives the signal to be processed, the clock terminal of the third flip-flop receives the third clock signal, and the output terminal of the third flip-flop outputs the third sampling signal. i-th sub-signal;

   The input terminal of the fourth flip-flop receives the signal to be processed, the clock terminal of the fourth flip-flop receives the fourth clock signal, and the output terminal of the fourth flip-flop outputs the fourth sampling signal. The i-th sub-signal.
6. The command decoding circuit according to claim 4, wherein the decoding module includes:

   a second delay unit, connected to the clock processing module, configured to receive the first clock signal, delay the first clock signal, and output the first delayed clock signal;

   A third delay unit is connected to the clock processing module and configured to receive the third clock signal, delay the third clock signal, and output a third delayed clock signal;

   a decoding processing unit connected to the command sampling module, the second delay unit and the third delay unit, and configured to decode and sample the N-bit sub-signal of the first sampling signal and the N-bit sub-signal of the second sampling signal based on the third delayed clock signal, and output a first decoded signal; decode and sample the N-bit sub-signal of the third sampling signal and the N-bit sub-signal of the fourth sampling signal based on the first delayed clock signal, and output a second decoded signal;

   Wherein, the first decoding signal and the second decoding signal constitute the target decoding signal, and the first decoding signal indicates the content of the command address signal in the first initial clock cycle; the second decoding signal Indicates the content of the command address signal in the second initial clock cycle, and the initial clock cycle refers to the clock cycle of the initial clock signal.
7. The command decoding circuit according to claim 6, wherein the decoding processing unit includes:

   A first decoding unit, connected to the command sampling module and the third delay unit, is configured to perform logical operations on the N-bit sub-signal of the first sampling signal and the N-bit sub-signal of the second sampling signal, and output the An intermediate signal; using the third delayed clock signal to sample the first intermediate signal and output the first decoded signal;

   The second decoding unit is connected to the command sampling module and the second delay unit, and is configured to perform logical operations on the N-bit sub-signal of the third sampling signal and the N-bit sub-signal of the fourth sampling signal, and output the N-bit sub-signal of the third sampling signal. Two intermediate signals: use the first delayed clock signal to perform sampling processing on the second intermediate signal, and output the second decoded signal.
8. The command decoding circuit according to claim 7, wherein N=4; the first decoding unit includes a first logic unit and a fifth flip-flop; wherein,

   The input terminal of the first logic unit receives the 4-bit sub-signal of the first sampling signal and the 4-bit sub-signal of the second sampling signal, and the output terminal of the first logic unit outputs a first intermediate signal; The input terminal of the fifth flip-flop receives the first intermediate signal, the clock terminal of the fifth flip-flop receives the third delayed clock signal, and the output terminal of the fifth flip-flop outputs the first decoded signal.
9. The command decoding circuit according to claim 7, wherein N=4; the second decoding unit includes a second logic unit and a sixth flip-flop;

   The input terminal of the second logic unit receives the 4-bit sub-signal of the third sampling signal and the 4-bit sub-signal of the fourth sampling signal, and the output terminal of the second logic unit outputs a second intermediate signal; The input terminal of the sixth flip-flop receives the second intermediate signal, the clock terminal of the sixth flip-flop receives the first delayed clock signal, and the output terminal of the sixth flip-flop outputs the second decoded signal.
10. The command decoding circuit according to claim 3, wherein the chip select sampling module includes a fourth delay unit, a seventh flip-flop and an eighth flip-flop; wherein,

    The input terminal of the fourth delay unit receives the chip select signal, and the output terminal of the fourth delay unit outputs the chip select delay signal;

    The input terminal of the seventh flip-flop receives the chip select delay signal, the clock terminal of the seventh flip-flop receives the first clock signal, and the output terminal of the seventh flip-flop outputs the first chip select sample signal;

    The input end of the eighth flip-flop receives the chip selection delay signal, the clock end of the eighth flip-flop receives the third clock signal, and the output end of the eighth flip-flop outputs the second chip selection sampling signal.
11. A command decoding method, wherein the method includes:

    The initial clock signal is subjected to frequency division and phase separation processing to output a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; wherein the first clock signal, the second clock signal, the The third clock signal and the fourth clock signal are a set of signals with the same clock period and a phase difference of 90 degrees. The rising edge of the first clock signal is aligned with the rising edge of the initial clock signal. The clock period of a clock signal is twice the clock period of the initial clock signal;

    Use the first clock signal, the second clock signal, the third clock signal and the fourth clock signal to sample the command address signal respectively, and output the first sampling signal, the second sampling signal and the third sampling signal. signal and the fourth sampled signal;

    The first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal are decoded and sampled based on the first clock signal and the third clock signal to output a target Decode the signal.
12. The command decoding method according to claim 11, wherein the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal in odd periods, and the rising edge of the second clock signal is aligned with the initial clock signal. The signals are aligned on the falling edge of the odd-numbered period, the rising edge of the third clock signal is aligned with the rising edge of the initial clock signal on the even-numbered period, and the rising edge of the fourth clock signal is aligned with the initial clock signal on the even-numbered period. falling edge alignment.
13. The command decoding method according to claim 12, wherein the method further includes:

    Using the first clock signal and the third clock signal to respectively sample the chip select signal, and output the first chip select sampling signal and the second chip select sampling signal;

    Wherein, the chip select signal is used to indicate whether the command address signal is valid or invalid.
14. A semiconductor memory including the command decoding circuit according to any one of claims 1 to 10.
15. The semiconductor memory of claim 14, wherein the semiconductor memory is a dynamic random access memory (DRAM), and the semiconductor memory complies with LPDDR6 memory specifications.

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