WO2024087781A1 - Command decoding circuit and semiconductor memory - Google Patents

Abstract

The present disclosure provides a command decoding circuit and a semiconductor memory, comprising using a first clock signal and a second clock signal to carry out processing on a chip selection signal and outputting a first control signal and a second control signal; using a third clock signal and a fourth clock signal to process the chip selection signal and outputting a third control signal and a fourth control signal; and using the first control signal to the fourth control signal to sample a command address signal and outputting a target sampling signal.

Description

A command decoding circuit and semiconductor memory

CROSS-REFERENCE TO RELATED APPLICATIONS

This disclosure claims priority to a Chinese patent application filed with the Chinese Patent Office on October 27, 2022, with application number 202211324749.2 and application name “A command decoding circuit and semiconductor memory”, the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to, but is not limited to, a command decoding circuit and a semiconductor memory.

Background technique

With the continuous development of semiconductor technology, the design principles and working details of memory are also being updated. Various circuits inside the memory need to be improved according to new requirements to meet design requirements and achieve better storage performance. For dynamic random access memory (DRAM), it is necessary to sample and decode the command address signal through the command decoding circuit to obtain the current operation instruction. At present, the power consumption of the command decoding circuit is relatively high, which affects the further development of memory performance.

Summary of the invention

The present disclosure provides a command decoding circuit and a semiconductor memory.

In a first aspect, an embodiment of the present disclosure provides a command decoding circuit, the command decoding circuit comprising:

A clock generating circuit configured to generate a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; wherein the clock periods of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are the same and the phases thereof are 90 degrees different from each other;

a first conversion circuit, connected to the clock generation circuit, configured to receive a chip select signal, perform multiple sampling and logic processing on the chip select signal using the first clock signal and the second clock signal, and output a first control signal and a second control signal; wherein, if the chip select signal meets a preset condition, both the first control signal and the second control signal have pulses;

a second conversion circuit, connected to the clock generation circuit, configured to receive the chip select signal, perform multiple sampling and logic processing on the chip select signal using the third clock signal and the fourth clock signal, and output a third control signal and a fourth control signal; wherein, if the chip select signal meets a preset condition, both the third control signal and the fourth control signal have pulses;

The command sampling circuit is connected to both the first conversion circuit and the second conversion circuit, and is configured to receive a command address signal, sample the command address signal using the first control signal, the second control signal, the third control signal, and the fourth control signal, and output a target sampling signal.

In some embodiments, when the chip select signal does not meet a preset condition, the first control signal, the second control signal, the third control signal, and the fourth control signal all maintain a constant level state.

In some embodiments, the clock generation circuit is configured to receive an initial clock signal, perform frequency division and phase division processing on the external initial clock signal, and output the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal;

The clock period of the first clock signal is twice the clock period of the initial clock signal, and the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal.

In some embodiments, the chip select signal is used to indicate whether the command address signal is valid or invalid. If the chip select signal meets a preset condition, the command address signal is valid; if the chip select signal does not meet the preset condition, the command address signal is invalid; the command address signal lasts for 2 initial clock cycles, and the initial clock cycle refers to the clock cycle of the initial clock signal; the preset condition refers to the presence of a level change edge in the chip select signal in the first initial clock cycle, and the presence of a level change edge in the chip select signal in the second initial clock cycle.

In some embodiments, when the chip select signal meets preset conditions, the pulse width of the first control signal, the pulse width of the second control signal, the pulse width of the third control signal and the pulse width of the fourth control signal are all the same, and the pulse width of the first control signal is the same as the initial clock cycle; wherein, the pulse leading edge of the first control signal is aligned with the rising edge of the first clock signal, the pulse leading edge of the second control signal is aligned with the rising edge of the second clock signal, the pulse leading edge of the third control signal is aligned with the rising edge of the third clock signal, and the pulse leading edge of the fourth control signal is aligned with the rising edge of the fourth clock signal.

In some embodiments, the first conversion circuit includes a first sampling unit, a first logic unit, and a second logic unit; wherein the first sampling unit is configured to use the first clock signal to sample the chip select signal to generate a first intermediate signal, and use the first The inverted signal of the clock signal samples the first intermediate signal to generate a second intermediate signal, and uses the second clock signal to sample the second intermediate signal to generate a third intermediate signal; the first logic unit is connected to the first sampling unit, and is configured to perform an AND operation on the first intermediate signal and the first clock signal, and output the first control signal; the second logic unit is connected to the first sampling unit, and is configured to perform an AND operation on the third intermediate signal and the second clock signal, and output the second control signal; wherein, if the chip select signal meets the preset conditions, then both the first intermediate signal and the third intermediate signal have pulses, and the pulse widths are both greater than the initial clock period.

In some embodiments, the second conversion circuit includes a second sampling unit, a third logic unit and a fourth logic unit; wherein the second sampling unit is configured to use the third clock signal to sample the chip select signal to generate a fourth intermediate signal, use the inverted signal of the third clock signal to sample the fourth intermediate signal to generate a fifth intermediate signal, and use the fourth clock signal to sample the fifth intermediate signal to generate a sixth intermediate signal; the third logic unit is connected to the second sampling unit and configured to perform an AND operation on the fourth intermediate signal and the third clock signal to output the third control signal; the fourth logic unit is connected to the second sampling unit and configured to perform an AND operation on the sixth intermediate signal and the fourth clock signal to output the fourth control signal; wherein, if the chip select signal meets the preset condition, both the fourth intermediate signal and the sixth intermediate signal have pulses, and the pulse widths are both greater than the initial clock period.

In some embodiments, the first sampling unit includes a first latch, a second latch, a third latch and a first inverter; wherein, the input end of the first latch receives the chip select signal, the clock end of the first latch receives the first clock signal, and the output end of the first latch outputs the first intermediate signal; the input end of the second latch receives the first intermediate signal, the input end of the first inverter receives the first clock signal, the clock end of the second latch is connected to the output end of the first inverter, and the output end of the second latch outputs the second intermediate signal; the input end of the third latch receives the second intermediate signal, the clock end of the third latch receives the second clock signal, and the output end of the third latch outputs the third intermediate signal.

In some embodiments, the second sampling unit includes a fourth latch, a fifth latch, a sixth latch and a second inverter; the input end of the fourth latch receives the chip select signal, the clock end of the fourth latch receives the third clock signal, and the output end of the fourth latch outputs the fourth intermediate signal; the input end of the fifth latch receives the fourth intermediate signal, the input end of the second inverter receives the third clock signal, the clock end of the fifth latch is connected to the output end of the second inverter, and the output end of the fifth latch outputs the fifth intermediate signal; the input end of the sixth latch receives the fifth intermediate signal, the clock end of the sixth latch receives the fourth clock signal, and the output end of the sixth latch outputs the sixth intermediate signal.

In some embodiments, the command decoding circuit also includes a first delay unit and a second delay unit; wherein the first delay unit is connected to the first conversion circuit and the second conversion circuit, and is configured to receive an initial chip select signal from the outside, delay the initial chip select signal, and output the chip select signal; the second delay unit is connected to the command sampling circuit, and is configured to receive an initial command address signal from the outside, delay the initial command address signal, and output the command address signal.

In some embodiments, the target sampling signal includes a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal, and the command address signal, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal all include (N+1)-bit sub-signals, and the command sampling circuit includes (N+1) command sampling units; the i-th command sampling unit is configured to perform two sampling processes on the i-th sub-signal of the command address signal using the first control signal and output the i-th sub-signal of the first sampling signal; and perform two sampling processes on the i-th sub-signal of the command address signal using the second control signal. The i-th sub-signal of the command address signal is sampled once, and the i-th sub-signal of the second sampling signal is output; the i-th sub-signal of the command address signal is sampled twice using the third control signal, and the i-th sub-signal of the third sampling signal is output; the i-th sub-signal of the command address signal is sampled once using the fourth control signal, and the i-th sub-signal of the fourth sampling signal is output; wherein the first sampling signal and the second sampling signal are in a timing aligned state, and the third sampling signal and the fourth sampling signal are in a timing aligned state, i and N are positive integers, and i is less than or equal to (N+1).

In some embodiments, the i-th command sampling unit includes a first trigger, a seventh latch, a second trigger, a third trigger, an eighth latch and a fourth trigger; wherein the input end of the first trigger receives the i-th sub-signal of the command address signal, the clock end of the first trigger receives the first control signal, the input end of the seventh latch is connected to the output end of the seventh latch, the clock end of the seventh latch receives the first control signal, and the output end of the seventh latch outputs the i-th sub-signal of the first sampling signal; the input end of the second trigger receives the i-th sub-signal of the command address signal, and the clock end of the second trigger receives the second control signal , the output end of the second trigger outputs the i-th sub-signal of the second sampling signal; the input end of the third trigger receives the i-th sub-signal of the command address signal, the clock end of the third trigger receives the third control signal, the input end of the eighth latch is connected to the output end of the third trigger, the clock end of the eighth latch receives the third control signal, and the output end of the eighth latch outputs the i-th sub-signal of the third sampling signal; the input end of the fourth trigger receives the i-th sub-signal of the command address signal, the clock end of the fourth trigger receives the fourth control signal, and the output end of the fourth trigger outputs the i-th sub-signal of the fourth sampling signal.

In some embodiments, the command decoding circuit further includes: a decoding circuit connected to the first conversion circuit, the second conversion circuit and the command sampling circuit, configured to decode the first sampling signal, the second sampling signal, the third sampling signal and the command sampling circuit. The fourth sampling signal is decoded and processed to obtain an intermediate decoded signal; and the intermediate decoded signal is sampled and processed based on the first control signal and the third control signal, and a target decoded signal is output; a chip select sampling circuit is connected to the clock generating circuit and is configured to receive the chip select signal; the chip select signal is sampled using the first clock signal and the third clock signal respectively, and a first chip select sampling signal and a second chip select sampling signal are output; wherein the target decoded signal, the first chip select sampling signal and the second chip select sampling signal are logically processed to generate a target command signal.

In some embodiments, the decoding circuit includes: a third delay unit, configured to delay the first control signal and output a first delayed control signal; delay the third control signal and output a second delayed control signal; a first decoding unit, connected to the third delay unit, configured to perform a logic operation on the (N+1)-bit sub-signal of the first sampling signal and the (N+1)-bit sub-signal of the second sampling signal, and output a first decoded signal; sample the first decoded signal using the second delayed control signal and output a first target signal; a second decoding unit, connected to the third delay unit, configured to perform a logic operation on the (N+1)-bit sub-signal of the third sampling signal and the (N+1)-bit sub-signal of the fourth sampling signal and output a second decoded signal; sample the second decoded signal using the first delayed control signal and output a second target signal; wherein the first target signal and the second target signal constitute the target decoded signal, the first target signal indicates the content of the command address signal in the first initial clock cycle; the second target signal indicates the content of the command address signal in the second initial clock cycle.

In a second aspect, an embodiment of the present disclosure provides a semiconductor memory, comprising a command decoding circuit as described in any one of the first aspects.

In some embodiments, the semiconductor memory is a dynamic random access memory DRAM, and the semiconductor memory complies with the LPDDR6 memory specification.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a command decoding circuit provided by an embodiment of the present disclosure;

FIG2A is a first schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

FIG2B is a second signal timing diagram provided by an embodiment of the present disclosure;

FIG3 is a schematic diagram of the composition structure of another command decoding circuit provided by an embodiment of the present disclosure;

FIG4 is a partial structural diagram of a command decoding circuit provided in an embodiment of the present disclosure;

FIG5A is a third signal timing diagram provided by an embodiment of the present disclosure;

FIG5B is a fourth signal timing diagram provided by an embodiment of the present disclosure;

FIG6 is a second partial structural diagram of a command decoding circuit provided in an embodiment of the present disclosure;

FIG7A is a fifth signal timing diagram provided by an embodiment of the present disclosure;

FIG7B is a sixth signal timing diagram provided by an embodiment of the present disclosure;

FIG8 is a third partial structural diagram of a command decoding circuit provided by an embodiment of the present disclosure;

FIG9 is a fourth partial structural diagram of a command decoding circuit provided in an embodiment of the present disclosure;

FIG10 is a fifth partial structural diagram of a command decoding circuit provided in an embodiment of the present disclosure;

FIG11 is a sixth partial structural diagram of a command decoding circuit provided in an embodiment of the present disclosure;

FIG12 is a seventh schematic diagram of a signal timing sequence provided by an embodiment of the present disclosure;

FIG. 13 is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present disclosure.

Detailed ways

The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

It should be pointed out that the terms "first\second" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

The following are explanations of professional terms involved in the embodiments of the present disclosure and the corresponding relationships between some terms:

Dynamic Random Access Memory (DRAM);

Synchronous Dynamic Random Access Memory (SDRAM);

Double Data Rate (DDR);

Low Power DDR (LPDDR);

Sixth generation LPDDR (6th LPDDR, LPDDR6);

Command address input (Command/Address, CMD/ADD or CA for short);

Chip select input (Chip Select Input, CS).

It should be understood that multiple semiconductor memories are integrated into one module (such as a memory stick), and these semiconductor memories share one control bus, and all semiconductor memories can receive CA input and CS input from the control bus. If the CS input received by the semiconductor memory has two pulses, it means that the semiconductor memory is selected, that is, the semiconductor memory needs to perform the operation corresponding to the CA input; if the CS input received by the semiconductor memory remains in a low level state, it means that the semiconductor memory is not selected, that is, the semiconductor memory does not need to perform the operation corresponding to the CA input.

In other words, during the operation of the semiconductor memory, the CA input and the CS input need to be sampled and decoded according to the initial clock signal Clk, so as to obtain the corresponding operation instructions.

According to the provisions of LPDDR6, the command part of the CA input (hereinafter referred to as CA Command) and the CS input both last for 2 initial clock cycles. The CA Command needs to be sampled at the rising edge and falling edge of the first initial clock cycle and the rising edge and falling edge of the second initial clock cycle, and the CS input needs to be sampled at the rising edge of the first initial clock cycle and the rising edge of the second initial clock cycle. Here, the initial clock cycle refers to the clock cycle of the initial clock signal Clk. Specifically, CA Command is a group of signals consisting of 4 sub-signals, and its sub-signals are represented as CA0, CA1, CA2 and CA3 respectively. See Table 1, which shows a partial command truth table of LPDDR6. In Table 1, both CA Command and CS inputs will last for 2 initial clock cycles, R1 refers to the rising edge of the first initial clock cycle, F1 refers to the falling edge of the first initial clock cycle, R2 refers to the rising edge of the second initial clock cycle, and F2 refers to the falling edge of the first 2 initial clock cycles. For CS, CA0~CA3, "H" indicates a high level state, "L" indicates a low level state, and "X" indicates that the level state is not concerned. It should be understood that Table 1 is derived from the industry standard document LPDDR6SPEC. Those skilled in the art can refer to LPDDR6SPEC to understand the meaning of the terms and abbreviations involved therein, and this part of the content does not affect the understanding of the embodiments of the present disclosure, so it will not be described in detail here.

Table 1

As shown in Table 1, the command decoding circuit in the semiconductor memory needs to perform decoding processing based on the R1 sampling result of the CS input, the R2 sampling result of the CS input, the R1 sampling result of the CA Command, the F1 sampling result of the CA Command, the R2 sampling result of the CA Command, and the F2 sampling result of the CA Command, and finally output the specific command of this CA Command.

At present, regardless of whether the semiconductor memory is selected, the command decoding circuit therein will always sample and decode the CA input, and then perform secondary decoding in combination with the CS input to obtain the target command signal, which consumes high power.

The disclosed embodiment provides a command decoding circuit, and only the command decoding circuit in the selected semiconductor memory will sample and decode the CA input, which not only realizes the correct decoding of the command address signal but also reduces power consumption.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to FIG1 , a schematic diagram of the structure of a command decoding circuit 10 provided in an embodiment of the present disclosure is shown. As shown in FIG1 , the command decoding circuit 10 includes:

The clock generating circuit 11 is configured to generate a first clock signal Clk_R0, a second clock signal Clk_F0, a third clock signal Clk_R1 and a fourth clock signal Clk_F1; wherein the clock periods of the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1 are the same and the phases thereof are 90 degrees different from each other;

The first conversion circuit 12 is connected to the clock generation circuit 11, and is configured to receive the chip selection signal CSD, perform multiple sampling and logic processing on the chip selection signal CSD using the first clock signal Clk_R0 and the second clock signal Clk_F0, and output the first control signal Clk_R0d and the second control signal Clk_F0d; wherein, if the chip selection signal CSD meets the preset condition, the first control signal Clk_R0d and the second control signal Clk_F0d both have pulses;

The second conversion circuit 13 is connected to the clock generation circuit 11, and is configured to receive the chip selection signal CSD, and use the third clock signal Clk_R1 and the fourth clock signal Clk_F1 to perform multiple sampling and logic processing on the chip selection signal CSD, and output the third control signal Clk_R1d and the fourth control signal Clk_F1d; wherein, if the chip selection signal CSD meets the preset condition, the third control signal Clk_R1d and the fourth control signal Clk_F1d both have pulses;

The command sampling circuit 14 is connected to the first conversion circuit 12 and the second conversion circuit 13, and is configured to receive the command address signal CA Command, and use the first control signal Clk_R0d, the second control signal Clk_F0d, the third control signal Clk_R1d and the fourth control signal Clk_F1d to sample the command address signal CA Command respectively, and output the target sampling signal.

In some embodiments, when the chip selection signal CSD does not meet a preset condition, the first control signal Clk_R0d, the second control signal Clk_F0d, the third control signal Clk_R1d, and the fourth control signal Clk_F1d all maintain a constant level state.

It should be noted that the command decoding circuit 10 of the embodiment of the present disclosure is applied to a semiconductor memory to realize the decoding requirements for the command address signal CA Command in LPDDR6. In addition, the command decoding circuit 10 can also be applied to a variety of circuit scenarios with similar requirements. The embodiment of the present disclosure will be explained and illustrated with the decoding of the command address signal CA Command later, but this does not constitute a relevant limitation.

It should be understood that if the chip select signal CSD meets the preset conditions, it means that the semiconductor memory to which the command decoding circuit belongs is selected, and the command address signal CA Command is valid for the semiconductor memory. If the chip select signal CSD does not meet the preset conditions, it means that the semiconductor memory to which the command decoding circuit belongs is not selected, and the command address signal CA Command is invalid for the semiconductor memory. Therefore, through the first conversion circuit 12 and the second conversion circuit 13, only when the semiconductor memory is selected, as shown in FIG2A, the first control signal Clk_R0d, the second control signal Clk_F0d, the third control signal Clk_R1d and the fourth control signal Clk_F1d have pulses, thereby realizing normal sampling of the command address signal CA Command; however, when the semiconductor memory is not selected, as shown in FIG2B, the first control signal Clk_R0d, the second control signal Clk_F0d, the third control signal Clk_R1d and the fourth control signal Clk_F1d all maintain a low level state (L) unchanged, and the command address signal will not be sampled, thereby reducing power consumption.

In some embodiments, please refer to FIG. 3 , the clock generating circuit 11 is configured to receive the initial clock signal Clk, perform frequency division and phase division processing on the external initial clock signal Clk, and output the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1. Please refer to FIG. 2A or FIG. 2B , the clock period of the first clock signal Clk_R0 is the period of the initial clock signal The rising edge of the first clock signal Clk_R0 is twice the rising edge of the initial clock signal.

Here, the clock generating circuit 11 may include a frequency division module and a phase division module, and the frequency division module may be implemented by a two-frequency division component composed of a NOT gate and a D-type flip-flop, and the phase division module may be implemented by multiple D-type flip-flops and delay devices.

It should be noted that, as mentioned above, the command address signal CA Command lasts for 2 initial clock cycles (i.e., the clock cycle of the initial clock signal Clk), the rising edge of the first clock signal Clk_R0 is aligned with the rising edge of the first initial clock cycle, the rising edge of the second clock signal Clk_F0 is aligned with the falling edge of the first initial clock cycle, the rising edge of the third clock signal Clk_R1 is aligned with the rising edge of the second initial clock cycle, and the rising edge of the fourth clock signal Clk_F1 is aligned with the falling edge of the second initial clock cycle. In this way, the first clock signal Clk_R0 to the fourth clock signal Clk_F1 can sample the content of the command address signal CA Command at different times.

In some embodiments, please refer to Figures 2A and 2B. When the chip select signal CSD meets the preset conditions, the pulse width of the first control signal Clk_R0d, the pulse width of the second control signal Clk_F0d, the pulse width of the third control signal Clk_R1d and the pulse width of the fourth control signal Clk_F1d are all the same, and the pulse width of the first control signal Clk_R0d is the same as the initial clock cycle; wherein, the pulse leading edge of the first control signal Clk_R0d is aligned with the rising edge of the first clock signal Clk_R0, the pulse leading edge of the second control signal Clk_F0d is aligned with the rising edge of the second clock signal Clk_F0, the pulse leading edge of the third control signal Clk_R1d is aligned with the rising edge of the third clock signal Clk_R1, and the pulse leading edge of the fourth control signal Clk_F1d is aligned with the rising edge of the fourth clock signal Clk_F1.

It should be noted that the pulse leading edge can be a rising edge or a falling edge, and FIG. 2A shows the pulse leading edge as a rising edge. In addition, the command sampling circuit 14 samples the command address signal CA Command using the pulse leading edges of the first control signal Clk_R0d to the fourth control signal Clk_F1d.

In this way, when the semiconductor memory is selected, the sampling result of the command address signal CA Command by the first control signal Clk_R0d indicates the information of the rising edge of the command address signal CA Command in the first initial clock cycle, the sampling result of the command address signal CA Command by the second control signal Clk_F0d indicates the information of the falling edge of the command address signal CA Command in the first initial clock cycle, the sampling result of the command address signal CA Command by the third control signal Clk_R1d indicates the information of the rising edge of the command address signal CA Command in the second initial clock cycle, and the sampling result of the command address signal CA Command by the fourth control signal Clk_F1d indicates the information of the falling edge of the command address signal CA Command in the second initial clock cycle, so as to realize the correct decoding of the command address signal CA Command later.

In a specific embodiment, as shown in FIG. 2A or FIG. 2B , the preset condition means that the chip select signal CSD has a level change edge in the first initial clock cycle, and the chip select signal CSD has a level change edge in the second initial clock cycle.

That is to say, please refer to FIG. 2A , if the chip select signal CSD has two pulse signals, it indicates that the semiconductor memory to which it belongs is selected; please refer to FIG. 2B , if the chip select signal CSD remains in a low level state (L), it indicates that the semiconductor memory to which it belongs is not selected.

From the above, it can be seen that for the command decoding circuit 10 provided in the embodiment of the present disclosure, due to the introduction of the first conversion circuit 12 and the second conversion circuit 13, only the command decoding circuit in the selected semiconductor memory will sample and decode the CA input, which not only realizes the correct decoding of the command address signal but also reduces power consumption.

The circuit configurations of the first conversion circuit 12 and the second conversion circuit 13 are provided below as examples.

In some embodiments, as shown in FIG. 4 , the first conversion circuit 12 includes a first sampling unit 121 , a first logic unit 122 , and a second logic unit 123 ; wherein,

A first sampling unit 121 is configured to sample the chip selection signal CSD using the first clock signal Clk_R0 to generate a first intermediate signal ClkEn_R0, sample the first intermediate signal ClkEn_R0 using an inverted signal of the first clock signal Clk_R0 to generate a second intermediate signal ClkEnD_R0, and sample the second intermediate signal ClkEnD_R0 using the second clock signal Clk_F0 to generate a third intermediate signal ClkEn_F0;

The first logic unit 122 is connected to the first sampling unit 121 and configured to perform an AND operation on the first intermediate signal ClkEn_R0 and the first clock signal Clk_R0 to output a first control signal Clk_R0d;

The second logic unit 123 is connected to the first sampling unit 121 , and is configured to perform an AND operation on the third intermediate signal ClkEn_F0 and the second clock signal Clk_F0 , and output a second control signal Clk_F0d.

It should be noted that, referring to FIG5A , if the chip select signal CSD meets the preset conditions, the first intermediate signal ClkEn_R0 and the third intermediate signal ClkEn_F0 both have pulses, and the pulse widths are both greater than the initial clock cycle, so that the first control signal Clk_R0d and the second control signal Clk_F0d have pulses; referring to FIG5B , if the chip select signal CSD does not meet the preset conditions, the first intermediate signal ClkEn_F0 and the third intermediate signal ClkEn_F0 both maintain a low level state (L) unchanged, so that the first control signal Clk_R0d and the second control signal Clk_F0d do not have pulses. Here, the first logic unit 122 and the second logic unit 123 can both be implemented by a two-input AND gate.

In a specific embodiment, as shown in FIG. 4 , the first sampling unit 121 includes a first latch 1211 , a second latch 1212 , a third latch 1213 and a first inverter 1214 . The input end of the first latch 1211 receives the chip select signal CSD, the clock end of the first latch 1211 receives the first clock signal Clk_R0, and the output end of the first latch 1211 outputs the first intermediate signal ClkEn_R0; the input end of the second latch 1212 receives the first intermediate signal ClkEn_R0, the input end of the first inverter 1214 receives the first clock signal Clk_R0, the clock end of the second latch 1212 is connected to the output end of the first inverter 1214, and the output end of the second latch 1212 outputs the second intermediate signal ClkEnD_R0; the input end of the third latch 1213 receives the second intermediate signal ClkEnD_R0, the clock end of the third latch 1213 receives the second clock signal Clk_F0, and the output end of the third latch 1213 outputs the third intermediate signal ClkEn_F0.

It should be noted that the function of the latch in the embodiment of the present disclosure is: when the clock terminal is at a low level, the signal at the output terminal changes following the signal at the input terminal; when the clock terminal is at a high level, the signal at the output terminal remains unchanged.

Thus, as shown in FIG5A, when the chip select signal meets the preset conditions, the first intermediate signal ClkEn_R0, the second intermediate signal ClkEnD_R0 and the third intermediate signal ClkEn_F0 all have pulses; as shown in FIG5B, when the chip select signal CSD does not meet the preset conditions, the first intermediate signal ClkEn_R0, the second intermediate signal ClkEnD_R0 and the third intermediate signal ClkEn_F0 all have no pulses. In particular, in FIG5A, the input and output waveforms of the third latch 1213 are consistent, but FIG5 shows an ideal situation, and there will be some deviations in the actual circuit, so the existence of the third latch 1213 is conducive to the regularization of the waveform.

It should also be noted that the structures of the second conversion circuit 13 and the first conversion circuit 12 are similar.

In some embodiments, as shown in FIG. 6 , the second conversion circuit 13 includes a second sampling unit 131 , a third logic unit 132 and a fourth logic unit 133 ; wherein,

The second sampling unit 131 is configured to sample the chip selection signal CSD using the third clock signal Clk_R1 to generate a fourth intermediate signal ClkEn_R1, sample the fourth intermediate signal ClkEn_R1 using the inverted signal of the third clock signal Clk_R1 to generate a fifth intermediate signal ClkEnD_R1, and sample the fifth intermediate signal ClkEnD_R1 using the fourth clock signal Clk_F1 to generate a sixth intermediate signal ClkEn_F1;

The third logic unit 132 is connected to the second sampling unit 131 and configured to perform an AND operation on the fourth intermediate signal ClkEn_R1 and the third clock signal Clk_R1 to output a third control signal Clk_R1d;

The fourth logic unit 133 is connected to the second sampling unit 131 , and is configured to perform an AND operation on the sixth intermediate signal ClkEn_F1 and the fourth clock signal Clk_F1 , and output a fourth control signal Clk_F1d.

It should be noted that, as shown in FIG7A , if the chip select signal CSD meets the preset conditions, the fourth intermediate signal ClkEn_R1 and the sixth intermediate signal ClkEn_F1 both have pulses, and the pulse widths are both greater than the initial clock cycle, so that the third control signal Clk_R1d and the fourth control signal Clk_F1d have pulses; as shown in FIG7B , if the chip select signal CSD does not meet the preset conditions, the fourth intermediate signal ClkEn_R1 and the sixth intermediate signal ClkEn_F1 remain in a low level state (L) unchanged, so that the third control signal Clk_R1d and the fourth control signal Clk_F1d do not have pulses. Here, the third logic unit 132 and the fourth logic unit 133 can be implemented by a two-input AND gate.

In some specific embodiments, as shown in FIG. 6 , the second sampling unit 131 includes a fourth latch 1311 , a fifth latch 1312 , a sixth latch 1313 and a second inverter 1314 . The input end of the fourth latch 1311 receives the chip select signal CSD, the clock end of the fourth latch 1311 receives the third clock signal Clk_R1, and the output end of the fourth latch 1311 outputs the fourth intermediate signal ClkEn_R1; the input end of the fifth latch 1312 receives the fourth intermediate signal ClkEn_R1, the input end of the second inverter 1314 receives the third clock signal Clk_R1, the clock end of the fifth latch 1312 is connected to the output end of the second inverter 1314, and the output end of the fifth latch 1312 outputs the fifth intermediate signal ClkEnD_R1; the input end of the sixth latch 1313 receives the fifth intermediate signal ClkEnD_R1, the clock end of the sixth latch 1313 receives the fourth clock signal Clk_F1, and the output end of the sixth latch 1313 outputs the sixth intermediate signal ClkEn_F1.

Thus, as shown in FIG7A , when the chip select signal meets the preset condition, the fourth intermediate signal ClkEn_R1, the fifth intermediate signal ClkEnD_R1 and the sixth intermediate signal ClkEn_F1 all have pulses; as shown in FIG7B , when the chip select signal does not meet the preset condition, the fourth intermediate signal ClkEn_R1, the fifth intermediate signal ClkEnD_R1 and the sixth intermediate signal ClkEn_F1 all have no pulses. Similarly, the existence of the sixth latch 1313 is conducive to the regularity of the waveform.

In some embodiments, as shown in FIG. 3 , the command decoding circuit 10 further includes a first delay unit 15 and a second delay unit 16 ; wherein,

The first delay unit 15 is connected to the first conversion circuit 12 and the second conversion circuit 13, and is configured to receive an initial chip select signal CS from the outside, delay the initial chip select signal CS, and output a chip select signal CSD;

The second delay unit 16 is connected to the command sampling circuit 14, and is configured to receive an initial command address signal from the outside, delay the initial command address signal, and output a command address signal CA Command.

It should be noted that the first delay unit 15 and the second delay unit 16 (or DlyTrim) can be formed by conventional delay devices. Furthermore, the first delay unit 15 and the second delay unit 16 can be designed as a circuit with adjustable delay parameters, or as a circuit with non-adjustable delay parameters, and its function is to delay the initial chip select signal CS (or initial command address signal) to obtain the chip select signal CSD (or command address signal CA Command) to achieve delay matching between signals.

In some embodiments, the target sampling signal includes a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal. The first sampling signal refers to the sampling result of the first control signal Clk_R0d on the command address signal CA Command, the second sampling signal refers to the sampling result of the second control signal Clk_F0d on the command address signal CA Command, the third sampling signal refers to the sampling result of the third control signal Clk_R1d on the command address signal CA Command, and the fourth sampling signal refers to the sampling result of the fourth control signal Clk_F1d on the command address signal CA Command.

Further, the command address signal CA Command, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal all include (N+1)-bit sub-signals. That is, the command address signal CA Command may include sub-signals such as CA0_D, CA1_D...CAN_D; the first sampling signal may include CA0_R0d, CA1_R0d...CAN_R0d, which are hereinafter represented as CA<N:0>_R0d; the second sampling signal may include CA0_F0, CA1_F0...CAN_F0, which are hereinafter represented as CA<N:0>_F0; the third sampling signal may include CA0_R1d, CA1_R1d...CAN_R1d, which are hereinafter represented as CA<N:0>_R1d; the fourth sampling signal may include CA0_F1, CA1_F1...CAN_F1, which are hereinafter represented as CA<N:0>_F1.

Correspondingly, as shown in FIG8 , the command sampling circuit 14 includes (N+1) command sampling units, and FIG8 takes N+1=4 as an example.

The i-th command sampling unit is configured to use the first control signal Clk_R0d to sample the i-th sub-signal of the command address signal CA Command twice, and output the i-th sub-signal of the first sampling signal; use the second control signal Clk_F0d to sample the i-th sub-signal of the command address signal CA Command once, and output the i-th sub-signal of the second sampling signal; use the third control signal Clk_R1d to sample the i-th sub-signal of the command address signal CA Command twice, and output the i-th sub-signal of the third sampling signal; use the fourth control signal Clk_F1d to sample the i-th sub-signal of the command address signal CA Command once, and output the i-th sub-signal of the fourth sampling signal; wherein i and N are positive integers, and i is less than or equal to (N+1).

It should be noted that the pulse leading edge of the first control signal Clk_R0d is ahead of the pulse leading edge of the second control signal Clk_F0d, so the first control signal Clk_R0d is sampled once more than the second control signal Clk_F0d, so that the first sampling signal and the second sampling signal are aligned in timing, which is convenient for subsequent joint decoding. Similarly, the third sampling signal and the fourth sampling signal are aligned in timing.

It should also be noted that the initial command signal also includes (N+1) signals, which are respectively represented as CA0, CA1~CAN. As shown in FIG8, the second delay unit includes (N+1) second delay subunits, and the i-th second delay subunit delays the i-th signal (which can be represented as CAi) of the initial command signal to obtain the i-th signal (which can be represented as CAi_D) of the command signal.

In a specific embodiment, as shown in FIG8 , the i-th command sampling unit includes a first trigger 141, a seventh latch 142, a second trigger 143, a third trigger 144, an eighth latch 145 and a fourth trigger 146. FIG8 only labels the components in the first command sampling unit, and the others can be understood by reference; wherein,

An input terminal of the first flip-flop 141 receives the i-th sub-signal CAi_D of the command address signal, a clock terminal of the first flip-flop 141 receives the first control signal Clk_R0d, an input terminal of the seventh latch 142 is connected to an output terminal of the first flip-flop 141, a clock terminal of the seventh latch 142 receives the first control signal Clk_R0d, and an output terminal of the seventh latch 142 outputs the i-th sub-signal CAi_R0d of the first sampling signal;

The input terminal of the second flip-flop 143 receives the ith sub-signal CAi_D of the command address signal, the clock terminal of the second flip-flop 143 receives the second control signal Clk_F0d, and the output terminal of the second flip-flop 143 outputs the ith sub-signal CAi_F0 of the second sampling signal;

An input terminal of the third flip-flop 144 receives the i-th sub-signal CAi_D of the command address signal, a clock terminal of the third flip-flop 144 receives the third control signal Clk_R1d, an input terminal of the eighth latch 145 is connected to an output terminal of the third flip-flop 144, a clock terminal of the eighth latch 145 receives the third control signal Clk_R1d, and an output terminal of the eighth latch 145 outputs the i-th sub-signal CAi_R1d of the third sampling signal;

An input terminal of the fourth flip-flop 146 receives the i-th sub-signal CAi_D of the command address signal, a clock terminal of the fourth flip-flop 146 receives the fourth control signal Clk_F1d, and an output terminal of the fourth flip-flop 146 outputs the i-th sub-signal CAi_F1 of the fourth sampling signal.

It should be noted that the function of the trigger in the embodiment of the present disclosure is: when the signal at the clock end rises, the signal at the output end samples the signal at the input end.

It should be noted that each command sampling unit has its own first trigger 141 , seventh latch 142 , second trigger 143 , third trigger 144 , eighth latch 145 and fourth trigger 146 . Please refer to FIG. 8 for details.

In some embodiments, as shown in FIG3 , the command decoding circuit 10 further includes:

The decoding circuit 17 is connected to the first conversion circuit 12, the second conversion circuit 13 and the command sampling circuit 14, and is configured to decode the first sampling signal CA<N:0>_R0d, the second sampling signal CA<N:0>_F0, the third sampling signal CA<N:0>_R1d and the fourth sampling signal CA<N:0>_F1 to obtain an intermediate decoding signal; and sample the intermediate decoding signal based on the first control signal Clk_R0d and the third control signal Clk_R1d, and output a target decoding signal Command;

The chip select sampling circuit 18 is connected to the clock generating circuit 11, and is configured to receive the chip select signal CSD, sample the chip select signal CSD using the first clock signal Clk_R0 and the third clock signal Clk_R1, and output the first chip select sampling signal CS_R0 and the second chip select sampling signal CS_R1.

It should be noted that according to the provisions of LPDDR6, the initial chip select signal CS also lasts for 2 initial clock cycles, and the chip select signal CSD needs to be sampled and processed at the rising edge of the first initial clock cycle and the rising edge of the second initial clock cycle. In the subsequent processing, the target decoding signal Command, the first chip select sampling signal CS_R0 and the second chip select sampling signal CS_R1 are logically processed to generate the target command signal. Here, the target command signal can indicate the specific content of this CA Command, such as PDE, SRE, ACT-1, ACT-2... in Table 1

In some embodiments, as shown in Figure 9, the chip select sampling circuit 18 includes a fifth flip-flop 181 and a sixth flip-flop 182, wherein the input end of the fifth flip-flop 181 receives the chip select signal CSD, the clock end of the fifth flip-flop 181 receives the first clock signal Clk_R0, and the output end of the fifth flip-flop 182 outputs the first chip select sampling signal CS_R0; the input end of the sixth flip-flop 182 receives the chip select signal CSD, the clock end of the sixth flip-flop 182 receives the third clock signal Clk_R1, and the output end of the sixth flip-flop 182 outputs the second chip select sampling signal CS_R1.

In some embodiments, as shown in Figure 3 (Figure 3 takes N+1=4 as an example), the decoding circuit 17 is connected to the command sampling circuit 14, and is configured to decode the first sampling signal CA<N:0>_R0d, the second sampling signal CA<N:0>_F0, the third sampling signal CA<N:0>_R1d and the fourth sampling signal CA<N:0>_F1 based on the first control signal Clk_R0d and the third control signal Clk_R1.

Correspondingly, as shown in FIG. 10 and FIG. 11 (both FIG. 10 and FIG. 11 are shown by taking N+1=4 as an example), the decoding circuit 17 includes:

The third delay unit 151 is configured to delay the first control signal Clk_R0d and output a first delayed control signal Clk_R0d1; Delaying the third control signal Clk_R1d and outputting a second delayed control signal Clk_R1d1;

The first decoding unit 152 is connected to the command sampling circuit 14 and the third delay unit 151, and is configured to perform a logic operation on the (N+1)-bit sub-signal of the first sampling signal and the (N+1)-bit sub-signal of the second sampling signal, and output a first decoded signal; and sample the first decoded signal using the second delay control signal Clk_R1d1, and output a first target signal Cmd_R1;

The second decoding unit 153 is connected to the command sampling circuit 14 and the third delay unit 151, and is configured to perform a logic operation on the (N+1)-bit sub-signal of the third sampling signal and the (N+1)-bit sub-signal of the fourth sampling signal to output a second decoded signal; and use the first delay control signal Clk_R0d1 to sample and process the second decoded signal to output a second target signal Cmd_R0.

It should be noted that the function of the third delay unit 151 is to delay the first control signal Clk_R0d and the third control signal Clk_R1d to achieve delay matching between the signals. Specifically, the third delay unit 151 includes two third delay sub-units, which are respectively used to delay the first control signal Clk_R0d and the third control signal Clk_R1d. The first decoding unit 152 and the second decoding unit 153 in FIG. 10 together constitute the decoding processing unit 150 in FIG. 11.

In a specific embodiment, as shown in Figure 11, the first decoding unit 152 includes a fifth logic unit 1521 and a seventh trigger 1522; wherein, the input end of the fifth logic unit 1521 receives a 4-bit sub-signal of the first sampling signal (i.e., CA0_R0d, CA1_R0d, CA2_R0d, CA3_R0d) and a 4-bit sub-signal of the second sampling signal (i.e., CA0_F0, CA1_F0, CA2_F0, CA3_F0), and the output end of the fifth logic unit 1521 outputs a first decoding signal; the input end of the seventh trigger 1522 receives the first decoding signal, the clock end of the seventh trigger 1522 receives the second delay control signal Clk_R1d1, and the output end of the seventh trigger 1522 outputs the first target signal Cmd_R1.

Similarly, as shown in Figure 11, the second decoding unit 153 includes a sixth logic unit 1531 and an eighth flip-flop 1532; the input end of the sixth logic unit 1531 receives the 4-bit sub-signals of the third sampling signal (i.e., CA0_R1d, CA1_R1d, CA2_R1d, CA3_R1d) and the 4-bit sub-signals of the fourth sampling signal (i.e., CA0_F1, CA1_F1, CA2_F1, CA3_F1), and the output end of the sixth logic unit 1531 outputs the second decoding signal; the input end of the eighth flip-flop 1532 receives the second decoding signal, the clock end of the eighth flip-flop 1532 receives the first delay control signal Clk_R0d1, and the output end of the eighth flip-flop 1532 outputs the second target signal Cmd_R0.

It should be noted that the first target signal Cmd_R1 and the second target signal Cmd_R0 constitute the target decoding signal Command. The first target signal Cmd_R1 indicates the content of the command address signal CA Command in the first initial clock cycle; the second target signal Cmd_R0 indicates the content of the command address signal CA Command in the second initial clock cycle. As mentioned above, the initial clock cycle refers to the clock cycle of the initial clock signal Clk.

It should be noted that the fifth logic unit 1521 (or the sixth logic unit 1531) can be implemented by a variety of logic devices, such as NAND gate, NOT gate, XOR gate, etc., which needs to be determined according to specific decoding rules (or called decoding rules), and the embodiments of the present disclosure do not limit this.

The aforementioned first to eighth triggers can all be implemented by D-type triggers, which can use the rising edge of the clock signal (i.e., the signal received at the input end) to sample the input signal (i.e., the signal received at the input end) to obtain an output signal (i.e., the signal at the output end); the aforementioned first to eighth latches can all be implemented by two D-type triggers. When the clock end is at a low level, the output changes with the input signal, and when the clock end is at a high level, the output remains unchanged.

In summary, for the command decoding circuit 10 provided in the embodiment of the present disclosure, FIG12 provides a timing diagram from an overall perspective. As shown in FIG12, the initial clock signal Clk is processed by frequency division and phase division to obtain the first clock signal Clk_R0, the second clock signal Clk_F0, the third clock signal Clk_R1 and the fourth clock signal Clk_F1. The first clock signal Clk_R0 to the fourth clock signal Clk_F1 sample and logically process the chip select signal CSD (that is, the initial chip select signal CS is delayed) to obtain the first control signal Clk_R0 to the fourth control signal Clk_F1 (see FIG2A); the first control signal Clk_R0 to the fourth control signal Clk_F1 respectively sample the command address signal CA<3:0> to obtain the first sampling signal CA<3:0>_R0d, the second sampling signal CA<3:0>_F0, the third sampling signal CA<3:0>_R1d, and the fourth sampling signal CA<3:0>_F1. Then, the first sampling signal CA<3:0>_R0d, the second sampling signal CA<3:0>_F0, the third sampling signal CA<3:0>_R1d and the fourth sampling signal CA<3:0>_F1 are decoded to obtain the first target signal Cmd_R1 and the second target signal Cmd_R0 (not shown in FIG. 12 ); finally, the first target signal Cmd_R1, the second target signal Cmd_R0, the first chip selection sampling signal CS_R0 and the second chip selection sampling signal CS_R1 are decoded together, and the decoding result is sampled by the command sampling clock signal ClkCmd_R1 to obtain the final target decoding signal Command. Here, the target decoding signal Command can indicate the specific content of this CA Command, such as PDE, SRE, ACT-1, ACT-2 in Table 1... In this way, only the command decoding circuit in the selected semiconductor memory will sample and decode the CA input, which not only realizes the correct decoding of the command address signal, but also reduces power consumption.

In another embodiment of the present disclosure, see Fig. 13, which shows a schematic diagram of the composition structure of a semiconductor memory 30 provided by the embodiment of the present disclosure. As shown in Fig. 13, the semiconductor memory 30 may include the command decoding circuit 10 described in any of the above embodiments.

In the embodiment of the present disclosure, the semiconductor memory 30 may be a dynamic random access memory DRAM, and the semiconductor memory complies with the requirements of LPDDR6.

The above are only preferred embodiments of the present disclosure and are not intended to limit the protection scope of the present disclosure.

It should be noted that in the present disclosure, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, The elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the element. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in the several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in the several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in the several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific implementation methods of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims (16)

1. A command decoding circuit, the command decoding circuit (10) comprising:

   A clock generating circuit (11) configured to generate a first clock signal, a second clock signal, a third clock signal and a fourth clock signal; wherein the clock periods of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are the same and the phases thereof differ by 90 degrees respectively;

   A first conversion circuit (12) is connected to the clock generation circuit (11), and is configured to receive a chip selection signal, perform multiple sampling and logic processing on the chip selection signal using the first clock signal and the second clock signal, and output a first control signal and a second control signal; wherein, if the chip selection signal meets a preset condition, both the first control signal and the second control signal have pulses;

   a second conversion circuit (13), connected to the clock generation circuit (11), configured to receive the chip selection signal, perform multiple sampling and logic processing on the chip selection signal using the third clock signal and the fourth clock signal, and output a third control signal and a fourth control signal; wherein, if the chip selection signal meets a preset condition, both the third control signal and the fourth control signal have pulses;

   A command sampling circuit (14) is connected to both the first conversion circuit (12) and the second conversion circuit (13), and is configured to receive a command address signal, sample the command address signal using the first control signal, the second control signal, the third control signal, and the fourth control signal, and output a target sampling signal.
2. The command decoding circuit according to claim 1, wherein:

   When the chip selection signal does not meet the preset condition, the first control signal, the second control signal, the third control signal and the fourth control signal all maintain a constant level state.
3. The command decoding circuit according to claim 1 or 2, wherein:

   The clock generating circuit (11) is configured to receive an initial clock signal, perform frequency division and phase division processing on the external initial clock signal, and output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal;

   The clock period of the first clock signal is twice the clock period of the initial clock signal, and the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal.
4. The command decoding circuit according to any one of claims 1 to 3, wherein the chip select signal is used to indicate whether the command address signal is valid or invalid, and if the chip select signal meets a preset condition, the command address signal is valid, and if the chip select signal does not meet the preset condition, the command address signal is invalid;

   The command address signal lasts for 2 initial clock cycles, and the initial clock cycle refers to the clock cycle of the initial clock signal; the preset condition refers to the existence of a level change edge of the chip select signal in the first initial clock cycle, and the existence of a level change edge of the chip select signal in the second initial clock cycle.
5. The command decoding circuit according to any one of claims 1 to 4, wherein:

   When the chip select signal meets the preset condition, the pulse width of the first control signal, the pulse width of the second control signal, the pulse width of the third control signal and the pulse width of the fourth control signal are all the same, and the pulse width of the first control signal is the same as the initial clock cycle;

   Among them, the pulse leading edge of the first control signal is aligned with the rising edge of the first clock signal, the pulse leading edge of the second control signal is aligned with the rising edge of the second clock signal, the pulse leading edge of the third control signal is aligned with the rising edge of the third clock signal, and the pulse leading edge of the fourth control signal is aligned with the rising edge of the fourth clock signal.
6. The command decoding circuit according to any one of claims 1 to 5, wherein the first conversion circuit (12) comprises a first sampling unit (121), a first logic unit (122) and a second logic unit (123);

   The first sampling unit (121) is configured to sample the chip selection signal using the first clock signal to generate a first intermediate signal, sample the first intermediate signal using an inverted signal of the first clock signal to generate a second intermediate signal, and sample the second intermediate signal using the second clock signal to generate a third intermediate signal;

   The first logic unit (122) is connected to the first sampling unit (121), and is configured to perform an AND operation on the first intermediate signal and the first clock signal, and output the first control signal;

   The second logic unit (123) is connected to the first sampling unit (121), and is configured to perform an AND operation on the third intermediate signal and the second clock signal, and output the second control signal;

   If the chip selection signal meets a preset condition, then both the first intermediate signal and the third intermediate signal have pulses, and the pulse widths are greater than an initial clock cycle.
7. The command decoding circuit according to any one of claims 1 to 6, wherein the second conversion circuit (13) comprises a second sampling unit (131), a third logic unit (132) and a fourth logic unit (133);

   The second sampling unit (131) is configured to sample the chip selection signal using the third clock signal to generate a fourth intermediate signal, sample the fourth intermediate signal using an inverted signal of the third clock signal to generate a fifth intermediate signal, and sample the fifth intermediate signal using the fourth clock signal to generate a sixth intermediate signal;

   The third logic unit (132) is connected to the second sampling unit (131), and is configured to perform an AND operation on the fourth intermediate signal and the third clock signal, and output the third control signal;

   The fourth logic unit (133) is connected to the second sampling unit (131), and is configured to perform an AND operation on the sixth intermediate signal and the fourth clock signal, and output the fourth control signal;

   If the chip selection signal meets a preset condition, then both the fourth intermediate signal and the sixth intermediate signal have pulses, and the pulse widths are greater than an initial clock cycle.
8. The command decoding circuit according to claim 6, wherein the first sampling unit (121) comprises a first latch (1211), a second latch (1212), a third latch (1213) and a first inverter (1214); wherein,

   The input end of the first latch (1211) receives the chip selection signal, the clock end of the first latch (1211) receives the first clock signal, and the output end of the first latch (1211) outputs the first intermediate signal;

   The input end of the second latch (1212) receives the first intermediate signal, the input end of the first inverter (1214) receives the first clock signal, the clock end of the second latch (1212) is connected to the output end of the first inverter (1214), and the output end of the second latch (1212) outputs the second intermediate signal;

   The input terminal of the third latch (1213) receives the second intermediate signal, the clock terminal of the third latch (1213) receives the second clock signal, and the output terminal of the third latch (1213) receives the second intermediate signal. The third intermediate signal is outputted at the terminal.
9. The command decoding circuit according to claim 7, wherein the second sampling unit (131) comprises a fourth latch (1311), a fifth latch (1312), a sixth latch (1313) and a second inverter (1314);

   The input end of the fourth latch (1311) receives the chip selection signal, the clock end of the fourth latch (1311) receives the third clock signal, and the output end of the fourth latch (1311) outputs the fourth intermediate signal;

   The input end of the fifth latch (1312) receives the fourth intermediate signal, the input end of the second inverter (1314) receives the third clock signal, the clock end of the fifth latch (1312) is connected to the output end of the second inverter (1314), and the output end of the fifth latch (1312) outputs the fifth intermediate signal;

   The input end of the sixth latch (1313) receives the fifth intermediate signal, the clock end of the sixth latch (1313) receives the fourth clock signal, and the output end of the sixth latch (1313) outputs the sixth intermediate signal.
10. The command decoding circuit according to any one of claims 1 to 9, wherein the command decoding circuit (10) further comprises a first delay unit (15) and a second delay unit (16); wherein,

    The first delay unit (15) is connected to the first conversion circuit (12) and the second conversion circuit (13), and is configured to receive an initial chip selection signal from the outside, delay the initial chip selection signal, and output the chip selection signal;

    The second delay unit (16) is connected to the command sampling circuit 14, and is configured to receive an initial command address signal from the outside, delay the initial command address signal, and output the command address signal.
11. The command decoding circuit according to any one of claims 1 to 10, wherein the target sampling signal comprises a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal, and the command address signal, the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal all comprise (N+1)-bit sub-signals, and the command sampling circuit (14) comprises (N+1) command sampling units;

    The i-th command sampling unit is configured to perform sampling processing on the i-th sub-signal of the command address signal twice using the first control signal, and output the i-th sub-signal of the first sampling signal; perform sampling processing on the i-th sub-signal of the command address signal once using the second control signal, and output the i-th sub-signal of the second sampling signal; perform sampling processing on the i-th sub-signal of the command address signal twice using the third control signal, and output the i-th sub-signal of the third sampling signal; perform sampling processing on the i-th sub-signal of the command address signal once using the fourth control signal, and output the i-th sub-signal of the fourth sampling signal;

    The first sampling signal and the second sampling signal are aligned in timing, the third sampling signal and the fourth sampling signal are aligned in timing, i and N are positive integers, and i is less than or equal to (N+1).
12. The command decoding circuit according to claim 11, wherein the i-th command sampling unit comprises a first flip-flop (141), a seventh latch (142), a second flip-flop (143), a third flip-flop (144), an eighth latch (145) and a fourth flip-flop (146); wherein,

    The input end of the first flip-flop (141) receives the i-th sub-signal of the command address signal, the clock end of the first flip-flop (141) receives the first control signal, the input end of the seventh latch (142) is connected to the output end of the seventh latch (142), the clock end of the seventh latch (142) receives the first control signal, and the output end of the seventh latch (142) outputs the i-th sub-signal of the first sampling signal;

    The input end of the second flip-flop (143) receives the i-th sub-signal of the command address signal, the clock end of the second flip-flop (143) receives the second control signal, and the output end of the second flip-flop (143) outputs the i-th sub-signal of the second sampling signal;

    The input end of the third flip-flop (144) receives the i-th sub-signal of the command address signal, the clock end of the third flip-flop (144) receives the third control signal, the input end of the eighth latch (145) is connected to the output end of the third flip-flop (144), the clock end of the eighth latch (145) receives the third control signal, and the output end of the eighth latch (145) outputs the i-th sub-signal of the third sampling signal;

    The input end of the fourth flip-flop (146) receives the i-th sub-signal of the command address signal, the clock end of the fourth flip-flop (146) receives the fourth control signal, and the output end of the fourth flip-flop (146) outputs the i-th sub-signal of the fourth sampling signal.
13. The command decoding circuit according to claim 12, wherein the command decoding circuit (10) further comprises:

    a decoding circuit (17), connected to the first conversion circuit (12), the second conversion circuit (13) and the command sampling circuit (14), configured to decode the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal to obtain an intermediate decoding signal; and to sample the intermediate decoding signal based on the first control signal and the third control signal to output a target decoding signal;

    A chip selection sampling circuit (18) is connected to the clock generation circuit (11) and is configured to receive the chip selection signal; use the first clock signal and the third clock signal to sample the chip selection signal respectively, and output a first chip selection sampling signal and a second chip selection sampling signal;

    The target decoding signal, the first chip selection sampling signal and the second chip selection sampling signal are logically processed to generate a target command signal.
14. The command decoding circuit according to claim 13, wherein the decoding circuit comprises:

    A third delay unit (151) is configured to delay the first control signal and output a first delayed control signal; and delay the third control signal and output a second delayed control signal;

    A first decoding unit (152) is connected to the third delay unit (151) and is configured to perform a logic operation on the (N+1)-bit sub-signal of the first sampling signal and the (N+1)-bit sub-signal of the second sampling signal to output a first decoded signal; and perform sampling processing on the first decoded signal using the second delay control signal to output a first target signal;

    a second decoding unit (153), connected to the third delay unit (151), configured to perform a logic operation on the (N+1)-bit sub-signal of the third sampling signal and the (N+1)-bit sub-signal of the fourth sampling signal, and output a second decoded signal; and perform sampling processing on the second decoded signal using the first delay control signal, and output a second target signal;

    The first target signal and the second target signal constitute the target decoded signal. The first target signal indicates the content of the command address signal in the first initial clock cycle; the second target signal indicates the content of the command address signal in the second initial clock cycle.
15. A semiconductor memory comprises a command decoding circuit (10) as claimed in any one of claims 1 to 14.
16. The semiconductor memory according to claim 15, wherein the semiconductor memory is a dynamic random access memory DRAM, and the semiconductor memory complies with LPDDR6 memory specifications.