CN117995239A

CN117995239A - Command decoding circuit and semiconductor memory

Info

Publication number: CN117995239A
Application number: CN202211324749.2A
Authority: CN
Inventors: 高恩鹏
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-27
Filing date: 2022-10-27
Publication date: 2024-05-07
Also published as: WO2024087781A1

Abstract

The embodiment of the disclosure provides a command decoding circuit and a semiconductor memory, comprising: a clock generation circuit configured to generate first to fourth clock signals; a first conversion circuit configured to sample and logically process a chip select signal a plurality of times using a first clock signal and a second clock signal, and output a first control signal and a second control signal; a second conversion circuit configured to sample and logically process the chip select signal a plurality of times using a third clock signal and a fourth clock signal, outputting a third control signal and a fourth control signal; if the chip selection signal meets the preset condition, the first control signal, the second control signal, the third control signal and the fourth control signal are all provided with pulses; and a command sampling circuit configured to sample the command address signal using the first control signal, the second control signal, the third control signal, and the fourth control signal, and output a target sampling signal. The embodiment of the disclosure can reduce the system power consumption.

Description

Command decoding circuit and semiconductor memory

Technical Field

The present disclosure relates to the field of integrated circuit technology, and in particular, to a command decoding circuit and a semiconductor memory.

Background

With the continuous development of semiconductor technology, the design principle and working details of the memory are updated, and various circuits in the memory need to be improved according to new requirements so as to meet the design requirements and achieve better memory performance. For a dynamic random access memory (Dynamic Random Access Memory, DRAM), the command address signal needs to be sampled and decoded by a command decoding circuit to obtain the current operation instruction. At present, the power consumption of the command decoding circuit is high, which affects the further development of the memory performance.

Disclosure of Invention

The present disclosure provides a command decoding circuit and a semiconductor memory capable of achieving correct decoding of command address signals and reducing system power consumption.

In a first aspect, embodiments of the present disclosure provide a command decoding circuit, the command decoding circuit comprising:

a clock generation circuit configured to generate a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal; the first clock signal, the second clock signal, the third clock signal and the fourth clock signal have the same clock period and are different in phase by 90 degrees in sequence;

The first conversion circuit is connected with the clock generation circuit and is configured to receive a chip selection signal, sample and logically process the chip selection signal for a plurality of times by utilizing the first clock signal and the second clock signal, and output a first control signal and a second control signal; if the chip selection signal meets a preset condition, the first control signal and the second control signal are both pulsed;

the second conversion circuit is connected with the clock generation circuit and is configured to receive the chip selection signal, sample and logically process the chip selection signal for a plurality of times by utilizing the third clock signal and the fourth clock signal, and output a third control signal and a fourth control signal; if the chip selection signal meets a preset condition, pulses exist in the third control signal and the fourth control signal;

And the command sampling circuit is connected with the first conversion circuit and the second conversion circuit and is configured to receive a command address signal, sample the command address signal by using the first control signal, the second control signal, the third control signal and the fourth control signal and output a target sampling signal.

In some embodiments, the first control signal, the second control signal, the third control signal, and the fourth control signal all maintain a level state unchanged if the chip select signal does not meet a preset condition.

In some embodiments, the clock generation circuit is configured to receive an initial clock signal, divide and split an external initial clock signal, and output the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal;

wherein the clock period of the first clock signal is 2 times the clock period of the initial clock signal, and the rising edge of the first clock signal is aligned with the rising edge of the initial clock signal.

In some embodiments, the chip select signal is used to indicate that the command address signal is valid or invalid, if the chip select signal meets a preset condition, the command address signal is valid, and if the chip select signal does not meet the preset condition, the command address signal is invalid; the command address signal lasts for 2 initial clock cycles, and the initial clock cycles refer to clock cycles of the initial clock signal; the preset condition is that the chip selection signal has a level change edge in the 1 st initial clock period and the chip selection signal has a level change edge in the 2 nd initial clock period.

In some embodiments, when the chip select signal meets a preset condition, the pulse width of the first control signal, the pulse width of the second control signal, the pulse width of the third control signal and the pulse width of the fourth control signal are all the same, and the pulse width of the first control signal is the same as the initial clock period; wherein the pulse leading edge of the first control signal is aligned with the rising edge of the first clock signal, the pulse leading edge of the second control signal is aligned with the rising edge of the second clock signal, the pulse leading edge of the third control signal is aligned with the rising edge of the third clock signal, and the pulse leading edge of the fourth control signal is aligned with the rising edge of the fourth clock signal.

In some embodiments, the first conversion circuit includes a first sampling unit, a first logic unit, and a second logic unit; wherein the first sampling unit is configured to sample the chip select signal with the first clock signal to generate a first intermediate signal, sample the first intermediate signal with an inverted signal of the first clock signal to generate a second intermediate signal, and sample the second intermediate signal with the second clock signal to generate a third intermediate signal; the first logic unit is connected with the first sampling unit and is configured to perform AND operation on the first intermediate signal and the first clock signal and output the first control signal; the second logic unit is connected with the first sampling unit and is configured to perform AND operation on the third intermediate signal and the second clock signal and output the second control signal; if the chip selection signal meets a preset condition, pulses exist in the first intermediate signal and the third intermediate signal, and the pulse width is larger than the initial clock period.

In some embodiments, the second conversion circuit includes a second sampling unit, a third logic unit, and a fourth logic unit; wherein the second sampling unit is configured to sample the chip select signal with the third clock signal to generate a fourth intermediate signal, sample the fourth intermediate signal with an inverted signal of the third clock signal to generate a fifth intermediate signal, and sample the fifth intermediate signal with the fourth clock signal to generate a sixth intermediate signal; the third logic unit is connected with the second sampling unit and is configured to perform AND operation on the fourth intermediate signal and the third clock signal and output the third control signal; the fourth logic unit is connected with the second sampling unit and is configured to perform an AND operation on the sixth intermediate signal and the fourth clock signal and output the fourth control signal; and if the chip selection signal meets a preset condition, the fourth intermediate signal and the sixth intermediate signal have pulses, and the pulse width is larger than the initial clock period.

In some embodiments, the first sampling unit includes a first latch, a second latch, a third latch, and a first inverter; the input end of the first latch receives the chip selection signal, the clock end of the first latch receives the first clock signal, and the output end of the first latch outputs the first intermediate signal; the input end of the second latch receives the first intermediate signal, the input end of the first inverter receives the first clock signal, the clock end of the second latch is connected with the output end of the first inverter, and the output end of the second latch outputs the second intermediate signal; the input end of the third latch receives the second intermediate signal, the clock end of the third latch receives the second clock signal, and the output end of the third latch outputs the third intermediate signal.

In some embodiments, the second sampling unit includes a fourth latch, a fifth latch, a sixth latch, and a second inverter; the input end of the fourth latch receives the chip selection signal, the clock end of the fourth latch receives the third clock signal, and the output end of the fourth latch outputs the fourth intermediate signal; the input end of the fifth latch receives the fourth intermediate signal, the input end of the second inverter receives the third clock signal, the clock end of the fifth latch is connected with the output end of the second inverter, and the output end of the fifth latch outputs the fifth intermediate signal; the input end of the sixth latch receives the fifth intermediate signal, the clock end of the sixth latch receives the fourth clock signal, and the output end of the sixth latch outputs the sixth intermediate signal.

In some embodiments, the command decoding circuit further comprises a first delay unit and a second delay unit; the first delay unit is connected with the first conversion circuit and the second conversion circuit and is configured to receive an initial chip selection signal from the outside, delay the initial chip selection signal and output the chip selection signal; the second delay unit is connected with the command sampling circuit and is configured to receive an initial command address signal from the outside, delay the initial command address signal and output the command address signal.

In some embodiments, the target sample signal comprises a first sample signal, a second sample signal, a third sample signal, and a fourth sample signal, and the command address signal, the first sample signal, the second sample signal, the third sample signal, and the fourth sample signal each comprise an (n+1) bit sub-signal, the command sample circuit comprising (n+1) command sample cells; an ith command sampling unit configured to perform sampling processing on an ith sub-signal of the command address signal twice by using the first control signal, and output the ith sub-signal of the first sampling signal; performing one-time sampling processing on an ith sub-signal of the command address signal by using the second control signal, outputting an ith sub-signal of the second sampling signal, performing two-time sampling processing on the ith sub-signal of the command address signal by using the third control signal, outputting an ith sub-signal of the third sampling signal, performing one-time sampling processing on the ith sub-signal of the command address signal by using the fourth control signal, and outputting an ith sub-signal of the fourth sampling signal; the first sampling signal and the second sampling signal are in an aligned state in time sequence, the third sampling signal and the fourth sampling signal are in an aligned state in time sequence, i and N are positive integers, and i is less than or equal to (N+1).

In some embodiments, the ith said command sample unit comprises a first flip-flop, a seventh latch, a second flip-flop, a third flip-flop, an eighth latch and a fourth flip-flop; the input end of the first trigger receives the ith sub-signal of the command address signal, the clock end of the first trigger receives the first control signal, the input end of the seventh latch is connected with the output end of the seventh latch, the clock end of the seventh latch receives the first control signal, and the output end of the seventh latch outputs the ith sub-signal of the first sampling signal; the input end of the second trigger receives the ith sub-signal of the command address signal, the clock end of the second trigger receives the second control signal, and the output end of the second trigger outputs the ith sub-signal of the second sampling signal; the input end of the third trigger receives the ith sub-signal of the command address signal, the clock end of the third trigger receives the third control signal, the input end of the eighth latch is connected with the output end of the third trigger, the clock end of the eighth latch receives the third control signal, and the output end of the eighth latch outputs the ith sub-signal of the third sampling signal; the input end of the fourth trigger receives the ith sub-signal of the command address signal, the clock end of the fourth trigger receives the fourth control signal, and the output end of the fourth trigger outputs the ith sub-signal of the fourth sampling signal.

In some embodiments, the command decoding circuit further comprises: the decoding circuit is connected with the first conversion circuit, the second conversion circuit and the command sampling circuit and is configured to decode the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal to obtain intermediate decoding signals; sampling the intermediate decoding signal based on the first control signal and the third control signal, and outputting a target decoding signal; a chip select sampling circuit, coupled to the clock generation circuit, configured to receive the chip select signal; the chip selection signal is sampled by the first clock signal and the third clock signal respectively, and a first chip selection sampling signal and a second chip selection sampling signal are output; and the target decoding signal, the first chip selection sampling signal and the second chip selection sampling signal are logically processed to generate a target command signal.

In some embodiments, the decoding circuit comprises: a third delay unit configured to delay the first control signal and output a first delayed control signal; performing delay processing on the third control signal and outputting a second delay control signal; a first decoding unit connected to the third delay unit and configured to perform a logic operation on the (n+1) -bit sub-signal of the first sampling signal and the (n+1) -bit sub-signal of the second sampling signal, and output a first decoding signal; sampling the first decoding signal by using the second delay control signal, and outputting a first target signal; a second decoding unit connected to the third delay unit and configured to perform a logic operation on the (n+1) bit sub-signal of the third sampling signal and the (n+1) bit sub-signal of the fourth sampling signal, and output a second decoding signal; sampling the second decoding signal by using the first delay control signal, and outputting a second target signal; wherein the first target signal and the second target signal constitute the target decoded signal, the first target signal indicating the content of the command address signal at 1 st initial clock cycle; the second target signal indicates the content of the command address signal at the 2 nd initial clock cycle.

In a second aspect, embodiments of the present disclosure provide a semiconductor memory including the command decoding circuit as set forth in any one of the first aspects.

In some embodiments, the semiconductor memory is a dynamic random access memory, DRAM, and the semiconductor memory meets LPDDR6 memory specifications.

The embodiment of the disclosure provides a command decoding circuit and a semiconductor memory, wherein the command decoding circuit can sample and decode a command address signal only when the semiconductor memory is selected (namely, a chip selection signal meets a preset condition), so that the command address signal can be correctly decoded, and the power consumption can be reduced.

Drawings

Fig. 1 is a schematic diagram of a composition structure of a command decoding circuit according to an embodiment of the disclosure;

FIG. 2A is a schematic diagram illustrating a signal timing diagram according to an embodiment of the disclosure;

FIG. 2B is a second signal timing diagram according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a command decoding circuit according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram showing a partial structure of a command decoding circuit according to an embodiment of the disclosure;

FIG. 5A is a third signal timing diagram according to an embodiment of the disclosure;

FIG. 5B is a schematic diagram of a signal timing diagram according to an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a partial structure of a command decoding circuit according to an embodiment of the disclosure;

FIG. 7A is a fifth signal timing diagram according to an embodiment of the present disclosure;

FIG. 7B is a schematic diagram of a signal timing diagram according to an embodiment of the disclosure;

Fig. 8 is a schematic diagram of a partial structure of a command decoding circuit according to an embodiment of the disclosure;

fig. 9 is a schematic diagram showing a partial structure of a command decoding circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic diagram showing a partial structure of a command decoding circuit according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram showing a partial structure of a command decoding circuit according to an embodiment of the disclosure;

FIG. 12 is a schematic diagram of a signal timing diagram according to an embodiment of the disclosure;

Fig. 13 is a schematic structural diagram of a semiconductor memory according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first/second" in relation to embodiments of the present disclosure is used merely to distinguish similar objects and does not represent a particular ordering of the objects, it being understood that the "first/second" may be interchanged with a particular order or precedence where allowed, so that embodiments of the present disclosure described herein may be implemented in an order other than that illustrated or described herein.

The following is a description of terms and relationships related to embodiments of the present disclosure:

A dynamic random access memory (Dynamic Random Access Memory, DRAM);

A synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM);

double Data Rate (DDR);

Low Power DDR (LPDDR);

Sixth generation LPDDR (6 th LPDDR, LPDDR 6);

Command Address input (CMD/ADD or CA for short);

chip select Input (CHIP SELECT Input, CS).

It will be appreciated that a plurality of semiconductor memories may be integrated into a single module (e.g., memory bank), which may share a control bus, and that all semiconductor memories may be capable of receiving both the CA and CS inputs from the control bus. If the CS input received by the semiconductor memory has two pulses, the semiconductor memory is selected, namely the semiconductor memory needs to execute the operation corresponding to the CA input; if the CS input received by the semiconductor memory remains unchanged in the low level state, the semiconductor memory is not selected, i.e. the semiconductor memory does not need to execute the operation corresponding to the CA input.

In other words, during the operation of the semiconductor memory, the CA input and the CS input need to be sampled and decoded according to the initial clock signal Clk, so as to obtain the corresponding operation command.

According to the regulation of LPDDR6, the Command portion (hereinafter referred to as CA Command) in the CA input and the CS input each last 2 initial clock cycles, and the CA Command is sampled at the rising edge and the falling edge of the 1 st initial clock cycle and at the rising edge and the falling edge of the 2 nd initial clock cycle, and the CS input is sampled at the rising edge of the 1 st initial clock cycle and at the rising edge of the 2 nd initial clock cycle. Here, the initial clock period refers to a clock period of the initial clock signal Clk. Specifically, CA Command is a set of 4 subsignals, denoted CA0, CA1, CA2, and CA3, respectively. See table 1, which shows a partial command truth table for LPDDR 6. In Table 1, both the CA Command and CS inputs last for 2 initial clock cycles, R1 is the rising edge of the 1 st initial clock cycle, F1 is the falling edge of the 1 st initial clock cycle, R2 is the rising edge of the 2 nd initial clock cycle, F2 is the falling edge of the 1 st 2 nd initial clock cycle, and for CS, CA 0-CA 3, "H" represents a high state, "L" represents a low state, and "X" represents no concern about the level state. It is to be understood that table 1 is from industry standard document LPDDR6 SPEC, and those skilled in the art will recognize the meaning of each term and abbreviation referred to therein with reference to LPDDR6 SPEC, and that this section does not affect the understanding of the embodiments of the present disclosure, so that detailed description thereof will not be provided herein.

TABLE 1

As shown in table 1, the Command decoding circuit in the semiconductor memory needs to perform decoding processing based on the R1 sampling result of the CS input, the R2 sampling result of the CS input, the R1 sampling result of the CA Command, the F1 sampling result of the CA Command, the R2 sampling result of the CA Command, and the F2 sampling result of the CA Command, and finally outputs the specific Command of the present CA Command.

At present, no matter whether the semiconductor memory is selected or not, the command decoding circuit in the semiconductor memory can always sample and decode the CA input, and then the CA input is combined with the CS input for secondary decoding to obtain a target command signal, so that the power consumption is high.

The embodiment of the disclosure provides a command decoding circuit, only the command decoding circuit in the selected semiconductor memory can sample and decode CA input, so that not only can correct decoding of command address signals be realized, but also power consumption can be reduced.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to fig. 1, a schematic diagram of the composition of a command decoding circuit 10 provided by an embodiment of the present disclosure is shown. As shown in fig. 1, the command decoding circuit 10 includes:

A clock generating circuit 11 configured to generate a first clock signal clk_r0, a second clock signal clk_f0, a third clock signal clk_r1, and a fourth clock signal clk_f1; wherein, the clock periods of the first clock signal clk_r0, the second clock signal clk_f0, the third clock signal clk_r1 and the fourth clock signal clk_f1 are the same and the phases are different by 90 degrees in sequence;

a first conversion circuit 12 connected to the clock generation circuit 11 and configured to receive the chip select signal CSD, perform sampling and logic processing on the chip select signal CSD multiple times by using the first clock signal clk_r0 and the second clock signal clk_f0, and output a first control signal clk_r0d and a second control signal clk_f0d; if the chip select signal CSD meets a preset condition, pulses exist in the first control signal clk_r0d and the second control signal clk_f0d;

A second conversion circuit 13 connected to the clock generation circuit 11 and configured to receive the chip select signal CSD, and perform multiple sampling and logic processing on the chip select signal CSD by using the third clock signal clk_r1 and the fourth clock signal clk_f1, and output a third control signal clk_r1d and a fourth control signal clk_f1d; if the chip select signal CSD meets a preset condition, pulses exist in the third control signal clk_r1d and the fourth control signal clk_f1d;

The Command sampling circuit 14 is connected to the first converting circuit 12 and the second converting circuit 13, and is configured to receive the Command address signal CA Command, sample the Command address signal CA Command by using the first control signal clk_r0d, the second control signal clk_f0d, the third control signal clk_r1d, and the fourth control signal clk_f1d, and output a target sampling signal.

In some embodiments, in the case that the chip select signal CSD does not meet the preset condition, the first control signal clk_r0d, the second control signal clk_f0d, the third control signal clk_r1d and the fourth control signal clk_f1d all maintain the level state unchanged.

It should be noted that the Command decoding circuit 10 of the embodiment of the present disclosure is applied to a semiconductor memory to realize the decoding requirement for the Command address signal CA Command in the LPDDR 6. In addition, the Command decoding circuit 10 may also be applied in various circuit scenarios with similar requirements, and the embodiments of the present disclosure will be explained and illustrated later with decoding of the Command address signal CA Command, but this is not meant to be limiting.

It should be understood that if the chip select signal CSD meets the preset condition, it indicates that the semiconductor memory to which the Command decoding circuit belongs is selected, and the current Command address signal CA Command is valid for the semiconductor memory. If the chip select signal CSD does not meet the preset condition, it indicates that the semiconductor memory to which the Command decoding circuit belongs is not selected, and the current Command address signal CA Command is invalid for the semiconductor memory. Therefore, through the first and second conversion circuits 12 and 13, only in the case where the semiconductor memory is selected, as shown in fig. 2A, the first, second, third and fourth control signals clk_r0d, clk_f0d, clk_r1d exist in pulses, thereby achieving normal sampling of the Command address signal CA Command; however, in the case where the semiconductor memory is not selected, as shown in fig. 2B, the first control signal clk_r0d, the second control signal clk_f0d, the third control signal clk_r1d, and the fourth control signal clk_f1d all maintain the low state (L) and do not sample the command address signal, thereby reducing power consumption.

In some embodiments, referring to fig. 3, the clock generating circuit 11 is configured to receive the initial clock signal Clk, divide and split the external initial clock signal Clk, and output the first clock signal clk_r0, the second clock signal clk_f0, the third clock signal clk_r1 and the fourth clock signal clk_f1. Referring to fig. 2A or 2B, the clock period of the first clock signal clk_r0 is 2 times that of the initial clock signal, and the rising edge of the first clock signal clk_r0 is aligned with the rising edge of the initial clock signal.

Here, the clock generating circuit 11 may include a frequency dividing module and a phase splitting module, and the frequency dividing module may be implemented by a frequency dividing component composed of a not gate and a D-type flip-flop, and the phase splitting module may be implemented by a plurality of D-type flip-flops and a delay device.

It should be noted that, as described above, the Command address signal CA Command lasts for 2 initial clock periods (i.e., the clock periods of the initial clock signal Clk), the rising edge of the first clock signal clk_r0 is aligned with the rising edge of the 1 st initial clock period, the rising edge of the second clock signal clk_f0 is aligned with the falling edge of the 1 st initial clock period, the rising edge of the third clock signal clk_r1 is aligned with the rising edge of the 2 nd initial clock period, and the rising edge of the fourth clock signal clk_f1 is aligned with the falling edge of the 2 nd initial clock period. Thus, the first clock signal clk_r0 to the fourth clock signal clk_f1 can sample the contents of the Command address signal CA Command at different times.

In some embodiments, referring to fig. 2A and 2B, in the case that the chip select signal CSD meets the preset condition, the pulse width of the first control signal clk_r0d, the pulse width of the second control signal clk_f0d, the pulse width of the third control signal clk_r1d, and the pulse width of the fourth control signal clk_f1d are the same, and the pulse width of the first control signal clk_r0d is the same as the initial clock period; wherein, the pulse leading edge of the first control signal clk_r0d is aligned with the rising edge of the first clock signal clk_r0, the pulse leading edge of the second control signal clk_f0d is aligned with the rising edge of the second clock signal clk_f0, the pulse leading edge of the third control signal clk_r1d is aligned with the rising edge of the third clock signal clk_r1, and the pulse leading edge of the fourth control signal clk_f1d is aligned with the rising edge of the fourth clock signal clk_f1.

The pulse front may be a rising edge or a falling edge, and fig. 2A illustrates that the pulse front is a rising edge as an example. The Command sampling circuit 14 samples the Command address signal CA Command by using the pulse fronts of the first to fourth control signals clk_r0d to clk_f1d.

Thus, in the case that the semiconductor memory is selected, the sampling result of the first control signal clk_r0d on the Command address signal CA Command indicates the information of the rising edge of the Command address signal CA Command at the 1 st initial clock cycle, the sampling result of the second control signal clk_f0d on the Command address signal CA Command indicates the information of the falling edge of the Command address signal CA Command at the 1 st initial clock cycle, the sampling result of the third control signal clk_r1d on the Command address signal CA Command indicates the information of the rising edge of the Command address signal CA Command at the 2 nd initial clock cycle, and the sampling result of the fourth control signal clk_f1d on the Command address signal CA Command indicates the information of the falling edge of the Command address signal CA Command at the 2 nd initial clock cycle, so that the correct decoding of the Command address signal CA Command is realized later.

In a specific embodiment, as shown in fig. 2A or fig. 2B, the preset condition means that the chip select signal CSD has a level change edge in the 1 st initial clock period, and the chip select signal CSD has a level change edge in the 2 nd initial clock period.

That is, referring to fig. 2A, if the chip select signal CSD has 2 pulse signals, it is indicated that the semiconductor memory to which it belongs is selected; referring to fig. 2B, if the chip select signal CSD remains in the low state (L), it is indicated that the semiconductor memory to which it belongs is not selected.

As can be seen from the above, with the command decoding circuit 10 provided in the embodiment of the present disclosure, since the first conversion circuit 12 and the second conversion circuit 13 are introduced, only the command decoding circuit in the selected semiconductor memory will sample and decode the CA input, so that not only the correct decoding of the command address signal is realized, but also the power consumption can be reduced.

The circuit configuration of the first conversion circuit 12, the second conversion circuit 13 is exemplarily provided below.

In some embodiments, as shown in fig. 4, the first conversion circuit 12 includes a first sampling unit 121, a first logic unit 122, and a second logic unit 123; wherein,

A first sampling unit 121 configured to sample the chip select signal CSD with the first clock signal clk_r0 to generate a first intermediate signal ClkEn _r0, sample the first intermediate signal ClkEn _r0 with an inverted signal of the first clock signal clk_r0 to generate a second intermediate signal ClkEnD _r0, and sample the second intermediate signal ClkEnD _r0 with the second clock signal clk_f0 to generate a third intermediate signal ClkEn _f0;

A first logic unit 122 connected to the first sampling unit 121 and configured to perform an and operation on the first intermediate signal ClkEn _r0 and the first clock signal clk_r0, and output a first control signal clk_r0d;

the second logic unit 123 is connected to the first sampling unit 121, and is configured to perform an and operation on the third intermediate signal ClkEn _f0 and the second clock signal clk_f0, and output a second control signal clk_f0d.

It should be noted that, referring to fig. 5A, if the chip select signal CSD meets the preset condition, the first intermediate signal ClkEn _r0 and the third intermediate signal ClkEn _f0 have pulses, and the pulse widths are larger than the initial clock period, so that the first control signal clk_r0d and the second control signal clk_f0d have pulses; referring to fig. 5B, if the chip select signal CSD does not meet the preset condition, the first intermediate signal ClkEn _f0 and the third intermediate signal ClkEn _f0 both keep the low-level state (L) unchanged, so that the first control signal clk_r0d and the second control signal clk_f0d have no pulse. Here, the first logic unit 122 and the second logic unit 123 may each be implemented by a two-input and gate.

In a specific embodiment, as shown in fig. 4, the first sampling unit 121 includes a first latch 1211, a second latch 1212, a third latch 1213, and a first inverter 1214. An input terminal of the first latch 1211 receives the chip select signal CSD, a clock terminal of the first latch 1211 receives the first clock signal clk_r0, and an output terminal of the first latch 1211 outputs the first intermediate signal ClkEn _r0; an input terminal of the second latch 1212 receives the first intermediate signal ClkEn _r0, an input terminal of the first inverter 1214 receives the first clock signal clk_r0, a clock terminal of the second latch 1212 is connected to an output terminal of the first inverter 1214, and an output terminal of the second latch 1212 outputs the second intermediate signal ClkEnD _r0; the input terminal of the third latch 1213 receives the second intermediate signal ClkEnD _r0, the clock terminal of the third latch 1213 receives the second clock signal clk_f0, and the output terminal of the third latch 1213 outputs the third intermediate signal ClkEn _f0.

It should be noted that the latch in the embodiments of the present disclosure has the following functions: when the clock end is at a low level, the signal of the output end changes along with the signal of the input end; when the clock terminal is at high level, the signal at the output terminal remains unchanged.

Thus, as shown in fig. 5A, in the case where the chip select signal meets the preset condition, pulses are present in each of the first intermediate signal ClkEn _r0, the second intermediate signal ClkEnD _r0, and the third intermediate signal ClkEn _f0; as shown in fig. 5B, in the case where the chip select signal CSD does not meet the preset condition, no pulse exists in the first intermediate signal ClkEn _r0, the second intermediate signal ClkEnD _r0, and the third intermediate signal ClkEn _f0. In particular, in fig. 5A, the input and output waveforms of the third latch 1213 are identical, but fig. 5 shows an ideal case, with some deviation in the actual circuit, so the presence of the third latch 1213 is advantageous for waveform regularity.

It should be noted that the structures of the second conversion circuit 13 and the first conversion circuit 12 are similar.

In some embodiments, as shown in fig. 6, the second conversion circuit 13 includes a second sampling unit 131, a third logic unit 132, and a fourth logic unit 133; wherein,

A second sampling unit 131 configured to sample the chip select signal CSD with the third clock signal clk_r1 to generate a fourth intermediate signal ClkEn _r1, sample the fourth intermediate signal ClkEn _r1 with the inverted signal of the third clock signal clk_r1 to generate a fifth intermediate signal ClkEnD _r1, and sample the fifth intermediate signal ClkEnD _r1 with the fourth clock signal clk_f1 to generate a sixth intermediate signal ClkEn _f1;

A third logic unit 132 connected to the second sampling unit 131 and configured to perform an and operation on the fourth intermediate signal ClkEn _r1 and the third clock signal clk_r1, and output a third control signal clk_r1d;

The fourth logic unit 133 is connected to the second sampling unit 131, and is configured to perform an and operation on the sixth intermediate signal ClkEn _f1 and the fourth clock signal clk_f1, and output a fourth control signal clk_f1d.

It should be noted that, as shown in fig. 7A, if the chip select signal CSD meets the preset condition, the fourth intermediate signal ClkEn _r1 and the sixth intermediate signal ClkEn _f1 have pulses, and the pulse widths are larger than the initial clock period, so that the third control signal clk_r1d and the fourth control signal clk_f1d have pulses; as shown in fig. 7B, if the chip select signal CSD does not meet the preset condition, the fourth intermediate signal ClkEn _r1 and the sixth intermediate signal ClkEn _f1 maintain the low-level state (L) unchanged, so that the third control signal clk_r1d and the fourth control signal clk_f1d have no pulse. Here, the third logic unit 132 and the fourth logic unit 133 may each be implemented by a two-input and gate.

In some specific embodiments, as shown in fig. 6, the second sampling unit 131 includes a fourth latch 1311, a fifth latch 1312, a sixth latch 1313, and a second inverter 1314. An input terminal of the fourth latch 1311 receives the chip select signal CSD, a clock terminal of the fourth latch 1311 receives the third clock signal clk_r1, and an output terminal of the fourth latch 1311 outputs the fourth intermediate signal ClkEn _r1; an input terminal of the fifth latch 1312 receives the fourth intermediate signal ClkEn _r1, an input terminal of the second inverter 1314 receives the third clock signal clk_r1, a clock terminal of the fifth latch 1312 is connected to an output terminal of the second inverter 1314, and an output terminal of the fifth latch 1312 outputs the fifth intermediate signal ClkEnD _r1; an input of the sixth latch 1313 receives the fifth intermediate signal ClkEnD _r1, a clock of the sixth latch 1313 receives the fourth clock clk_f1, and an output of the sixth latch 1313 outputs the sixth intermediate signal ClkEn _f1.

Thus, as shown in fig. 7A, in the case where the chip select signal meets the preset condition, pulses are present in each of the fourth intermediate signal ClkEn _r1, the fifth intermediate signal ClkEnD _r1, and the sixth intermediate signal ClkEn _f1; as shown in fig. 7B, in the case where the chip select signal does not meet the preset condition, no pulse exists in any of the fourth intermediate signal ClkEn _r1, the fifth intermediate signal ClkEnD _r1, and the sixth intermediate signal ClkEn _f1. Similarly, the presence of sixth latch 1313 facilitates waveform regularity.

In some embodiments, as shown in fig. 3, the command decoding circuit 10 further includes a first delay unit 15 and a second delay unit 16; wherein,

A first delay unit 15 connected to the first conversion circuit 12 and the second conversion circuit 13, configured to receive the initial chip selection signal CS from the outside, perform delay processing on the initial chip selection signal CS, and output a chip selection signal CSD;

the second delay unit 16 is connected to the Command sampling circuit 14, and is configured to receive an initial Command address signal from the outside, delay the initial Command address signal, and output a Command address signal CA Command.

It should be noted that the first delay unit 15 and the second delay unit 16 (or referred to as DlyTrim) may be configured using conventional delay devices. Further, the first delay unit 15 and the second delay unit 16 may be designed as a circuit with adjustable delay parameters, or may be designed as a circuit with non-adjustable delay parameters, which is used to delay the initial chip select signal CS (or the initial Command address signal) to obtain the chip select signal CSD (or the Command address signal CA Command), so as to implement delay matching between signals.

In some embodiments, the target sampling signal includes a first sampling signal, a second sampling signal, a third sampling signal and a fourth sampling signal, the first sampling signal is a sampling result of the first control signal clk_r0d on the Command address signal CA Command, the second sampling signal is a sampling result of the second control signal clk_f0d on the Command address signal CA Command, the third sampling signal is a sampling result of the third control signal clk_r1d on the Command address signal CA Command, and the fourth sampling signal is a sampling result of the fourth control signal clk_f1d on the Command address signal CA Command.

Further, the Command address signal CA Command, the first sampling signal, the second sampling signal, the third sampling signal, and the fourth sampling signal each include an (n+1) -bit sub-signal. That is, the Command address signal CA Command may include the sub-signals CA0_ D, CA1_D … … CAN_D; the first sampled signal may include CA0_R0d, CA1_R0d … … CAN_R0d, denoted CA < N0 > _R0d; the second sampled signal may include CA0_F0, CA1_F0 … … CAN_F0, denoted CA < N0 > _F0; the third sampled signal may include CA0_R1d, CA1_R1d … … CAN_R1d, denoted CA < N0 > _R1d; the fourth sampled signal may include CA0_F1, CA1_F1 … … CAN_F1, denoted CA < N0 > _F1 later.

Accordingly, as shown in fig. 8, the command sampling circuit 14 includes (n+1) command sampling units, and fig. 8 is shown by taking n+1=4 as an example.

An ith Command sampling unit configured to perform sampling processing on an ith bit sub-signal of the Command address signal CA Command twice by using the first control signal clk_r0d, and output the ith bit sub-signal of the first sampling signal; the ith sub-signal of the Command address signal CA Command is sampled once by using a second control signal Clk_F0d, and the ith sub-signal of the second sampling signal is output; the ith sub-signal of the Command address signal CA Command is sampled twice by utilizing a third control signal Clk_R1d, the ith sub-signal of the third sampling signal is output, and the ith sub-signal of the Command address signal CA Command is sampled once by utilizing a fourth control signal Clk_F1d, and the ith sub-signal of the fourth sampling signal is output; wherein i and N are positive integers, and i is less than or equal to (N+1).

It should be noted that, the pulse leading edge of the first control signal clk_r0d leads the pulse leading edge of the second control signal clk_f0d, so that the first control signal clk_r0d is sampled more than the second control signal clk_f0d, so that the first sampling signal and the second sampling signal are aligned in time sequence, and the subsequent common decoding is facilitated. Likewise, the third sampling signal and the fourth sampling signal are in a time-aligned state.

The initial command signal also includes (n+1) signals, which are denoted as CA0 and CA1 to CAN, respectively. As shown in fig. 8, the second delay unit includes (n+1) second delay subunits, and the ith second delay subunit delays the ith bit signal (may be denoted as CAi) of the initial command signal to obtain the ith bit signal (may be denoted as cai_d) of the command signal.

In a specific embodiment, as shown in fig. 8, the ith command sampling unit includes a first flip-flop 141, a seventh latch 142, a second flip-flop 143, a third flip-flop 144, an eighth latch 145, and a fourth flip-flop 146, and only the components in the 1 st command sampling unit are numbered in fig. 8, and other references can be understood; wherein,

The input end of the first flip-flop 141 receives the i-th bit sub-signal cai_d of the command address signal, the clock end of the first flip-flop 141 receives the first control signal clk_r0d, the input end of the seventh latch 142 is connected with the output end of the first flip-flop 141, the clock end of the seventh latch 142 receives the first control signal clk_r0d, and the output end of the seventh latch 142 outputs the i-th bit sub-signal cai_r0d of the first sampling signal;

The input end of the second flip-flop 143 receives the i-th bit sub-signal cai_d of the command address signal, the clock end of the second flip-flop 143 receives the second control signal clk_f0d, and the output end of the second flip-flop 143 outputs the i-th bit sub-signal cai_f0 of the second sampling signal;

The input end of the third flip-flop 144 receives the i-th bit sub-signal cai_d of the command address signal, the clock end of the third flip-flop 144 receives the third control signal clk_r1d, the input end of the eighth latch 145 is connected with the output end of the third flip-flop 144, the clock end of the eighth latch 145 receives the third control signal clk_r1d, and the output end of the eighth latch 145 outputs the i-th bit sub-signal cai_r1d of the third sampling signal;

The input terminal of the fourth flip-flop 146 receives the i-th bit sub-signal cai_d of the command address signal, the clock terminal of the fourth flip-flop 146 receives the fourth control signal clk_f1d, and the output terminal of the fourth flip-flop 146 outputs the i-th bit sub-signal cai_f1 of the fourth sampling signal.

It should be noted that the functions of the flip-flop in the embodiment of the present disclosure are: the signal at the output terminal samples the signal at the input terminal at the rising edge of the signal at the clock terminal.

It should be noted that each command sampling unit has a respective first flip-flop 141, seventh flip-flop 142, second flip-flop 143, third flip-flop 144, eighth flip-flop 145 and fourth flip-flop 146, which is specifically understood with reference to fig. 8.

In some embodiments, as shown in fig. 3, the command decoding circuit 10 further includes:

decoding circuit 17, first conversion circuit 12, second conversion circuit 13, and command sampling circuit 14 are connected and configured to decode first sampling signal CA < N0 > _R0d, second sampling signal CA < N0 > _F0, third sampling signal CA < N0 > _R1d, and fourth sampling signal CA < N0 > _F1 to obtain intermediate decoded signal; sampling the intermediate decoding signal based on the first control signal Clk_R0d and the third control signal Clk_R1d, and outputting a target decoding signal Command;

the chip-selection sampling circuit 18 is connected to the clock generation circuit 11, and is configured to receive the chip-selection signal CSD, sample the chip-selection signal CSD with the first clock signal clk_r0 and the third clock signal clk_r1, and output the first chip-selection sampling signal cs_r0 and the second chip-selection sampling signal cs_r1.

The initial chip select signal CS also lasts for 2 initial clock cycles according to the LPDDR6 rule, and the chip select signal CSD needs to be sampled at the rising edge of the 1 st initial clock cycle and the rising edge of the 2 nd initial clock cycle. In the subsequent processing, the target decoding signal Command, the first chip select sampling signal cs_r0 and the second chip select sampling signal cs_r1 are logically processed to generate the target Command signal. Here, the target Command signal can indicate the specific contents of the current CA Command, e.g., PDE, SRE, ACT-1, ACT-2 … … in Table 1

In some embodiments, as shown in fig. 9, the chip-select sampling circuit 18 includes a fifth flip-flop 181 and a sixth flip-flop 182, wherein an input terminal of the fifth flip-flop 181 receives the chip-select signal CSD, a clock terminal of the fifth flip-flop 181 receives the first clock signal clk_r0, and an output terminal of the fifth flip-flop 182 outputs the first chip-select sampling signal cs_r0; the input terminal of the sixth flip-flop 182 receives the chip select signal CSD, the clock terminal of the sixth flip-flop 182 receives the third clock signal clk_r1, and the output terminal of the sixth flip-flop 182 outputs the second chip select sampling signal cs_r1.

In some embodiments, as shown in fig. 3 (fig. 3 illustrates n+1=4, for example), decoding circuit 17 is coupled to command sampling circuit 14 and is configured to decode first, second, third, and fourth sampling signals CA < N:0> _r0d, CA < N:0> _f0, CA < N:0> _r1d, CA < N:0> _f1 based on first and third control signals clk_r0d, clk_r1d.

Accordingly, as shown in fig. 10 and 11 (fig. 10 and 11 are each shown by way of example with n+1=4), the decoding circuit 17 includes:

A third delay unit 151 configured to delay the first control signal clk_r0d and output a first delayed control signal clk_r0d1; performing delay processing on the third control signal Clk_R1d, and outputting a second delay control signal Clk_R1d1;

A first decoding unit 152 connected to the command sampling circuit 14 and the third delay unit 151, configured to perform a logic operation on the (n+1) bit sub-signal of the first sampling signal and the (n+1) bit sub-signal of the second sampling signal, and output a first decoded signal; sampling the first decoding signal by using a second delay control signal Clk_R1d1 to output a first target signal cmd_R1;

A second decoding unit 153, connected to the command sampling circuit 14 and the third delay unit 151, configured to perform a logic operation on the (n+1) -bit sub-signal of the third sampling signal and the (n+1) -bit sub-signal of the fourth sampling signal, and output a second decoded signal; the second decoding signal is sampled by the first delay control signal clk_r0d1 to output a second target signal cmd_r0.

Note that the third delay unit 151 is configured to delay the first control signal clk_r0d and the third control signal clk_r1d to achieve delay matching between signals. Specifically, the third delay unit 151 includes 2 third delay sub-units for delaying the first control signal clk_r0d and the third control signal clk_r1d, respectively. The first decoding unit 152 and the second decoding unit 153 in fig. 10 together constitute the decoding processing unit 150 in fig. 11.

In a specific embodiment, as shown in fig. 11, the first decoding unit 152 includes a fifth logic unit 1521 and a seventh flip-flop 1522; wherein the input terminal of the fifth logic unit 1521 receives the 4-bit sub-signals of the first sampling signal (i.e., ca0_r0d, ca1_r0d, ca2_r0d, ca3_r0d) and the 4-bit sub-signals of the second sampling signal (i.e., ca0_f0, ca1_f0, ca2_f0, ca3_f0), and the output terminal of the fifth logic unit 1521 outputs the first decoding signal; the input terminal of the seventh flip-flop 1522 receives the first decoded signal, the clock terminal of the seventh flip-flop 1522 receives the second delay control signal clk_r1d1, and the output terminal of the seventh flip-flop 1522 outputs the first target signal cmd_r1.

Similarly, as shown in fig. 11, the second decoding unit 153 includes a sixth logic unit 1531 and an eighth flip-flop 1532; the input terminal of the sixth logic unit 1531 receives the 4-bit sub-signals (i.e., ca0_r1d, ca1_r1d, ca2_r1d, ca3_r1d) of the third sampling signal and the 4-bit sub-signals (i.e., ca0_f1, ca1_f1, ca2_f1, ca3_f1) of the fourth sampling signal, and the output terminal of the sixth logic unit 1531 outputs the second decoding signal; the input terminal of the eighth flip-flop 1532 receives the second decoding signal, the clock terminal of the eighth flip-flop 1532 receives the first delay control signal clk_r0d1, and the output terminal of the eighth flip-flop 1532 outputs the second target signal cmd_r0.

It should be noted that the first target signal cmd_r1 and the second target signal cmd_r0 constitute a target decoding signal Command. The first target signal cmd_r1 indicates the content of the Command address signal CA Command at the 1 st initial clock cycle; the second target signal cmd_r0 indicates the content of the Command address signal CA Command at the 2 nd initial clock cycle. As previously mentioned, the initial clock period refers to the clock period of the initial clock signal Clk.

It should be noted that the fifth logic unit 1521 (or the sixth logic unit 1531) may be implemented by various logic devices, such as a nand gate, a nor gate, an exclusive-or gate, and the like, and specifically needs to be determined according to a specific decoding rule (or referred to as a decoding rule), which is not limited in the embodiments of the present disclosure.

The first to eighth flip-flops may be implemented by a D-type flip-flop, which may sample an input signal (i.e., a signal received by an input terminal) with a rising edge of a clock signal (i.e., a signal received by a clock terminal) to obtain an output signal (i.e., a signal at the output terminal); the first to eighth latches can be realized by two D-type flip-flops, and when the clock terminal is at a low level, the output changes with the input signal, and when the clock terminal is at a high level, the output remains unchanged.

In summary, for the command decoding circuit 10 provided in the embodiments of the present disclosure, fig. 12 provides a timing diagram from an overall perspective. As shown in fig. 12, the initial clock signal Clk is subjected to frequency division and phase separation to obtain a first clock signal clk_r0, a second clock signal clk_f0, a third clock signal clk_r1 and a fourth clock signal clk_f1, and the first clock signal clk_r0 to the fourth clock signal clk_f1 sample and logically process the chip select signal CSD (i.e., the initial chip select signal CS is delayed) to obtain a first control signal clk_r0 to a fourth control signal clk_f1 (see fig. 2A); the first control signal Clk_R0 to the fourth control signal Clk_F1 sample the command address signals CA <3:0> respectively, and sequentially obtain a first sampling signal CA <3:0> _R0d, a second sampling signal CA <3:0> _F0, a third sampling signal CA <3:0> _R1d and a fourth sampling signal CA <3:0> _F1. Then, the first sampled signal CA <3:0> _R0d, the second sampled signal CA <3:0> _F0, the third sampled signal CA <3:0> _R1d and the fourth sampled signal CA <3:0> _F1 are decoded to obtain a first target signal cmd_R1 and a second target signal cmd_R0 (not shown in FIG. 12); finally, the first target signal cmd_r1, the second target signal cmd_r0, the first chip select sampling signal cs_r0 and the second chip select sampling signal cs_r1 are decoded together, and the decoding result is sampled by the Command sampling clock signal ClkCmd _r1 to obtain the final target decoded signal Command. Here, the target decode signal Command can indicate the specific content of the current CA Command, for example PDE, SRE, ACT-1 and ACT-2 … … in table 1, and only the Command decode circuit in the selected semiconductor memory will sample and decode the CA input, so that not only the correct decoding of the Command address signal can be realized, but also the power consumption can be reduced.

In another embodiment of the present disclosure, referring to fig. 13, a schematic diagram of a composition structure of a semiconductor memory 30 provided by an embodiment of the present disclosure is shown. As shown in fig. 13, the semiconductor memory 30 may include the command decoding circuit 10 described in any of the foregoing embodiments.

In the disclosed embodiment, the semiconductor memory 30 may be a dynamic random access memory DRAM, and the semiconductor memory complies with the regulations of LPDDR 6.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments. The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A command decoding circuit, the command decoding circuit comprising:

2. The command decoding circuit of claim 1, wherein,

And under the condition that the chip selection signal does not meet the preset condition, the first control signal, the second control signal, the third control signal and the fourth control signal all keep the level state unchanged.

3. The command decoding circuit of claim 2, wherein,

The clock generation circuit is configured to receive an initial clock signal, perform frequency division and phase separation processing on an external initial clock signal, and output the first clock signal, the second clock signal, the third clock signal and the fourth clock signal;

4. A command decoding circuit according to claim 3, wherein the chip select signal is used to indicate whether the command address signal is valid or invalid, if the chip select signal meets a preset condition, the command address signal is valid, and if the chip select signal does not meet a preset condition, the command address signal is invalid;

The command address signal lasts for 2 initial clock cycles, and the initial clock cycles refer to clock cycles of the initial clock signal; the preset condition is that the chip selection signal has a level change edge in the 1 st initial clock period and the chip selection signal has a level change edge in the 2 nd initial clock period.

5. The command decoding circuit of claim 4, wherein,

When the chip selection signal meets a preset condition, the pulse width of the first control signal, the pulse width of the second control signal, the pulse width of the third control signal and the pulse width of the fourth control signal are the same, and the pulse width of the first control signal is the same as the initial clock period;

Wherein the pulse leading edge of the first control signal is aligned with the rising edge of the first clock signal, the pulse leading edge of the second control signal is aligned with the rising edge of the second clock signal, the pulse leading edge of the third control signal is aligned with the rising edge of the third clock signal, and the pulse leading edge of the fourth control signal is aligned with the rising edge of the fourth clock signal.

6. The command decoding circuit of claim 4, wherein the first conversion circuit comprises a first sampling unit, a first logic unit, and a second logic unit; wherein,

The first sampling unit is configured to sample the chip select signal by using the first clock signal to generate a first intermediate signal, sample the first intermediate signal by using an inverted signal of the first clock signal to generate a second intermediate signal, and sample the second intermediate signal by using the second clock signal to generate a third intermediate signal;

the first logic unit is connected with the first sampling unit and is configured to perform AND operation on the first intermediate signal and the first clock signal and output the first control signal;

the second logic unit is connected with the first sampling unit and is configured to perform AND operation on the third intermediate signal and the second clock signal and output the second control signal;

If the chip selection signal meets a preset condition, pulses exist in the first intermediate signal and the third intermediate signal, and the pulse width is larger than the initial clock period.

7. The command decoding circuit of claim 6, wherein the second conversion circuit comprises a second sampling unit, a third logic unit, and a fourth logic unit; wherein,

The second sampling unit is configured to sample the chip select signal by using the third clock signal to generate a fourth intermediate signal, sample the fourth intermediate signal by using an inverted signal of the third clock signal to generate a fifth intermediate signal, and sample the fifth intermediate signal by using the fourth clock signal to generate a sixth intermediate signal;

The third logic unit is connected with the second sampling unit and is configured to perform AND operation on the fourth intermediate signal and the third clock signal and output the third control signal;

the fourth logic unit is connected with the second sampling unit and is configured to perform an AND operation on the sixth intermediate signal and the fourth clock signal and output the fourth control signal;

And if the chip selection signal meets a preset condition, the fourth intermediate signal and the sixth intermediate signal have pulses, and the pulse width is larger than the initial clock period.

8. The command decoding circuit of claim 6, wherein the first sampling unit comprises a first latch, a second latch, a third latch, and a first inverter; wherein,

The input end of the first latch receives the chip selection signal, the clock end of the first latch receives the first clock signal, and the output end of the first latch outputs the first intermediate signal;

The input end of the second latch receives the first intermediate signal, the input end of the first inverter receives the first clock signal, the clock end of the second latch is connected with the output end of the first inverter, and the output end of the second latch outputs the second intermediate signal;

The input end of the third latch receives the second intermediate signal, the clock end of the third latch receives the second clock signal, and the output end of the third latch outputs the third intermediate signal.

9. The command decoding circuit of claim 7, wherein the second sampling unit comprises a fourth latch, a fifth latch, a sixth latch, and a second inverter;

The input end of the fourth latch receives the chip selection signal, the clock end of the fourth latch receives the third clock signal, and the output end of the fourth latch outputs the fourth intermediate signal;

The input end of the fifth latch receives the fourth intermediate signal, the input end of the second inverter receives the third clock signal, the clock end of the fifth latch is connected with the output end of the second inverter, and the output end of the fifth latch outputs the fifth intermediate signal;

the input end of the sixth latch receives the fifth intermediate signal, the clock end of the sixth latch receives the fourth clock signal, and the output end of the sixth latch outputs the sixth intermediate signal.

10. The command decoding circuit of claim 1, wherein the command decoding circuit further comprises a first delay unit and a second delay unit; wherein,

The first delay unit is connected with the first conversion circuit and the second conversion circuit and is configured to receive an initial chip selection signal from the outside, delay the initial chip selection signal and output the chip selection signal;

The second delay unit is connected with the command sampling circuit and is configured to receive an initial command address signal from the outside, delay the initial command address signal and output the command address signal.

11. The command decoding circuit of any one of claims 1-10, wherein the target sample signal comprises a first sample signal, a second sample signal, a third sample signal, and a fourth sample signal, and wherein the command address signal, the first sample signal, the second sample signal, the third sample signal, and the fourth sample signal each comprise an (n+1) bit sub-signal, the command sample circuit comprising (n+1) command sample cells;

An ith command sampling unit configured to perform sampling processing on an ith sub-signal of the command address signal twice by using the first control signal, and output the ith sub-signal of the first sampling signal; performing one-time sampling processing on an ith sub-signal of the command address signal by using the second control signal, outputting an ith sub-signal of the second sampling signal, performing two-time sampling processing on the ith sub-signal of the command address signal by using the third control signal, outputting an ith sub-signal of the third sampling signal, performing one-time sampling processing on the ith sub-signal of the command address signal by using the fourth control signal, and outputting an ith sub-signal of the fourth sampling signal;

The first sampling signal and the second sampling signal are in an aligned state in time sequence, the third sampling signal and the fourth sampling signal are in an aligned state in time sequence, i and N are positive integers, and i is less than or equal to (N+1).

12. The command decoding circuit of claim 11, wherein the ith command sampling unit comprises a first flip-flop, a seventh latch, a second flip-flop, a third flip-flop, an eighth latch, and a fourth flip-flop; wherein,

The input end of the first trigger receives the ith sub-signal of the command address signal, the clock end of the first trigger receives the first control signal, the input end of the seventh latch is connected with the output end of the seventh latch, the clock end of the seventh latch receives the first control signal, and the output end of the seventh latch outputs the ith sub-signal of the first sampling signal;

The input end of the second trigger receives the ith sub-signal of the command address signal, the clock end of the second trigger receives the second control signal, and the output end of the second trigger outputs the ith sub-signal of the second sampling signal;

The input end of the third trigger receives the ith sub-signal of the command address signal, the clock end of the third trigger receives the third control signal, the input end of the eighth latch is connected with the output end of the third trigger, the clock end of the eighth latch receives the third control signal, and the output end of the eighth latch outputs the ith sub-signal of the third sampling signal;

The input end of the fourth trigger receives the ith sub-signal of the command address signal, the clock end of the fourth trigger receives the fourth control signal, and the output end of the fourth trigger outputs the ith sub-signal of the fourth sampling signal.

13. The command decoding circuit of claim 12, wherein the command decoding circuit further comprises:

The decoding circuit is connected with the first conversion circuit, the second conversion circuit and the command sampling circuit and is configured to decode the first sampling signal, the second sampling signal, the third sampling signal and the fourth sampling signal to obtain intermediate decoding signals; sampling the intermediate decoding signal based on the first control signal and the third control signal, and outputting a target decoding signal;

A chip select sampling circuit, coupled to the clock generation circuit, configured to receive the chip select signal; the chip selection signal is sampled by the first clock signal and the third clock signal respectively, and a first chip selection sampling signal and a second chip selection sampling signal are output;

And the target decoding signal, the first chip selection sampling signal and the second chip selection sampling signal are logically processed to generate a target command signal.

14. The command decoding circuit of claim 13, wherein the decoding circuit comprises:

a third delay unit configured to delay the first control signal and output a first delayed control signal; performing delay processing on the third control signal and outputting a second delay control signal;

a first decoding unit connected to the third delay unit and configured to perform a logic operation on the (n+1) -bit sub-signal of the first sampling signal and the (n+1) -bit sub-signal of the second sampling signal, and output a first decoding signal; sampling the first decoding signal by using the second delay control signal, and outputting a first target signal;

A second decoding unit connected to the third delay unit and configured to perform a logic operation on the (n+1) bit sub-signal of the third sampling signal and the (n+1) bit sub-signal of the fourth sampling signal, and output a second decoding signal; sampling the second decoding signal by using the first delay control signal, and outputting a second target signal;

wherein the first target signal and the second target signal constitute the target decoded signal, the first target signal indicating the content of the command address signal at 1 st initial clock cycle; the second target signal indicates the content of the command address signal at the 2 nd initial clock cycle.

15. A semiconductor memory comprising the command decoding circuit according to any one of claims 1 to 14.

16. The semiconductor memory of claim 15, wherein the semiconductor memory is a dynamic random access memory DRAM and the semiconductor memory complies with LPDDR6 memory specifications.