CN117762193A - Variable clock structure circuit - Google Patents
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- CN117762193A CN117762193A CN202410193130.5A CN202410193130A CN117762193A CN 117762193 A CN117762193 A CN 117762193A CN 202410193130 A CN202410193130 A CN 202410193130A CN 117762193 A CN117762193 A CN 117762193A
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Abstract
The embodiment of the application provides a variable clock structure circuit. The variable clock circuit includes n clock fanout circuits, where n is an integer greater than 1. Each clock fan-out circuit comprises a crystal oscillator input end and a coaxial input end, wherein the crystal oscillator input end is connected with the crystal oscillator, and the coaxial input end is connected with an input end coaxial connector. The clock output end of each clock fan-out circuit is connected with the PCIE switching chip. The first coaxial output end is connected with the first output end coaxial connector, and the second coaxial output end is connected with the second output end coaxial connector. And except for the 1 st clock-fanout circuit, a first end of a first PCIE slot of the i-th clock-fanout circuit is connected to the RC device, and a second end is connected to a coaxial input end of the 1 st clock-fanout circuit through a first coaxial output end. Thus, by varying the input of the 1 st clock-fanout circuit, and varying the coaxial input of the i-th clock-fanout circuit, a variety of clock architectures can be implemented.
Description
Technical Field
the application relates to the technical field of communication, in particular to a circuit with a variable clock structure.
Background
The peripheral component interconnect express (peripheral component interconnect express, PCIE) switching chip is used for transmitting data among PCIE devices connected to the switching chip by organizing switching among PCIE channels in the peripheral component interconnect express (peripheral component interconnect express, PCIE) switching chip, so that data routing and forwarding are realized. Currently, PCIE switching performance is widely used in high performance computing architectures. In order to ensure data transmission of all PCIE setting keys, a PCIE switching chip needs a stable and reliable clock source. And the bandwidth and performance of PCIE switch chips are closely related to the quality of the connected clock source.
However, different PCIE switch chips are involved in different clock architectures, and how to design a clock architecture that meets the clock requirements of multiple types of PCIE switch chips becomes critical.
Disclosure of Invention
the embodiment of the application provides a variable clock structure circuit which is used for meeting the clock requirements of PCIE switching chips of various types.
the embodiment of the application provides a variable clock structure circuit, which comprises n clock fan-out circuits, wherein n is an integer greater than 1;
The crystal oscillator input end of each clock fan-out circuit in the n clock fan-out circuits is used for being connected with a corresponding crystal oscillator, the coaxial input end of each clock fan-out circuit is used for being connected with a corresponding input end coaxial connector, the first coaxial output end of each clock fan-out circuit is used for being connected with a corresponding first output end coaxial connector, the second coaxial output end of each clock fan-out circuit is connected with a corresponding second output end coaxial connector, and the clock output end of each clock fan-out circuit is connected with the clock input end of a peripheral component interconnect express PCIE switching chip; the first output end coaxial connector and the second output end coaxial connector are used for connecting different clock fan-out circuits;
The first end of the first PCIE slot of the ith clock-fan-out circuit in the n clock-fan-out circuits is used for being connected with RC equipment, the second end of the first PCIE slot of the ith clock-fan-out circuit is used for being connected to the first coaxial input end of the 1 st clock-fan-out circuit through a first coaxial output end, n is more than or equal to i and more than 1, and n is an integer.
optionally, the 2 clock outputs of the 1 st clock fanout circuit are used for connecting the 2 clock inputs of the PCIE switching chip.
Optionally, the ith clock fanout circuit further includes: and the at least one second PCIE slot is used for providing a second clock signal, and the second clock signal is used for representing a clock signal different from the first clock signal output by the clock output end of the ith clock fan-out circuit.
Optionally, the n clock fanout circuits include: and the power supply is provided by the low-dropout linear voltage regulator.
Optionally, if the RC device, the PCIE switch chip and the port device corresponding to the variable clock structure circuit are homologous clocks,
the first end of the first PCIE slot of the ith clock-out circuit is connected with the RC equipment, and the second end of the first PCIE slot of the ith clock-out circuit is connected to the coaxial input end of the 1 st clock-out circuit through a first coaxial output end;
The first coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the i th clock fan-out circuit through a first output end coaxial connector, the second coaxial output end of the 1 st clock fan-out circuit is connected with the j th clock fan-out circuit in the n clock fan-out circuits through a second output end coaxial connector, j is not equal to i, n is not less than j is more than 1, and j is an integer;
and the crystal oscillator input end of the jth clock fan-out circuit and the crystal oscillator input end of the 1 st clock fan-out circuit are in idle states.
optionally, if the RC device, the PCIE switch chip and the port device corresponding to the variable clock structure circuit are independent clocks,
a first end of a first PCIE slot of the ith clock fan-out circuit is connected with the RC equipment;
The crystal oscillator input end of the ith clock fan-out circuit and the crystal oscillator input end of the 1 st clock fan-out circuit are both in working states.
Optionally, if the RC device is an independent clock, the PCIE switch chip and the port device corresponding to the variable clock structure circuit are homologous clocks,
a first end of a first PCIE slot of the ith clock fan-out circuit is connected with the RC equipment;
The first coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the i th clock fan-out circuit through a first output end coaxial connector, the second coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the j th clock fan-out circuit in the n clock fan-out circuits through a second output end coaxial connector, j is not equal to i, n is not less than j and is larger than 1, and j is an integer;
The crystal oscillator input end of the 1 st clock fan-out circuit is in a working state, and the crystal oscillator input end of the i-th clock fan-out circuit and the crystal oscillator input end of the j-th clock fan-out circuit are in idle states.
optionally, if the port device corresponding to the variable clock structure circuit is an independent clock, the PCIE switching chip and the RC device are homologous clocks,
a first end of a first PCIE slot of the ith clock-out circuit is connected with the RC equipment, and a second end of the first PCIE slot is connected to a coaxial input end of the 1 st clock-out circuit through a first coaxial output end;
And the crystal oscillator input end of the ith clock fan-out circuit is in a working state.
Optionally, if the port devices corresponding to the RC device and the variable clock structure circuit are homologous clocks, the PCIE switching chip is an independent clock,
a first end of a first PCIE slot of the ith clock fan-out circuit is connected with the RC equipment;
The first coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the i th clock fan-out circuit through a first output end coaxial connector, the second coaxial output end of the i th clock fan-out circuit is connected with the coaxial input end of the j th clock fan-out circuit in the n clock fan-out circuits through a second output end coaxial connector, j is not equal to i, n is not less than j and is larger than 1, and j is an integer.
Optionally, the second end of the first PCIE slot of the ith clock-out circuit is connected to one end of a switch component, and the other end of the switch component is used to connect to the coaxial input end of the 1 st clock-out circuit through a first coaxial output end; the switch assembly is connected in a jumping mode through a three-terminal capacitor. The beneficial effects are that:
The embodiment of the application provides a variable clock structure circuit. The variable clock circuit includes n clock fanout circuits, where n is an integer greater than 1. Each clock fan-out circuit comprises two input ends, namely a crystal oscillator input end and a coaxial input end, wherein the crystal oscillator input end is connected with the crystal oscillator, and the coaxial input end is connected with an input end coaxial connector. Each clock fan-out circuit comprises a plurality of output ends, wherein the clock output ends are connected with the PCIE exchange chips and are used for providing clock signals for the PCIE exchange chips. The first coaxial output end is connected with the first output end coaxial connector, and the second coaxial output end is connected with the second output end coaxial connector. And except for the 1 st clock-fanout circuit, a first end of a first PCIE slot of the i-th clock-fanout circuit is connected to the RC device, and a second end is connected to a coaxial input end of the 1 st clock-fanout circuit through a first coaxial output end. Thus, by changing the input end of the 1 st clock fan-out circuit and changing the coaxial input end of the i th clock fan-out circuit, various clock architectures, such as implementing a homologous clock architecture of the PCIE switching chip, the RC device and the variable clock structure circuit, an independent clock structure, and an architecture in which the PCIE switching chip is an independent clock, the RC device and the variable clock structure circuit is a homologous clock, etc., can be implemented. Therefore, the variable clock structure circuit provided by the embodiment of the application can realize variable clock structure, so that the clock architecture meeting the requirements of PCIE exchange chips can be designed based on the variable clock structure.
Drawings
FIG. 1 is a schematic diagram of a homologous clock architecture;
FIG. 2 is a schematic diagram of an independent clock architecture;
FIG. 3 is a schematic diagram of a partition clock architecture according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a circuit diagram of a variable clock structure according to an embodiment of the present application;
Fig. 5 is a schematic diagram of another variable clock circuit according to an embodiment of the present application.
Detailed Description
With the landing of 5G technology, the data throughput capacity requirement is greatly increased, the pressure of the operation bandwidth is also increased, and the speed requirement on heterogeneous computing buses is also increased, so that the accelerated development of the number and the speed of core bus PCIE bus channels in the high-performance computing architecture is promoted.
The PCIE exchange chip is used for transmitting data among PCIE devices connected to the exchange chip through exchange among PCIE channels organized in the PCIE exchange chip, so that data routing and forwarding are realized. Currently, PCIE switching performance is widely used in high performance computing architectures. In order to ensure data transmission of all PCIE setting keys, a PCIE switching chip needs a stable and reliable clock source. And the bandwidth and performance of PCIE switch chips are closely related to the quality of the connected clock source.
In order to ensure the reliability of the clock source connected to the PCIE switch chips, different clock architectures are often required for PCIE switch chips of different types. The prior art clock architecture is a solidified one. For example, a homologous clock architecture, or an independent clock architecture.
To better illustrate the solidified clock architecture, a description is first given of a homologous clock architecture, an independent clock architecture, and a partitioned clock architecture.
Referring to fig. 1, a schematic diagram of a homologous clock architecture is shown.
the Root Complex (RC) device 101 and the endpoint device (hereinafter, the endpoint device is denoted by EP device) 103 to which the PCIE switch chip 102 is connected use the homologous clock PCIE Refclk.
Referring to fig. 2, a schematic diagram of an independent clock architecture is shown.
The RC device 101 connected to the PCIE switch chip 102 is connected to the clock source refclk#1, and the connected EP device 103 is connected to refclk#2. Wherein refclk#1 and refclk#2 are used to represent different clock sources.
Referring to fig. 3, a schematic diagram of a partition clock architecture according to an embodiment of the present application is provided. The PCIE switch chip performs partitioning, and is divided into 2 parts, which are part 1 and part 0 respectively. The clocks of part 1 and part 0 are independent. The RC device, PCIE switching chip, and EP device 3 in Partition0 use an independent clock. In fig. 3, P0, P4 and P6 are 3 ports of the PCIE switch chip, and the 3 ports share a separate clock P00CLK with the RC device and the EP device.
In Partition 1, the RC device and the port P2 of the PCIE switch chip share one independent clock (the clock shown in fig. 3 is P02 CLK), and the port P8, the port P12 and the EP device of the PCIE switch chip share another independent clock (the clock is two paths, one path is P12CLK, and the other path is P08 CLK).
The clock architecture adopted by the PCIE switching chip at present is a combination of the three clock architectures. As shown in table 1, a clock architecture commonly used for PCIE switch chips is provided.
Table 1 clock architecture in PCIE switch chips
However, the clock structure of the present PCIE clock circuit design is a solidified clock structure, i.e. only one clock structure of table 1 can be supported. However, PCIE switch chips are of a large variety, and different PCIE switch chips require different clock architectures, so that different PCIE clock circuits need to be designed, and the universality is poor.
in view of the above problems, an embodiment of the present application provides a variable clock structure circuit for implementing a PCIE clock circuit to support different clock architectures.
the following describes the variable clock structure circuit provided by the embodiment of the application in detail and completeness.
Referring to fig. 4, a circuit schematic diagram of a variable clock structure is provided in an embodiment of the present application. The variable clock structure circuit includes n clock fanout circuits. Wherein n is an integer greater than 1, that is, n may be 2, 3, 4, or the like.
Each clock fan-out circuit comprises a crystal oscillator input end and a coaxial input end, wherein the crystal oscillator input end is used for being connected with a corresponding crystal oscillator, and the coaxial input end is used for being connected with a corresponding input end coaxial connector. Namely, the crystal oscillator input end of the 1 st clock fan-out circuit is connected with the crystal oscillator A11, the coaxial input end is connected with the coaxial connector A11, the crystal oscillator input end of the 2 nd clock fan-out circuit is connected with the crystal oscillator A21, the coaxial input end is connected with the coaxial connectors A22 and …, the crystal oscillator input end of the nth clock fan-out circuit is connected with the crystal oscillator An1, and the coaxial input end is connected with the coaxial connector An2. Wherein, coaxial connector a11, coaxial connector a22 and coaxial connector An2 are used to represent different coaxial connectors. Crystal oscillator A11, crystal oscillator A22 and crystal oscillator An2 are used to represent different crystal oscillators.
Each clock-fanout circuit includes a clock output and two coaxial outputs (a first coaxial output and a second coaxial output, respectively). The first coaxial output end is connected with the corresponding first output end coaxial connector, and the second coaxial output end is connected with the corresponding second output end coaxial connector. Namely, the first coaxial output end of the 1 st clock fan-out circuit is connected with the first coaxial connector a12, the second coaxial output end is connected with the second coaxial connector a13, the first coaxial output end of the 2 nd clock fan-out circuit is connected with the first output end coaxial connector a21, the second coaxial output end is connected with the second coaxial connectors a23 and … …, the first coaxial output end of the n-th clock fan-out circuit is connected with the first output end coaxial connector An1, and the second coaxial output end is connected with the second coaxial connector An3. The first output coaxial connector a21, the first output coaxial connector An1 represent different first output coaxial connectors. The second coaxial connectors a13, a23, an3 represent different second coaxial connectors.
In addition, except for the 1 st clock fan-out circuit, the first end of the first PCIE slot of the other clock fan-out circuits is connected to the RC device, the second end is connected to the first output end coaxial connector, and the first coaxial input end of the 1 st clock fan-out circuit is connected through the first output end coaxial connector. For example, the PCIE slot a21 of the 2 nd clock-fanout circuit is connected to the first coaxial connector a21, and the first coaxial connector a21 is connected to the input coaxial connector a11 of the 1 st clock-fanout circuit.
Optionally, the number of clock output ends of the 1 st clock output circuit may be m, where m is an integer greater than 1 and less than or equal to n. Each clock output end is connected with a partition of a PCIE switching chip. Wherein the number of m is determined according to the number of partitions of the PCIE switching chip. In the embodiment of the application, the number of the output ends of the 1 st clock output circuit is limited to be the same as the number of the partitions of the PCIE switching chip, so that the partition clock architecture of the PCIE switching chip is realized.
Therefore, by changing the input end of the 1 st clock fan-out circuit and the coaxial input end of other clock fan-out circuits, the application can realize various clock architectures, such as a PCIE switching chip, RC equipment and a homologous clock architecture of a variable clock structure circuit, an independent clock structure, and an architecture in which the PCIE switching chip is an independent clock, the RC equipment and the variable clock structure circuit is a homologous clock. Therefore, the variable clock structure circuit provided by the embodiment of the application can realize variable clock structure, so that the clock architecture meeting the requirements of PCIE exchange chips can be designed based on the variable clock structure.
In order to better illustrate the structural schematic diagram of the variable clock structure circuit provided by the embodiment of the application. The following description will take an example in which the clock fanout circuit includes 3: clock-out 1, clock-out 2, clock-out 3. It will be appreciated by those skilled in the art that the number of clock fanout circuits is not limited to 3, but may be plural, such as 5, such as 10, etc. The present application is not particularly limited.
Referring to fig. 5, a schematic diagram of another variable clock structure circuit according to an embodiment of the present application is shown. The circuit comprises a clock-fan-out 1, a clock-fan-out 2, and a clock-fan-out 3.
The input channels of the clock fan-out 1, the clock fan-out 2 and the clock fan-out 3 have 2 paths, one path (namely, a crystal oscillator input end) is the crystal oscillator of the plate, and the other path (namely, a coaxial input end) is a coaxial connector. The clock fan-out 1 is connected with the crystal oscillator A1 and the coaxial connection A1. The clock fan-out 2 connects the crystal B1 and the coaxial connector B2. The clock fan-out 3 connects the crystal oscillator C1 and the coaxial connection C2.
the clock output channels of the clock fanout 1, the clock fanout 2 and the clock fanout 3 are all connected with the PCIE switch chip, wherein the clock level for the PCIE switch chip is current mode logic (Current Mode Logic, CML) by default.
It should be noted that the above CML is only schematically illustrated, and the clock level may be other levels by default according to needs, such as Low-voltage differential signal (Low-Voltage Differential Signaling, LVDS), low-voltage positive power emitter coupling logic (Low voltage positive emitter couped logic, LVPECL), high-speed current driving logic (High-speed Current Steering Logic, HSCL), and the like, which are not particularly limited in the present application.
In the embodiment of the application, one path of the clock fan-out 1 is connected with the coaxial connector A2, and the other path is connected with the coaxial connector A3. The default clock level of the coaxial connector in the embodiment of the application can be CML type, LVDS, LVPECL, etc. The present application is not particularly limited. The clock fan-out 1 is also connected with a power supply 1, and the power supply 1 is controlled by the FPGA controller. Alternatively, the power supply 1 may be a low dropout linear regulator (low dropout regulator, LDO) chip output circuit, which helps reduce filtering of the power supply 1 and keeps the voltage stable.
The clock output end of the clock fan-out 2 includes PCIE slot B1, PCIE slot B2, PCIE slot B3, PCIE slot B4, and may be of HSCL type for default level. It should be noted that HSCL is only schematically shown, and the default type may be LVDS level, LVPECL level, CML level, or the like, as required, and the present application is not particularly limited. In order to improve the clock level flexibility of the clock architecture, the default levels of PCIE slots B1, PCIE slot B2, PCIE slot B3, PCIE slot B4 are different from the clock output level. Therefore, the clock level in the clock architecture can be quickly changed by changing the interface with the PCIE exchange chip, and the requirements of the PCIE chip and the port device are met. The clock of PCIE slot B1 may be configured as an input (the input signal is the clock of clock fanout 2) through SW1, and configured as an output through SW1, and the clock is output to coaxial connector B1. For this reason, SW1 needs to satisfy the three-terminal capacitance to realize the jumper connection.
the clock output end of the clock fan-out 3 includes PCIE slot C1, PCIE slot C2, PCIE slot C3, PCIE slot C4, and may be of HSCL type at a default level. It should be noted that HSCL is only schematically shown, and the default type may be LVDS level, LVPECL level, CML level, or the like, as required, and the present application is not particularly limited. In order to improve the clock level flexibility of the clock architecture, the default levels of PCIE slots C1, PCIE slot C2, PCIE slot C3, PCIE slot C4 are different from the clock output level. Therefore, the clock level in the clock architecture can be quickly changed by changing the interface with the PCIE exchange chip, and the requirements of the PCIE chip and the port device are met. The clock of PCIE slot B1 may be configured with an input (the input signal is the clock of clock fanout 2) through SW2, and configured with an output through SW2, and the clock is output to the coaxial connector C1. For this reason, SW2 needs to satisfy the three-terminal capacitance to realize the jumper connection.
the power supply 2 corresponding to the clock fan-out 2 and the power supply 3 corresponding to the clock fan-out 3 are powered on and powered off by the FPGA, are LDO chips, and can generate low-voltage ripple signals. Therefore, the power supply is controlled by the FPGA to flexibly control the power-on and power-off time sequence of the clock chip, the power supply can be turned off in the idle state of the clock chip, the power consumption of the whole machine is reduced, and the space radiation interference and the source of crosstalk on the PCB can be eliminated.
The PCIE switching chip provided by the embodiment of the present application includes 2 partitions, which are respectively a Bank1 and a Bank2. Each bank has 16 high speed channels (Lane 0-15). Each bank has an independent clock input. The clock input to Bank1 selects, via SW3, whether the clock source is clock fan-out 1 or clock fan-out 2. The clock input to Bank2 selects, via SW4, whether the clock source is clock-fan 1 or clock-fan 3.SW3 and SW4 are three terminal capacitance implementation hops.
In the embodiment of the application, one path of CML clock output end of the clock fan-out 1 is communicated with the Bank1 through the SW3, and the other path of CML clock output end is communicated with the Bank2 through the SW 4. The clock output of the clock fan-out 2 communicates with Bank1 through SW 3. The clock output of the clock fan-out 4 communicates with Bank2 through SW 4.
The following describes various operating states provided by the embodiment of the present application with reference to fig. 2.
In one possible embodiment, if the clocks of the RC device and the PCIE switch chip and the EP device are identical, the clocks of the RC device and the PCIE switch chip and the EP device are identical. Optionally, the PCIE slot B1 is connected to the RC device, and the PCIE slot B1 configures the clock to be output to the coaxial connector B1 through SW1, and the coaxial connector B1 is interconnected with the coaxial connector A1 through a cable. The input channel of the clock-fan 1 selects the coaxial connector A1. The clock fan-out 1 outputs signals to the PCIE switch chip and the coax A2 and the coax A3, and SW3 and SW4 select the clock source to be the clock fan-out 1.
the coaxial connector A2 and the coaxial connector B2 are interconnected by a cable, and the coaxial connector A3 and the coaxial connector C2 are interconnected by a cable. At this time, the input channel of the clock fan-out 2 selects the coaxial connector B2. The clock fan-out 2 outputs signals to the PCIE slots B2, B3, and B4. The input channel of the clock-fanout 3 selects the coaxial connector C2. The clock fanout 3 outputs signals to the PCIE slots C1, C2, C3, and C4.
It should be noted that, the RC device may be connected to PCIE slot C1, and the specific implementation is the same as that of connection B1, which is not discussed here.
In another possible embodiment, if the RC device and PCIE switch chip and EP device are clocked independently. Optionally, PCIE slot B1 connects to an RC device. PCIE slot B1 clocks idle state. The input channel of the clock fan-out 1 selects the crystal oscillator A1. The clock fanout 1 outputs signals to the PCIE switch chip, and SW3 and SW4 select the clock source to be the clock fanout 1. The input channel of the clock fan-out 2 selects the crystal B1. The clock fan-out 2 outputs signals to the PCIE slots B2, B3, and B4. The input channel of the clock-fanout 3 selects the crystal oscillator C1. The clock fanout 3 outputs signals to the PCIE slots C1, C2, C3, and C4.
It should be noted that, the RC device may be connected to PCIE slot C1, and the specific implementation is the same as that of connection B1, which is not discussed here.
In yet another possible implementation, if the RC device is independent of the clock; PCIE switching chips are clocked homologous to the EP device. Optionally, PCIE slot B1 connects to an RC device. PCIE slot B1 clocks idle state. The input channel of the clock fan-out 1 selects the crystal oscillator A1. The clock fan-out 1 outputs signals to the PCIE switch chip and the coax A2 and the coax A3, and SW3 and SW4 select the clock source to be the clock fan-out 1. The coaxial connector A2 and the coaxial connector B2 are interconnected by a cable, and the coaxial connector A3 and the coaxial connector C2 are interconnected by a cable. The input channel of the clock-fan-out 2 selects the coaxial connector B2. The clock fan-out 2 outputs signals to the PCIE slots B2, B3, and B4. The input channel of the clock-fanout 3 selects the coaxial connector C2. The clock fanout 3 outputs signals to the PCIE slots C1, C2, C3, and C4.
It should be noted that, the RC device may be connected to PCIE slot C1, and the specific implementation is the same as that of connection B1, which is not discussed here.
in another possible implementation manner, if the RC device exchanges chip homologous clocks with the PCIE; the EP device is independent clock. Optionally, PCIE slot B1 connects to an RC device. PCIE slot B1 configures the clock to be output to coaxial connector B1 through SW1, coaxial connector B1 and coaxial connector A1 being interconnected by a cable. The input channel of the clock-fan 1 selects the coaxial connector A1. The clock fanout 1 outputs signals to the PCIE switch chip, and SW3 and SW4 select the clock source to be the clock fanout 1. The input channel of the clock fan-out 2 selects the crystal B1. The clock fan-out 2 outputs signals to the PCIE slots B2, B3, and B4. The input channel of the clock-fanout 3 selects the crystal oscillator C1. The clock fanout 3 outputs signals to the PCIE slots C1, C2, C3, and C4.
It should be noted that, the RC device may be connected to PCIE slot C1, and the specific implementation is the same as that of connection B1, which is not discussed here.
In one possible implementation, if the RC device is clocked homologous to the EP device; PCIE switches chip independent clocks. Optionally, PCIE slot B1 connects to an RC device. The input channel of the clock fan-out 1 selects the crystal oscillator A1. The clock fanout 1 outputs signals to the PCIE switch chip, and SW3 and SW4 select the clock source to be the clock fanout 1. The input channel of the clock-fan-out 2 selects the coaxial connector B2. The clock fan-out 2 outputs signals to the PCIE slots B2, B3, and B4.PCIE slot B1 configures the clock to be output to coaxial connector B1 through SW1, coaxial connector B1 and coaxial connector B2 being interconnected by a cable. The coaxial connector B3 and the coaxial connector C2 are interconnected by a cable. The input channel of the clock-fanout 3 selects the coaxial connector C2. The clock fanout 3 outputs signals to the PCIE slots C1, C2, C3, and C4.
It should be noted that, the RC device may be connected to PCIE slot C1, and the specific implementation is the same as that of connection B1, which is not discussed here.
In yet another possible implementation, if the RC device and PCIE switch chip and EP device partition clock architecture. Both PCIE slot B1 and PCIE slot C1 may be connected to RC devices, and may be connected to 2 RC devices. PCIE slot B1 is connected with RC equipment, PCIE slot C1 is connected with another RC equipment. The input channel of the clock fan-out 1 selects the crystal oscillator A1. The clock fanout 1 outputs signals to the PCIE switch chip and the coax connector A2, SW3 selects the clock source to be the clock fanout 2, and SW4 selects the clock source to be the clock fanout 1. The coaxial connector A2 and the coaxial connector C2 are interconnected by a cable.
The input channel of the clock-fan-out 2 selects the coaxial connector B2. The clock fan-out 2 outputs signals to the PCIE switch chip and PCIE slots B2, PCIE slot B3, PCIE slot B4.PCIE slot B1 configures the clock to be output to coaxial connector B1 through SW1, coaxial connector B1 and coaxial connector B2 being interconnected by a cable. The partition of the clock fan-out 2 supports the three homologous clocks of the RC equipment, the PCIE exchange chip and the EP equipment.
The input channel of the clock-fanout 3 selects the coaxial connector C2.PCIE slot C1 clocks idle state. The clock fanout 3 outputs signals to the PCIE slots C2, C3, C4. The partitions of the clock fanout 3 support RC device independent clocks; PCIE switching chips are clocked homologous to the EP device.
In yet another possible implementation, if the RC device and PCIE switch chip and EP device partition clock architecture. Both PCIE slot B1 and PCIE slot C1 may be connected to RC devices, and may be connected to 2 RC devices. PCIE slot B1 is connected with RC equipment, PCIE slot C1 is connected with another RC equipment. The input channel of the clock-fan 1 selects the coaxial connector A1. The clock fanout 1 outputs signals to the PCIE switch chip, and SW3 and SW4 select the clock source to be the clock fanout 1.
The input channel of the clock fan-out 2 selects the crystal B1. The clock fanout 2 outputs signals to PCIE slots B2, B3, B4.PCIE slot B1 configures the clock to be output to coaxial connector B1 through SW1, coaxial connector B1 and coaxial connector A1 being interconnected by a cable. The partition of the clock fan-out 2 supports the homologous clocks of RC equipment and PCIE exchange chips; the EP device is independent clock.
The input channel of the clock-fanout 3 selects the crystal oscillator C1.PCIE slot C1 clocks idle state. The clock fanout 3 outputs signals to the PCIE slots C2, C3, C4. The partition of the clock fan-out 3 supports independent clocks of the RC equipment, the PCIE exchange chip and the EP equipment.
From the foregoing description of the embodiments, it will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of functional modules is illustrated, and in practical application, the above-described functional allocation may be implemented by different functional modules according to needs, i.e. the internal structure of the apparatus is divided into different functional modules to implement all or part of the functions described above. The specific working processes of the above-described systems, devices and units may refer to the corresponding processes in the foregoing method embodiments, which are not described herein.
In the several embodiments provided in this embodiment, it should be understood that the disclosed system and method may be implemented in other ways. For example, the embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present embodiment may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units described above may be implemented in hardware.
the integrated unit may be implemented as a switching chip and sold or used as a stand-alone product. Based on such understanding, the technical solution of the present embodiment may be essentially or a part contributing to the prior art or all or part of the technical solution may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in the respective embodiments. And the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic or optical disk, and the like.
The foregoing is merely illustrative of specific embodiments of the present application, and the scope of the present application is not limited thereto, but any changes or substitutions within the technical scope of the present application should be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A variable clock structure circuit comprising n clock fanout circuits, n being an integer greater than 1;
The crystal oscillator input end of each clock fan-out circuit in the n clock fan-out circuits is used for being connected with a corresponding crystal oscillator, the coaxial input end of each clock fan-out circuit is used for being connected with a corresponding input end coaxial connector, the first coaxial output end of each clock fan-out circuit is used for being connected with a corresponding first output end coaxial connector, the second coaxial output end of each clock fan-out circuit is connected with a corresponding second output end coaxial connector, and the clock output end of each clock fan-out circuit is connected with the clock input end of a peripheral component interconnect express PCIE switching chip; the first output end coaxial connector and the second output end coaxial connector are used for connecting different clock fan-out circuits;
The first end of the first PCIE slot of the ith clock-fan-out circuit in the n clock-fan-out circuits is used for connecting root complex RC equipment, the second end of the first PCIE slot of the ith clock-fan-out circuit is used for connecting to the first coaxial input end of the 1 st clock-fan-out circuit through the first coaxial output end, n is greater than or equal to i > 1, and n is an integer.
2. the variable clock architecture circuit of claim 1, wherein 2 clock outputs of the 1 st clock fanout circuit are used to connect 2 clock inputs of the PCIE switching chip.
3. the variable clock structure circuit of claim 1, wherein the ith clock fanout circuit further comprises: and the at least one second PCIE slot is used for providing a second clock signal, and the second clock signal is used for representing a clock signal different from the first clock signal output by the clock output end of the ith clock fan-out circuit.
4. The variable clock structure circuit of claim 1, wherein the n clock fanout circuits comprise: and the power supply is provided by the low-dropout linear voltage regulator.
5. The variable clock architecture circuit of any one of claims 1-4, wherein if the RC device, the PCIE switch chip and the port device corresponding to the variable clock architecture circuit are homologous clocks,
a first end of a first PCIE slot of the ith clock-out circuit is connected with the RC equipment, and a second end of the first PCIE slot of the ith clock-out circuit is connected to a coaxial input end of the 1 st clock-out circuit through a corresponding first coaxial output end;
The first coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the i th clock fan-out circuit through a corresponding first output end coaxial connector, the second coaxial output end of the 1 st clock fan-out circuit is connected with the j-th clock fan-out circuit in the n clock fan-out circuits through a corresponding second output end coaxial connector, j is not equal to i, n is not less than j and is larger than 1, and j is an integer;
and the crystal oscillator input end of the jth clock fan-out circuit and the crystal oscillator input end of the 1 st clock fan-out circuit are in idle states.
6. The variable clock architecture circuit of any one of claims 1-4, wherein if the RC device, the PCIE switch chip and the port device corresponding to the variable clock architecture circuit are independent clocks,
a first end of a first PCIE slot of the ith clock fan-out circuit is connected with the RC equipment;
The crystal oscillator input end of the ith clock fan-out circuit and the crystal oscillator input end of the 1 st clock fan-out circuit are both in working states.
7. The variable clock architecture circuit of any one of claims 1-4, wherein if the RC device is an independent clock, the PCIE switch chip and the port device corresponding to the variable clock architecture circuit are homologous clocks,
a first end of a first PCIE slot of the ith clock fan-out circuit is connected with the RC equipment;
the first coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the i th clock fan-out circuit through a corresponding first output end coaxial connector, the second coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the j th clock fan-out circuit in the n clock fan-out circuits through a corresponding second output end coaxial connector, j is not equal to i, n is not less than j > 1, and j is an integer;
The crystal oscillator input end of the 1 st clock fan-out circuit is in a working state, and the crystal oscillator input end of the i-th clock fan-out circuit and the crystal oscillator input end of the j-th clock fan-out circuit are in idle states.
8. the variable clock architecture circuit of any one of claims 1-4, wherein if the port device corresponding to the variable clock architecture circuit is an independent clock, the PCIE switch chip and the RC device are homologous clocks,
a first end of a first PCIE slot of the ith clock-out circuit is connected with the RC equipment, and a second end of the first PCIE slot is connected to a coaxial input end of the 1 st clock-out circuit through a corresponding first coaxial output end;
And the crystal oscillator input end of the ith clock fan-out circuit is in a working state.
9. The variable clock architecture circuit of any one of claims 1-4, wherein if the RC device and the port device corresponding to the variable clock architecture circuit are homologous clocks, the PCIE switch chip is an independent clock,
a first end of a first PCIE slot of the ith clock fan-out circuit is connected with the RC equipment;
The first coaxial output end of the 1 st clock fan-out circuit is connected with the coaxial input end of the i th clock fan-out circuit through a corresponding first output end coaxial connector, the second coaxial output end of the i th clock fan-out circuit is connected with the coaxial input end of the j th clock fan-out circuit in the n clock fan-out circuits through a corresponding second output end coaxial connector, j is not equal to i, n is not less than j and is larger than 1, and j is an integer.
10. The variable clock architecture circuit of any one of claims 1-4, wherein a first PCIE slot second end of the ith clock-fanout circuit is connected to one end of a switch assembly, and wherein the other end of the switch assembly is configured to be connected to a coaxial input of the 1 st clock-fanout circuit through a first coaxial output; the switch assembly is connected in a jumping mode through a three-terminal capacitor.
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| WO2024016896A1 (en) * | 2022-07-19 | 2024-01-25 | 普源精电科技股份有限公司 | Multi-phase clock generation circuit and method |
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| CN113986795A (en) * | 2021-12-23 | 2022-01-28 | 苏州浪潮智能科技有限公司 | Clock architecture, method and medium supporting PCIE (peripheral component interface express) clock |
| WO2024016896A1 (en) * | 2022-07-19 | 2024-01-25 | 普源精电科技股份有限公司 | Multi-phase clock generation circuit and method |
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