CN115425956A - Multi-path fan-out circuit and clock driver - Google Patents
Multi-path fan-out circuit and clock driver Download PDFInfo
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- CN115425956A CN115425956A CN202210934578.9A CN202210934578A CN115425956A CN 115425956 A CN115425956 A CN 115425956A CN 202210934578 A CN202210934578 A CN 202210934578A CN 115425956 A CN115425956 A CN 115425956A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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Abstract
The application discloses multichannel fan-out circuit and clock driver relates to the clock driver field, includes: the LVPECL circuit comprises an amplifying circuit, a bias circuit and a plurality of LVPECL output circuits, wherein the bias circuit is respectively connected with the amplifying circuit and each LVPECL output circuit and is used for providing current bias and switching signals. The LVPECL output circuit comprises two conversion circuits which are in mirror symmetry. The amplifying circuit is connected with the LVPECL output circuit and used for amplifying the differential input signal and outputting a first level standard signal and a second level standard signal. The LVPECL output circuit is used for converting the first level standard signal and the second level standard signal into a first output signal and a second output signal. The function of converting a group of differential input signals into multi-channel high-speed data output can be realized, and because the two conversion circuits are arranged in a mirror symmetry manner, the low skew can be realized when the signal output by each conversion circuit is used as a clock signal.
Description
Technical Field
The present application relates to the field of clock technologies, and in particular, to a multi-channel fan-out circuit and a clock driver.
Background
The clock driver is widely applied to the fields of wireless communication, data networks and the like, and the basic function of the clock driver is to enhance the driving capability of a clock signal, so that the functions of timing synchronization, clock generation, clock recovery, clock distribution and the like of a communication network can be realized. Generally, the clock signal is the signal with the highest hopping frequency of the whole system, which can interfere with the normal working state of the surrounding circuit, and the larger the amplitude and the higher the frequency of the clock signal are, the stronger the interference to the surrounding circuit is. In addition, due to the existence of parasitic capacitance on a circuit board where the clock driver is located, the input clock signal with a large amplitude needs more time to be charged and discharged, and the propagation speed of the clock signal is limited, so that a reasonable clock driver is required to be used as buffering in a multi-clock high-speed circuit system, the driving capability is improved, and the transmission of multiple clock signals is realized.
Disclosure of Invention
The application provides a multi-path fan-out circuit and a clock driver, which are used for converting a single-path differential input signal into a multi-path output signal.
The technical scheme is as follows:
in a first aspect, a multi-fan-out circuit is provided, the circuit comprising: the LVPECL circuit comprises an amplifying circuit, a biasing circuit and a plurality of LVPECL output circuits, wherein the biasing circuit is respectively connected with the amplifying circuit and each LVPECL output circuit, and is used for providing current bias and switching signals;
each LVPECL output circuit comprises two mirror-symmetrical conversion circuits;
the amplifying circuit is connected with the two conversion circuits included in each LVPECL output circuit and used for amplifying a group of received differential input signals to obtain a first level standard signal and a second level standard signal with opposite potentials;
the LVPECL output circuit is configured to convert the first level standard signal into a first output signal by one of the two conversion circuits, and to convert the second level standard signal into a second output signal by the other of the two conversion circuits, the second output signal and the first output signal having opposite potentials.
The embodiment of the application provides a multi-path fan-out circuit, wherein a group of differential input signals input to an amplifying circuit are amplified by the amplifying circuit to obtain a first level standard signal and a second level standard signal, and the first level standard signal and the second level standard signal are provided for a plurality of LVPECL output circuits. Because the amplifying circuit is connected with a plurality of LVPECL output circuits, each LVPECL output circuit can convert a first level standard signal and a second level standard signal as input signals to obtain two output signals, namely a first output signal and a second output signal, so that the scheme can realize the function of converting a group of differential input signals into a plurality of paths of high-speed data for output.
Optionally, the potential of the first level standard signal is opposite to the potential of the first output signal, and the potential of the second level standard signal is opposite to the potential of the second output signal.
Optionally, the conversion circuit includes an emitter follower circuit, a differential amplifier circuit and an emitter coupling circuit, the emitter follower circuit is used for receiving a level standard signal, and the emitter follower circuit is connected to the differential amplifier circuit; the level standard signal is the first level standard signal or the second level standard signal;
the differential amplification circuit is used for receiving the signal output by the emitter follower circuit and amplifying the signal output by the emitter follower circuit, and the differential amplification circuit is connected with the emitter coupling circuit;
the emitter coupling circuit is used for receiving the signal output by the differential amplification circuit and enabling the potential of the output signal output by the emitter coupling circuit to be opposite to the potential of the level standard signal.
Optionally, the emitter follower circuit includes a first triode, and a base of the first triode is used for receiving the level standard signal;
the differential amplification circuit comprises a second triode and a first resistor, wherein the base electrode of the second triode is connected with the emitting electrode of the first triode, the collector electrode of the second triode is connected with the first end of the first resistor, and the second end of the first resistor is used for receiving voltage provided by an external power supply;
the emitter coupling circuit comprises a third triode, the base electrode of the third triode is connected with the collector electrode of the second triode, and the emitter electrode of the third triode is used for outputting the output signal.
Optionally, the LVPECL output circuit further includes a first bias current source and a second bias current source, the first bias current source is connected to the emitter follower circuit in the first conversion circuit of the two conversion circuits, and the second bias current source is connected to the differential amplifier circuit in the first conversion circuit.
Optionally, one of the two conversion circuits is duplicated by the other of the two conversion circuits.
Optionally, the set of differential input signals comprises a first signal and a second signal which are equal in amplitude and opposite in phase, the amplifying circuit comprises an input circuit and an intermediate amplifying circuit,
the first input end of the input circuit is used for receiving the first signal, the second input end of the input circuit is used for receiving the second signal, the first output end of the input circuit is connected with the first input end of the intermediate amplification circuit, the second output end of the input circuit is connected with the second input end of the intermediate amplification circuit, and the input circuit is used for pre-amplifying the first signal to obtain a first-stage amplification signal and pre-amplifying the second signal to obtain a second-stage amplification signal;
the output end of the middle amplifying circuit is connected with each LVPECL output circuit, and is used for amplifying the primary amplifying signal to obtain the first level standard signal and amplifying the secondary amplifying signal to obtain the second level standard signal.
Optionally, the input circuit includes a first differential amplifier, the intermediate amplifying circuit includes a second differential amplifier, a first input terminal of the first differential amplifier is configured to receive the first signal, and a second input terminal of the first differential amplifier is configured to receive the second signal;
a first input end of the second differential amplifier is configured to receive the first-stage amplified signal, a second input end of the second differential amplifier is configured to receive the second-stage amplified signal, an output end of the second differential amplifier is connected to a first input end and a second input end of each LVPECL output circuit, the first input end of the LVPECL output circuit is configured to receive the first level standard signal, and the second input end of the LVPECL output circuit is configured to receive the second level standard signal.
Optionally, at least one of the first differential amplifier and the second differential amplifier includes the following structure: the fourth triode, the fifth triode, the third resistor, the fourth resistor and the third bias current source;
a base of the fourth transistor is configured to receive the first signal, a base of the fifth transistor is configured to receive the second signal,
the collector of the fourth triode is connected with the first end of the third resistor, the collector of the fifth triode is connected with the first end of the fourth resistor,
the second end of the third resistor and the second end of the fourth resistor are used for receiving voltage provided by an external power supply,
and the emitter of the fourth triode and the emitter of the fifth triode are connected with the third bias current source.
In a second aspect, a clock driver is provided that employs the multi-fan-out circuit as described above. It is understood that the beneficial effects of the second aspect can be referred to the related description of the first aspect, and are not described herein again.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a multi-fan-out circuit according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a conversion circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit structure diagram of an LVPECL output circuit according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of an amplifying circuit provided in an embodiment of the present application;
fig. 5 is a circuit configuration diagram of a differential amplifier according to an embodiment of the present application;
fig. 6 is a block diagram 1: a schematic diagram of a 16 fan-out circuit;
fig. 7 is a schematic diagram of an LVPECL output circuit according to an embodiment of the present disclosure.
Detailed Description
To make the objects, technical solutions and advantages of the present application more clear, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
It should be understood that reference to "a plurality" in this application means two or more. In the description of the present application, "/" means "or" unless otherwise stated, for example, a/B may mean a or B; "and/or" herein is only an association relationship describing an association object, and means that there may be three relationships, for example, a and/or B, and may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, for the convenience of clearly describing the technical solutions of the present application, the terms "first", "second", and the like are used to distinguish the same items or similar items having substantially the same functions and actions. Those skilled in the art will appreciate that the terms "first," "second," and the like do not denote any order or importance, but rather the terms "first," "second," and the like do not denote any order or importance.
Before explaining the embodiments of the present application in detail, an application scenario of the embodiments of the present application will be described.
The oscillator generates a set of differential input signals, requires multiplexing the same differential input signals, and therefore requires a clock driver to fan out the set of differential input signals in multiple ways.
The multi-fan-out circuit and the clock driver provided in the embodiments of the present application are explained in detail below.
Fig. 1 is a multi-fan-out circuit provided in an embodiment of the present application, including: an amplifier circuit 101, a bias circuit 102, and a plurality of LVPECL output circuits 103. The amplifier circuit 101 is connected to a plurality of LVPECL output circuits 103, and the bias circuit 102 is connected to the amplifier circuit 101 and the plurality of LVPECL output circuits 103, respectively. The bias circuit 102 is used for providing a current bias and a switching signal for the amplifying circuit 101 and the plurality of Low Voltage Positive Emitter Coupled Logic (LVPECL) output circuits 103. Each LVPECL output circuit comprises two switching circuits that are mirror symmetric. The amplifying circuit 101 is connected to two conversion circuits included in each LVPECL output circuit 103, and is configured to amplify a set of received differential input signals to obtain a first level standard signal and a second level standard signal with opposite potentials. The LVPECL output circuit 103 is configured to convert the first level standard signal into a first output signal by one of the two conversion circuits, and to convert the second level standard signal into a second output signal by the other of the two conversion circuits, the second output signal being opposite in potential to the first output signal.
The amplifying circuit 101 is configured to receive a set of differential input signals, i.e. a first signal and a second signal with equal amplitudes and opposite phases. Such as VINP signals and VINN signals. After receiving the VINP signal and the VINN signal, the amplifying circuit 101 amplifies the two signals, so that the signal finally output by the amplifying circuit meets the standard condition of the LVPECL output circuit 103.
In one embodiment of the present application, the multi-fan-out circuit includes 16 LVPECL output circuits, and each LVPECL output circuit receives a level standard signal required to satisfy the LVPECL standard, so that the amplifying circuit 101 outputs the first level standard signal OUTP and the second level standard signal OUTN according to the condition of the LVPECL output circuit.
The embodiment of the application provides a multi-path fan-out circuit, wherein a group of differential input signals input to an amplifying circuit are amplified by the amplifying circuit to obtain a first level standard signal and a second level standard signal, and the first level standard signal and the second level standard signal are provided for a plurality of LVPECL output circuits. Because the amplifying circuit is connected with a plurality of LVPECL output circuits, each LVPECL output circuit can convert a first level standard signal and a second level standard signal as input signals to obtain two output signals, namely a first output signal and a second output signal, so that the scheme can realize the function of converting a group of differential input signals into multi-path high-speed data for output.
In one embodiment of the present application, the potential of the first level standard signal is opposite to the potential of the first output signal, and the potential of the second level standard signal is opposite to the potential of the second output signal.
As an example, when the potential of the first level standard signal is a high level signal, the first output signal is a low level signal, whereas when the potential of the first level standard signal is a low level signal, the first output signal is a high level signal. The second level standard signal is the same as the second output signal, and the description is omitted again.
In one embodiment of the present application, as shown in fig. 2, the conversion circuit 1031 includes an emitter follower circuit 201, a differential amplifier circuit 202, and an emitter coupling circuit 203. The emitter follower circuit 201 is used for receiving a first level standard signal, and the emitter follower circuit 201 is connected with the differential amplifier circuit 202. The differential amplifier circuit 202 is used for receiving the signal output by the emitter follower circuit 201, the differential amplifier circuit 202 is used for amplifying the signal output by the emitter follower circuit 201, and the differential amplifier circuit 202 is connected with the emitter coupling circuit 203. The emitter-coupling circuit 203 is for receiving the signal output from the differential amplification circuit, and for making the potential of the output signal output from the emitter-coupling circuit 203 opposite to the potential of the level standard signal.
As an example, as shown in fig. 2 and 3, the emitter follower circuit 201 includes a transistor Q1 (i.e., a first transistor), and a base of the transistor Q1 is used for receiving the first level standard signal. The differential amplifier circuit 202 comprises a transistor Q2 (i.e. a second transistor) and a resistor R0 (i.e. a first resistor), wherein a base electrode of the transistor Q2 is connected with an emitting electrode of the transistor Q1, a collector electrode of the transistor Q2 is connected with a first end of the resistor R0, and a second end of the resistor R0 is used for receiving a voltage provided by an external power supply VDD. The emitter-coupled circuit 203 includes a transistor Q3 (i.e., a third transistor), a base of the transistor Q3 is connected to a collector of the transistor Q2, and an emitter of the transistor Q3 is used for outputting a first output signal. In the case where the first level standard signal is at a high potential and the second level standard signal is at a low potential, the emitter coupling circuit 203 matches the levels of the first level standard signal and the first output signal, and matches the levels of the second level standard signal and the second output signal, that is, the first output signal is at a low potential and the second output signal is at a high potential.
In one embodiment of the present application, the LVPECL output circuit 103 further comprises a first bias current source and a second bias current source. The first bias current source is connected with the emitter follower circuit, and the second bias current source is connected with the differential amplification circuit.
As an example, as shown in fig. 3, the positive terminal of the bias current source Ibias1 (i.e., the first bias current source) is connected to the emitter of the transistor Q1 (i.e., the first transistor), and the positive terminal of the bias current source Ibias0 (i.e., the second bias current source) is connected to the emitter of the diode Q2 (i.e., the second diode).
In an embodiment of the present application, since the two conversion circuits 1031 have the same structure, as an example, referring to fig. 3, a first conversion circuit 301 and a second conversion circuit 302 are divided. The second conversion circuit 302 includes a transistor Q4, a transistor Q5, a transistor Q6, and a resistor R1. The base of the triode Q4 is used for receiving the second level standard signal. The base electrode of the triode Q5 is connected with the emitting electrode of the triode Q4, the collector electrode of the triode Q5 is connected with the first end of the resistor R1, and the second end of the resistor R1 is used for receiving voltage provided by an external power supply VDD. The base electrode of the triode Q6 is connected with the collector electrode of the triode Q5, and the emitting electrode of the triode Q6 is used for outputting a second output signal.
The positive electrode of a bias current source Ibias1 which is the same as the first bias current source is connected with the emitter of the triode Q5, and the positive electrode of a bias current source Ibias0 (namely, a second bias current source) is connected with the emitter of the diode Q5.
In one embodiment of the present application, referring to fig. 3, one of the first conversion circuit 301 and the second conversion circuit 302 is duplicated from the other.
As an example, the layout technology adopted by the LVPECL output circuit 103 is HALF CELL technology. HALF CELL technology includes: when drawing the circuit layout of the LVPECL output circuit 103, the first conversion circuit 301 is drawn first. The first conversion circuit 301 is multiplexed to generate a second conversion circuit 302, and the first conversion circuit 301 and the second conversion circuit 302 form a circuit layout of the LVPECL output circuit.
Specifically, referring to fig. 2, when the LVPECL output circuit 103 is drawn, the first conversion circuit 301, that is, the left half of the dotted line 1 in fig. 3, is drawn, and after the drawing is completed, the circuit diagram is copied and subjected to a mirror image operation, and the emitter of the transistor Q2 is connected to the emitter of the transistor Q5, so that the drawing of the circuit diagram of the LVPECL output circuit 103 is completed.
In one embodiment of the present application, a set of differential input signals includes first and second signals that are equal in amplitude and opposite in phase. As shown in fig. 4, the amplification circuit 101 includes an input circuit 401 and an intermediate amplification circuit 402. The input end of the input circuit 401 is configured to receive a first differential input signal and a second differential input signal, and the output end of the input circuit 401 is connected to the input end of the intermediate amplifying circuit. The input circuit 401 is configured to pre-amplify the first differential input signal to obtain a first-stage amplified signal, and to pre-amplify the second differential input signal to obtain a second-stage amplified signal. The output end of the middle amplifying circuit 402 is connected to each LVPECL output circuit 103, and is configured to amplify the first-level amplified signal to obtain a first level standard signal, and to amplify the second-level amplified signal to obtain a second level standard signal. In one embodiment of the present application, the input circuit 401 includes a first differential amplifier, and the intermediate amplification circuit 402 includes a second differential amplifier. The first differential amplifier is used for receiving a first differential input signal and a second differential input signal, and the second differential amplifier is used for receiving a signal output by the input circuit. The first differential amplifier and the second differential amplifier have the same circuit structure.
As an example, two input terminals of the first differential amplifier are used for receiving a first differential input signal VINP and a second differential input signal VINN, and the first differential amplifier pre-amplifies and shapes the first differential input signal and the second differential input signal and outputs two output signals OUTP and OUTN. The input end of the second differential amplifier receives the signals OUTP and OUTN output by the first differential amplifier, that is, the second differential amplifier takes the signals OUTP and OUTN as input signals, and the second differential amplifier further amplifies the signals OUTP and OUTN and outputs a first level standard signal and a second level standard signal.
In one embodiment of the present application, a circuit configuration diagram of the first differential amplifier is shown in fig. 5. The first differential amplifier includes a transistor Q7 (i.e., a fourth transistor), a transistor Q8 (i.e., a fifth transistor), a resistor R2 (i.e., a third resistor), a resistor R3 (i.e., a fourth resistor), and a bias current source Ibias2 (i.e., a third bias current source). The base of transistor Q7 is configured to receive the first differential input signal, and the base of transistor Q8 is configured to receive the second differential input signal. The collector of the transistor Q7 is connected to the first terminal of the resistor R2, and the collector of the transistor Q8 is connected to the first terminal of the resistor R3. The second end of the resistor R2 and the second end of the resistor R3 are used for receiving the voltage provided by the external power supply VDD, and the emitter of the transistor Q7 and the emitter of the transistor Q8 are connected with a bias current source Ibias2.
The intermediate amplification circuit 402 includes a second differential amplifier having the same structure as the first differential amplifier, as shown in fig. 5. And the base electrode of the triode Q7 and the base electrode of the triode Q8 are used for receiving two output signals output by the first differential amplifier. The collector of the transistor Q7 and the collector of the transistor Q8 are used to output the first level standard signal and the second level standard signal, respectively.
The embodiment of the application provides a clock driver, which is applied to a multi-clock high-speed circuit system, and the clock driver adopts the multi-path fan-out circuit. The multi-fan-out circuit is configured to receive a set of clock input signals (e.g., a first differential input signal and a second differential input signal) and output a plurality of sets of clock output signals (e.g., a plurality of sets of a first output signal and a second output signal).
Fig. 6 shows a multi-fan-out circuit in a clock driver according to an embodiment of the present application. The input circuit 601 is a first differential amplifier for receiving differential input signals VINP and VINN. The intermediate amplifying circuit 602 is a second differential amplifier, and is configured to receive the differential input signal processed by the input circuit 601 and amplify the signal into a first level standard signal and a second level standard signal. The bias circuit 603 is connected to the input circuit 601, the intermediate amplifier circuit 602, and the 16 LVPECL output circuits 604 for providing a bias current and a turn-off signal. When the input circuit 601 receives the first differential input signal VINP and the second differential input signal VINN, the first differential amplifier and the second differential amplifier process the received signals to output the first level standard signal and the second level standard signal to each LVPECL output circuit 604, each LVPECL output circuit 604 amplifies the first level standard signal and the second level standard signal to output the first output signal and the second output signal, and finally outputs 16 sets of the first output signal OUTN and the second output signal OUTP.
As another example, as shown in fig. 7, the LVPECL output circuit 701 is structured as shown in the figure. The first level standard signal and the second level standard signal are INP and INN, are connected to the base electrodes of the triode Q1 and the triode Q4, and are provided with tail current bias by Vb. Triode Q1 is the same with triode Q4 size, and output signal connects triode Q2 and triode Q5's base, and the signal after the amplification is exported by triode Q3 and triode Q6, and wherein triode Q2 is the same with triode Q5 size, and triode Q3 is the same with triode Q6 size, provides the tail current biasing by Vb. After the first level standard signal INP and the second level standard signal INN pass through the emitter followers, namely the triode Q1 and the triode Q4, the common mode voltage is reduced, the pair transistors of the differential amplifier, namely the triode Q2 and the triode Q5 are ensured to be in an amplification area, the magnitude of tail current Ib is controlled by Vb, and the output swing amplitude is Ib & R4. When INP is high potential, the base potential of the triode Q2 is high through the triode Q1, and similarly, the base potential of the triode Q5 is low, most of tail current flows through the triode Q2, the base potential of the triode Q3 is low potential, the base potential of the triode Q6 is high potential, the output OUTN is low potential, and the OUTP is high potential; the reverse is true, and will not be described herein.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the technical solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.
Claims (10)
1. A multi-way fan-out circuit, the circuit comprising: an amplifying circuit, a bias circuit and a plurality of LVPECL output circuits,
the bias circuit is respectively connected with the amplifying circuit and each LVPECL output circuit, and is used for providing current bias and switching signals;
each LVPECL output circuit comprises two conversion circuits which are in mirror symmetry;
the amplifying circuit is connected with the two conversion circuits included in each LVPECL output circuit and used for amplifying a group of received differential input signals to obtain a first level standard signal and a second level standard signal with opposite potentials;
the LVPECL output circuit is configured to convert the first level standard signal into a first output signal by one of the two conversion circuits, and to convert the second level standard signal into a second output signal by the other of the two conversion circuits, the second output signal and the first output signal having opposite potentials.
2. The circuit according to claim 1, wherein a potential of the first level standard signal is opposite to a potential of the first output signal, and a potential of the second level standard signal is opposite to a potential of the second output signal.
3. The circuit of claim 1, wherein the conversion circuit comprises an emitter follower circuit, a differential amplifier circuit, and an emitter-coupled circuit,
the emitter follower circuit is used for receiving a level standard signal and is connected with the differential amplification circuit; the level standard signal is the first level standard signal or the second level standard signal;
the differential amplification circuit is used for receiving the signal output by the emitter follower circuit and amplifying the signal output by the emitter follower circuit, and the differential amplification circuit is connected with the emitter coupling circuit;
the emitter coupling circuit is used for receiving the signal output by the differential amplification circuit and enabling the potential of the output signal output by the emitter coupling circuit to be opposite to the potential of the level standard signal.
4. The circuit of claim 3, wherein the emitter follower circuit comprises a first transistor having a base for receiving the level reference signal;
the differential amplification circuit comprises a second triode and a first resistor, wherein the base electrode of the second triode is connected with the emitting electrode of the first triode, the collector electrode of the second triode is connected with the first end of the first resistor, and the second end of the first resistor is used for receiving voltage provided by an external power supply;
the emitter coupling circuit comprises a third triode, the base electrode of the third triode is connected with the collector electrode of the second triode, and the emitter electrode of the third triode is used for outputting the output signal.
5. The circuit of any of claims 1-4, wherein said LVPECL output circuit further comprises a first bias current source connected to the emitter follower circuit of a first of said two switching circuits and a second bias current source connected to the differential amplifier circuit of said first switching circuit.
6. A circuit as claimed in any one of claims 1 to 4, wherein one of the two conversion circuits is duplicated by the other of the two conversion circuits.
7. A circuit according to any one of claims 1 to 3, wherein the set of differential input signals comprises first and second signals of equal amplitude and opposite phase, the amplifying circuit comprises an input circuit and an intermediate amplifying circuit,
the first input end of the input circuit is used for receiving the first signal, the second input end of the input circuit is used for receiving the second signal, the first output end of the input circuit is connected with the first input end of the intermediate amplifying circuit, the second output end of the input circuit is connected with the second input end of the intermediate amplifying circuit, and the input circuit is used for pre-amplifying the first signal to obtain a first-stage amplified signal and pre-amplifying the second signal to obtain a second-stage amplified signal;
the output end of the middle amplifying circuit is connected with each LVPECL output circuit, and the middle amplifying circuit is used for amplifying the first-level amplifying signal to obtain the first level standard signal and amplifying the second-level amplifying signal to obtain the second level standard signal.
8. The circuit of claim 7, wherein the input circuit comprises a first differential amplifier, the intermediate amplification circuit comprises a second differential amplifier,
a first input terminal of the first differential amplifier is used for receiving the first signal, and a second input terminal of the first differential amplifier is used for receiving the second signal;
a first input end of the second differential amplifier is configured to receive the first-stage amplified signal, a second input end of the second differential amplifier is configured to receive the second-stage amplified signal, an output end of the second differential amplifier is connected to a first input end and a second input end of each LVPECL output circuit, the first input end of the LVPECL output circuit is configured to receive the first level standard signal, and the second input end of the LVPECL output circuit is configured to receive the second level standard signal.
9. The circuit of claim 8, wherein at least one of the first differential amplifier and the second differential amplifier comprises the structure:
a fourth triode, a fifth triode, a third resistor, a fourth resistor and a third bias current source,
a base of the fourth transistor is configured to receive the first signal, a base of the fifth transistor is configured to receive the second signal,
the collector of the fourth triode is connected with the first end of the third resistor, the collector of the fifth triode is connected with the first end of the fourth resistor,
the second end of the third resistor and the second end of the fourth resistor are used for receiving voltage provided by an external power supply,
and the emitter of the fourth triode and the emitter of the fifth triode are connected with the third bias current source.
10. A clock driver, characterized in that the clock driver employs the multi-way fanout circuit of any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210934578.9A CN115425956A (en) | 2022-08-04 | 2022-08-04 | Multi-path fan-out circuit and clock driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210934578.9A CN115425956A (en) | 2022-08-04 | 2022-08-04 | Multi-path fan-out circuit and clock driver |
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| CN115425956A true CN115425956A (en) | 2022-12-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210934578.9A Pending CN115425956A (en) | 2022-08-04 | 2022-08-04 | Multi-path fan-out circuit and clock driver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117762193A (en) * | 2024-02-21 | 2024-03-26 | 井芯微电子技术(天津)有限公司 | Variable clock structure circuit |
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2022
- 2022-08-04 CN CN202210934578.9A patent/CN115425956A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117762193A (en) * | 2024-02-21 | 2024-03-26 | 井芯微电子技术(天津)有限公司 | Variable clock structure circuit |
| CN117762193B (en) * | 2024-02-21 | 2024-05-10 | 井芯微电子技术(天津)有限公司 | Variable clock structure circuit |
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