CN115296662A

CN115296662A - Multiphase clock generating circuit and method

Info

Publication number: CN115296662A
Application number: CN202210848272.1A
Authority: CN
Inventors: 严波; 许强; 王悦
Original assignee: Puyuan Jingdian Technology Co ltd
Current assignee: Puyuan Jingdian Technology Co ltd
Priority date: 2022-07-19
Filing date: 2022-07-19
Publication date: 2022-11-04
Also published as: WO2024016896A1

Abstract

The application discloses a multiphase clock generating circuit and a method, belongs to the technical field of signal processing, and is used for solving the problems of complex structure and high power consumption of the existing multiphase clock generating circuit. The circuit comprises: the signal input end of the frequency division module receives and is connected with a clock source signal and is used for carrying out frequency division on the clock source signal by two to generate a first reference clock signal and a second reference clock signal which are intersected with each other; and the multi-phase clock generation module is connected with the output end of the frequency division module, and is used for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal with a predetermined phase difference relation.

Description

Multiphase clock generating circuit and method

Technical Field

The application belongs to the technical field of signal processing, and particularly relates to a multiphase clock generation circuit and a multiphase clock generation method.

Background

In signal processing systems, such as Time-Interleaved Analog-to-Digital converters (TIADC), multichannel Time-to-Digital converters (TDC), and the like, multiple clocks having a fixed clock skew relationship need to be used, and such multiple clocks are referred to as multiphase clocks.

Most of the existing multiphase clocks are generated by using Phase Locked Loops (PLLs) or Delay Locked Loops (DLLs) and other technologies, and both the two methods need to use a feedback Loop, a large-area Loop filter and an external reference clock, so that the problems of complex circuit, high power consumption and the like exist.

Disclosure of Invention

The embodiment of the application aims to provide a multi-phase clock generating circuit and a method, which can solve the problems of complex structure and high power consumption of the existing multi-phase clock generating circuit.

In order to solve the technical problem, the present application is implemented as follows:

in a first aspect, an embodiment of the present application provides a multiphase clock generation circuit, including: the clock source signal processing device comprises a frequency division module, a first clock signal processing module and a second clock signal processing module, wherein the signal input end of the frequency division module receives and is connected with a clock source signal and is used for carrying out frequency division on the clock source signal by two to generate a first reference clock signal and a second reference clock signal which are intersected with each other; and the multi-phase clock generation module is connected with the output end of the frequency division module and used for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal with a predetermined phase difference relation.

In a second aspect, an embodiment of the present application provides a multiphase clock generation method, where the method is applied to the multiphase clock generation circuit described in the first aspect, and the method includes: dividing a clock source signal by two through a frequency division module to generate a first reference clock signal and a second reference clock signal which are intersected with each other, wherein a signal input end of the frequency division module receives the clock source signal; and receiving the first reference clock signal and the second reference clock signal through a multi-phase clock generation module and outputting a four-phase clock signal with a predetermined phase difference relation, wherein the multi-phase clock generation module is connected with the frequency division module.

In a third aspect, embodiments of the present application provide an electronic device, which includes a processor, a memory, and a program or instructions stored on the memory and executable on the processor, and when executed by the processor, the program or instructions implement the steps of the multiphase clock generation method according to the second aspect.

In a fourth aspect, embodiments of the present application provide a readable storage medium, on which a program or instructions are stored, which when executed by a processor implement the steps of the multiphase clock generation method according to the second aspect.

In a fifth aspect, the present application provides a chip, where the chip includes a processor and a communication interface, where the communication interface is coupled to the processor, and the processor is configured to execute a program or instructions to implement the steps of the multiphase clock generation method according to the second aspect.

In the embodiment of the present application, through a frequency division module, a signal input end of the frequency division module receives a connection clock source signal, and is configured to divide the frequency of the clock source signal by two to generate a first reference clock signal and a second reference clock signal that intersect with each other; and the multi-phase clock generation module is connected with the output end of the frequency division module and used for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal with a predetermined phase difference relationship, so that the problems of complex structure and high power consumption of the conventional multi-phase clock generation circuit can be solved.

Drawings

Fig. 1 is a schematic structural diagram of a multiphase clock generation circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic structural diagram of a multiphase clock generation module of another multiphase clock generation circuit provided in an embodiment of the present application;

fig. 3 is a schematic structural diagram of a multiphase clock generation module of another multiphase clock generation circuit according to an embodiment of the present application;

FIG. 4 is a schematic flow chart diagram of a multiphase clock generation method provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a multiphase clock generating apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic structural diagram of an electronic device provided in the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/", and generally means that the former and latter related objects are in an "or" relationship.

A multiphase clock generating circuit and a method provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a multiphase clock generation circuit according to an embodiment of the present disclosure. The multiphase clock generation circuit 100 includes: a frequency dividing module 110, a signal input end of which receives and connects a clock source signal, and is configured to divide the clock source signal by two to generate a first reference clock signal and a second reference clock signal that intersect with each other; a multi-phase clock generating module 120, connected to the output end of the frequency dividing module, for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal having a predetermined phase difference relationship.

In one implementation, the multiphase clock generation circuit 100 transmits signals in a differential manner.

It should be noted that, the ability of common mode and interference resistance of the circuit can be enhanced by transmitting signals in a differential mode. The differential transmission is that the sending end transmits electric signals with equal amplitude and opposite phases on two signal lines, and the receiving end performs subtraction operation on the received signals of the two lines, so that signals with doubled amplitudes are obtained. The anti-interference principle is as follows: if both signal lines are subjected to the same (in-phase, equal amplitude) interference signal, the received signals of the two lines are subtracted by the receiving end, so that the interference signals are basically cancelled.

As shown in fig. 1, the input terminals VIP and VIN of the frequency dividing module 110 are used as differential input terminals of the whole circuit, the clock source signal CLKIN is input, the clock source signal is divided by two to generate a first reference clock signal Ref _ CLK1 and a second reference clock signal Ref _ CLK2 intersecting each other with a phase difference of 90 °, which are respectively connected to the two differential input terminals VIP _1/VIN _1 and VIP _2/VIN _2 of the multi-phase clock generating module 120, and the four pairs of differential outputs of the multi-phase clock generating module, i.e., a _ VOP/a _ VON, B _ VOP/B _ VON, C _ VOP/C _ VON, D _ VOP/D _ VON, are four phase clock signal output terminals of the whole circuit, and respectively output clock signals a _ CLK, B _ CLK, C _ CLK, D _ CLK of four channels.

The multiphase clock generating circuit provided by the application can realize the output of a four-phase clock through the combination of the frequency dividing module and the multiphase clock generating module, does not need a feedback loop, a large-area loop filter and an external reference clock in the multiphase clock generating circuit based on PLL or DLL, has a simple structure, is convenient to design and produce, and has great advantages in area and power consumption.

According to the multiphase clock generation circuit provided by the embodiment of the application, through the frequency division module, the signal input end of the frequency division module receives and is connected with a clock source signal, and the frequency division module is used for carrying out frequency division on the clock source signal to generate a first reference clock signal and a second reference clock signal which are mutually intersected; and the multiphase clock generation module is connected with the output end of the frequency division module and used for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal with a preset phase difference relationship, so that the problems of complex structure and high power consumption of the conventional multiphase clock generation circuit can be solved.

In one implementation, the multi-phase clock generation module includes: a plurality of multiplexing modules, wherein each multiplexing module is configured to directly output or flip-flop the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal; and/or each multiplexing module is used for directly outputting or overturning the second reference clock signal to obtain a signal of at least one channel in the four-phase clock signals.

In one implementation, each multiplexing module includes a plurality of signal input terminals and a signal selection terminal, where each signal input terminal receives the first reference clock signal or the second reference clock signal, the signals received by the plurality of signal input terminals are not identical, and the signal selection terminal is configured to control the multiplexing module to select one of the first reference clock signal and the second reference clock signal for inputting a signal of at least one channel of the four-phase clock signals.

The multiphase clock generation module comprises a mode selection end, wherein the mode selection end receives a mode control signal and is used for controlling and generating the four-phase clock signals in different modes, and the different modes correspond to different predetermined phase difference relations.

In one implementation, the multiphase clock generation module further comprises: and the buffer module is used for directly outputting the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal.

Fig. 2 is a schematic structural diagram of a multiphase clock generation module of a multiphase clock generation circuit according to an embodiment of the present disclosure. One embodiment of the present application provides a multiphase clock generation circuit comprising: the clock source signal processing device comprises a frequency division module, a first clock signal processing module and a second clock signal processing module, wherein the signal input end of the frequency division module receives and is connected with a clock source signal and is used for carrying out frequency division on the clock source signal by two to generate a first reference clock signal and a second reference clock signal which are intersected with each other; a multi-phase clock generating module 220, connected to the output of the frequency dividing module, for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal having a predetermined phase difference relationship, wherein, as shown in fig. 2, the multi-phase clock generating module 220 includes: a

buffer module

221 and 3

multiplexing modules

222, 223 and 224. The differential input end VIP/VIN of the buffer module 221 is connected to the first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN, and the differential output end VOP/VON is used as the a-channel differential output end of the circuit to output the signal a _ CLK, as can be known from fig. 1, the output phase is 0 °.

The VIP _1/VIN _1 terminals of the differential input path 1 of the multiplexing module 222 are receiving the first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; the VIP _2/VIN _2 end of the differential input path 2 is reversely connected with the first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; s <0> is connected with a gating signal MODE _ SELECT <0>, and the phase of 1 or 2 channels can be selected to be output; the differential output terminal VOP/VON is used as the B-channel differential output terminal of the whole circuit to output the signal B _ CLK, and the output phase is 0 ° or 180 ° as can be seen from fig. 1.

The VIP _1/VIN _1 terminals of the differential input path 1 of the multiplexing module 223 are receiving the second reference clock signal Ref _ CLK2_ VIP/Ref _ CLK2_ VIN; the VIP _2/VIN _2 end of the differential input path 2 is positively connected with a first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; s <0> is connected with a gating signal MODE _ SELECT <1>, and the phase of a 1 or 2 channel can be selected for output; the differential output terminal VOP/VON is used as the C-channel differential output terminal of the whole circuit to output the signal C _ CLK, and as can be seen from fig. 1, the output phase is 90 ° or 0 °.

The VIP _1/VIN _1 terminals of the differential input path 1 of the multiplexing module 224 are receiving the first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; the VIP _2/VIN _2 end of the differential input path 2 is reversely connected with a first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; the VIP _3/VIN _3 ends of the differential input path 3 are reversely connected with a second reference clock signal Ref _ CLK2_ VIP/Ref _ CLK2_ VIN; s <0> is connected with a gating signal MODE _ SELECT <2>, the phase of 1, 2 or 3 channels can be selected for output, the differential output end VOP/VON is used as the D channel differential output end of the whole circuit, and the output phase of a signal D _ CLK can be known to be 0 degrees, 180 degrees or 270 degrees from FIG. 1.

In summary, by selecting the control signal MODE _ SELECT <2>, the main available outputs of the circuit are: 0 °, 90 °, 180 °, 270 °;0 °, 0 °; three output modes of 0 degree, 180 degrees, 0 degree and 180 degrees.

In one implementation manner, the frequency division module includes a synchronization signal terminal, and the synchronization signal terminal receives a synchronization control signal and is used for performing synchronization control on generation of the first reference clock signal and the second reference clock signal.

In the embodiment of the application, the frequency division module with the synchronization function can synchronize the four-phase clock, so that the determination of the time sequence relation can be realized. Meanwhile, a plurality of multiplexing modules are connected in parallel, a clock source signal can be converted and output to obtain a four-phase clock signal with a preset phase difference relationship under the condition of less circuits, the circuit is simple in structure and low in power consumption, and the design of the circuit has certain advantages in time delay, temperature drift and phase noise.

The multiphase clock generation circuit provided by the embodiment of the application comprises the following modules: a plurality of multiplexing modules, wherein each multiplexing module is configured to directly output or flip-flop the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal; and/or each multiplexing module is configured to directly output or flip-flop the second reference clock signal to obtain a signal of at least one channel in the four-phase clock signal, where each multiplexing module includes a plurality of signal input terminals and a signal selection terminal, where each signal input terminal receives the first reference clock signal or the second reference clock signal, the signals received by the plurality of signal input terminals are not identical, and the signal selection terminal is configured to control the multiplexing module to select one of the first reference clock signal and the second reference clock signal to input the signal of at least one channel in the four-phase clock signal, so that the problems of complex structure and high power consumption of an existing multi-phase clock generation circuit can be solved.

In one implementation, the circuit further includes:

the digital code stored in each register is used for controlling the corresponding multiplexing module to select one from the first reference clock signal and the second reference clock signal and input the selected one to obtain a signal of at least one channel in the four-phase clock signals;

or the decoder is respectively connected with the multiplexers and is used for coding the mode control signal to obtain different codes, wherein the different codes are used for controlling a corresponding multiplexing module to select one of the first reference clock signal and the second reference clock signal and input the selected one to obtain a signal of at least one channel in the four-phase clock signals.

In one implementation, the plurality of multiplexing modules includes: the first-level multiplexing modules are used for selecting one of the first reference clock signal and the second reference clock signal to output to obtain a third reference clock signal or a fourth reference clock signal, and the second-level multiplexing modules are used for directly outputting or turning over the third reference clock signal or the fourth reference clock signal to output to obtain a signal of at least one channel in the four-phase clock signal.

Fig. 3 is a schematic structural diagram of a multiphase clock generation module of another multiphase clock generation circuit according to an embodiment of the present application. Another embodiment of the present application provides a multiphase clock generation circuit including: the clock source signal processing device comprises a frequency division module, a first clock signal processing module and a second clock signal processing module, wherein the signal input end of the frequency division module receives and is connected with a clock source signal and is used for carrying out frequency division on the clock source signal by two to generate a first reference clock signal and a second reference clock signal which are intersected with each other; a multi-phase clock generating module 320, connected to the output of the frequency dividing module, for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal having a predetermined phase difference relationship, wherein as shown in fig. 3, the multi-phase clock generating module 320 includes: 6 multiplexing modules and a decoder 327, wherein the 6 multiplexing modules include 2 first-

stage multiplexing modules

321, 322 and 4 second-

stage multiplexing modules

323, 324, 325 and 326, an input of the decoder 327 is connected to a control signal MODE _ SELECT <0>, and outputs a 6-bit control signal S <5> for controlling each multiplexing module to SELECT one of the first reference clock signal and the second reference clock signal to obtain a signal of at least one channel of the four-phase clock signals.

Specifically, the VIP _1/VIN _1 terminals of the differential input path 1 of the first-stage multiplexing module 321 are receiving the first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; the VIP _2/VIN _2 ends of the differential input path 2 are positively connected with a second reference clock signal Ref _ CLK2_ VIP/Ref _ CLK2_ VIN; s <0> is connected with the output signal S <0> of the decoder 327, and the phase of 1 or 2 paths can be selected for output; the differential output terminal VOP/VON outputs a third reference clock signal Ref _ CLK3 to the subsequent circuit, and the output phase is 0 ° or 90 °.

The VIP _1/VIN _1 terminals of the differential input path 1 of the first-stage multiplexing module 322 are positively connected to the second reference clock signal Ref _ CLK2_ VIP/Ref _ CLK2_ VIN; the VIP _2/VIN _2 ends of the differential input channel 2 are positively connected with a first reference clock signal Ref _ CLK1_ VIP/Ref _ CLK1_ VIN; s <0> is connected with the output signal S <1> of the decoder, and the phase of 1 or 2 paths can be selected for output; the differential output end VOP/VON is used as a differential signal to be connected with a post-stage circuit, and the output phase is also 90 degrees or 0 degrees.

The VIP _1/VIN _1 end of the differential input channel 1 of the second-stage multiplexing module 323 is positively connected with the output end VOP/VON of the first-stage multiplexing module 321; the VIP _2/VIN _2 end of the differential input path 2 is reversely connected with the output end VOP/VON of the first-stage multiplexing module 321; s <0> terminates the output signal S <2> of the decoder, can choose the phase place of 1 or 2 passways to export; the differential output end VOP/VON is used as the A channel differential output end of the circuit, and the output phase can be any phase of 0 degree, 90 degrees, 180 degrees or 270 degrees.

The VIP _1/VIN _1 end of the differential input channel 1 of the second-stage multiplexing module 324 is positively connected with the output end VOP/VON of the first-stage multiplexing module 322; the VIP _2/VIN _2 end of the differential input path 2 is reversely connected with the output end VOP/VON of the first-stage multiplexing module 322; s <0> terminates the output signal S <3> of the decoder, can choose the phase place of 1 or 2 passways to export; the differential output end VOP/VON is used as the B-channel differential output end of the circuit, and the output phase can be any phase of 0 degree, 90 degrees, 180 degrees or 270 degrees.

The VIP _1/VIN _1 end of the differential input channel 1 of the second-stage multiplexing module 325 is positively connected with the output end VOP/VON of the first-stage multiplexing module 321; the VIP _2/VIN _2 end of the differential input channel 2 is reversely connected with the output end VOP/VON of the first-stage multiplexing module 321; s <0> terminates the output signal S <4> of the decoder, can choose the phase place of 1 or 2 passways to export; the differential output end VOP/VON is used as the C channel differential output end of the circuit, and the output phase can be any phase of 0 degree, 90 degrees, 180 degrees or 270 degrees.

The VIP _1/VIN _1 end of the differential input channel 1 of the secondary multiplexing module 326 is positively connected with the output end VOP/VON of the primary multiplexing module 322; the VIP _2/VIN _2 end of the differential input path 2 is reversely connected with the output end VOP/VON of the first-stage multiplexing module 322; s <0> is connected with the output signal S <5> of the decoder, and the phase of 1 or 2 paths can be selected for output; the differential output end VOP/VON is used as the D channel differential output end of the circuit, and the output phase can be any phase of 0 degree, 90 degrees, 180 degrees or 270 degrees.

In summary, the circuit can generate four-phase output clocks with arbitrary phase combinations of 0 °, 90 °, 180 °, and 270 ° by appropriate control of the decoder 327.

In this embodiment, two-stage cascade of multiple multiplexing modules is adopted, the first-stage multiplexing module realizes one output from the first reference clock signal and the second reference clock signal, and the second-stage multiplexing module realizes direct output or flip output of signals on the basis of the first-stage multiplexing module, so that a four-phase output clock with any phase combination can be output, and thus, good circuit matching and good inter-channel matching degree can be realized.

The present application further provides a method for generating a multiphase clock, the method being applied to the multiphase clock generating circuit shown in fig. 1 to 3, comprising: dividing a clock source signal by two through a frequency dividing module to generate a first reference clock signal and a second reference clock signal which are intersected with each other, wherein a signal input end of the frequency dividing module receives the clock source signal; the first reference clock signal and the second reference clock signal are received by the multi-phase clock generating module, and four-phase clock signals with a preset phase difference relation are output, wherein the multi-phase clock generating module is connected with the frequency dividing module, so that the problems of complex structure and high power consumption of the conventional multi-phase clock generating circuit can be solved.

A multiphase clock generation method provided in the embodiments of the present application is described below with reference to the accompanying drawings by using specific embodiments and application scenarios thereof.

Fig. 4 illustrates a multiphase clock generation method according to an embodiment of the present application. The method may be applied to the multi-phase clock generation circuit described above with reference to fig. 1 to 3, or the method may be performed by each functional block in the multi-phase clock generation circuit described above. In other words, the method may be executed by software or hardware of each functional block installed in the multiphase clock generation circuit, the method including the steps of:

s401: the clock source signal is divided by two through the frequency dividing module to generate a first reference clock signal and a second reference clock signal which intersect with each other.

And the signal input end of the frequency division module receives the clock source signal.

S402: and receiving the first reference clock signal and the second reference clock signal through a multi-phase clock generation module, and outputting four-phase clock signals with a predetermined phase difference relation.

Wherein the multiphase clock generation module is connected with the frequency division module.

In one implementation, the step S402 includes: directly outputting or turning over the first reference clock signal by each multiplexing module in a plurality of multiplexing modules to obtain a signal of at least one channel in the four-phase clock signal; and/or, each multiplexing module in a plurality of multiplexing modules directly outputs or overturns the second reference clock signal to obtain a signal of at least one channel in the four-phase clock signal.

In one implementation, the step S402 includes: the first reference clock signal or the second reference clock signal is received through each signal input end, the multiplexing module is controlled to select one of the first reference clock signal and the second reference clock signal to be input through the signal selection end to obtain a signal of at least one channel in the four-phase clock signal, wherein each multiplexing module comprises a plurality of signal input ends and one signal selection end, and signals received by the signal input ends are not identical.

In one implementation, the step S401 includes: the frequency dividing module comprises a synchronous signal end, and the synchronous signal end receives a synchronous control signal, wherein the synchronous control signal is used for synchronously controlling the generation of the first reference clock signal and the second reference clock signal.

In one implementation, the step S402 includes: the multiphase clock generation module comprises a mode selection end, and the mode selection end receives a mode control signal, wherein the mode control signal is used for controlling and generating the four-phase clock signals in different modes, and the different modes correspond to different predetermined phase difference relations.

In one implementation, the step S402 includes: and controlling the corresponding multiplexing module to select one of the first reference clock signal and the second reference clock signal and input the selected one to obtain a signal of at least one channel in the four-phase clock signal through the plurality of registers respectively connected with the signal selection ends of the plurality of multiplexing modules, wherein each register stores different numbers for controlling the corresponding multiplexing module.

In one implementation, the step S402 includes: and the mode control signals are respectively connected with the multiplexers through decoders, and different codes are obtained by coding the mode control signals, wherein the different codes are used for controlling a corresponding multiplexing module to select one from the first reference clock signal and the second reference clock signal to input so as to obtain a signal of at least one channel in the four-phase clock signals.

In one implementation, the multiphase clock generation method transmits signals in a differential manner.

The specific implementation of the above steps can be seen from the description of the relevant functional modules of the multiphase clock generation circuit in fig. 1 to fig. 3, and the execution of the corresponding steps can achieve the same technical effect, and is not repeated here to avoid repetition.

According to the multiphase clock generation method provided by the embodiment of the application, a clock source signal is subjected to frequency division by a frequency division module, a first reference clock signal and a second reference clock signal which are intersected with each other are generated, wherein a signal input end of the frequency division module receives the clock source signal; the first reference clock signal and the second reference clock signal are received by the multi-phase clock generating module, and four-phase clock signals with a preset phase difference relation are output, wherein the multi-phase clock generating module is connected with the frequency dividing module, so that the problems of complex structure and high power consumption of the conventional multi-phase clock generating circuit can be solved.

It should be noted that, in the multi-phase clock generation method provided in the embodiments of the present application, the execution subject may be a multi-phase clock generation apparatus, or a control module in the multi-phase clock generation apparatus for executing the multi-phase clock generation method. In the embodiments of the present application, a multiphase clock generation apparatus executes a multiphase clock generation method as an example, and the multiphase clock generation apparatus provided in the embodiments of the present application is described.

Fig. 5 is a schematic structural diagram of a multiphase clock generation apparatus according to an embodiment of the present application. As shown in fig. 5, the multiphase clock generation apparatus 500 includes: a frequency dividing module 510, a signal input end of which receives a clock source signal, and is configured to divide the clock source signal by two to generate a first reference clock signal and a second reference clock signal that intersect with each other; and a multi-phase clock generating module 520, connected to the frequency dividing module, for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal having a predetermined phase difference relationship.

In one implementation, the multiphase clock generating apparatus 500 transmits signals in a differential manner.

In one implementation, the multi-phase clock generation module 520 includes: a plurality of multiplexing modules, wherein each multiplexing module is configured to directly output or flip-flop the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal; and/or each multiplexing module is used for directly outputting or overturning the second reference clock signal to obtain a signal of at least one channel in the four-phase clock signals.

The multiphase clock generating module 520 comprises a mode selecting terminal, which receives a mode control signal for controlling the generation of the four-phase clock signals in different modes, wherein the different modes correspond to different predetermined phase difference relationships.

In one implementation, the multi-phase clock generation module 520 further includes: and the buffer module is used for directly outputting the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal.

In one implementation, the frequency dividing module 510 includes a synchronization signal terminal, which receives a synchronization control signal for synchronously controlling the generation of the first reference clock signal and the second reference clock signal.

In one implementation, the multiphase clock generating apparatus 500 further comprises:

or the decoder is respectively connected with the multiplexers and is used for coding the mode control signal to obtain different codes, wherein the different codes are used for controlling the corresponding multiplexing module to select one of the first reference clock signal and the second reference clock signal to input to obtain a signal of at least one channel in the four-phase clock signal.

The multiphase clock generating device in the embodiment of the present application may be a device, or may also be a component, an integrated circuit, or a chip in a terminal, and the embodiment of the present application is not particularly limited.

The multiphase clock generating device in the embodiment of the present application may be a device having an operating system, and may also be other possible operating systems, and the embodiment of the present application is not particularly limited.

The multiphase clock generation device provided in the embodiment of the present application can implement the functions of each corresponding module in the multiphase clock generation circuit in fig. 1 to 3, or implement each process implemented in the multiphase clock generation method embodiment in fig. 4, and is not described here again to avoid repetition.

Optionally, as shown in fig. 6, an electronic device 600 further provided in the embodiments of the present application includes a processor 601, a memory 602, and a program or instructions stored on the memory 602 and executable on the processor 601, where the program or instructions when executed by the processor 601 implement: dividing a clock source signal by two through a frequency division module to generate a first reference clock signal and a second reference clock signal which are intersected with each other, wherein a signal input end of the frequency division module receives the clock source signal; and receiving the first reference clock signal and the second reference clock signal through a multi-phase clock generation module and outputting a four-phase clock signal with a predetermined phase difference relation, wherein the multi-phase clock generation module is connected with the frequency division module.

It should be noted that the embodiment of the electronic device in this specification and the embodiment of the multi-phase clock generation circuit in this specification are based on the same inventive concept, and therefore, specific implementation of this embodiment may refer to implementation of the corresponding multi-phase clock generation circuit, and repeated details are not repeated.

The embodiments of the present application further provide a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the foregoing multi-phase clock generation method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and so on.

The embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is configured to run a program or an instruction to implement each process of the embodiment of the multiphase clock generation method or to implement the functions of each module of the embodiment of the multiphase clock generation circuit or the multiphase clock generation device, and the same technical effects can be achieved, and are not described herein again to avoid repetition.

It should be understood that the chips mentioned in the embodiments of the present application may also be referred to as system-on-chip, system-on-chip or system-on-chip, etc.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, an electronic device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of a computer-readable medium.

Computer-readable media, including both permanent and non-permanent, removable and non-removable media, may implement the information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrases "comprising a," "8230," "8230," or "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus comprising the element.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A multiphase clock generation circuit, comprising:

the clock source processing device comprises a frequency division module, a first frequency division module and a second frequency division module, wherein a signal input end of the frequency division module receives a clock source signal and is used for carrying out frequency division on the clock source signal by two to generate a first reference clock signal and a second reference clock signal which are intersected with each other;

and the multi-phase clock generation module is connected with the frequency division module and used for receiving the first reference clock signal and the second reference clock signal and outputting a four-phase clock signal with a predetermined phase difference relation.

2. The circuit of claim 1, wherein the multi-phase clock generation module comprises:

a plurality of multiplexing modules, wherein each multiplexing module is configured to directly output or flip-flop the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal; and/or each multiplexing module is used for directly outputting or overturning the second reference clock signal to obtain a signal of at least one channel in the four-phase clock signals.

3. The circuit of claim 1, wherein the multi-phase clock generation module further comprises:

and the buffer module is used for directly outputting the first reference clock signal to obtain a signal of at least one channel in the four-phase clock signal.

4. The circuit of claim 2, wherein each of the multiplexing modules comprises a plurality of signal input terminals and a signal selection terminal, wherein each of the signal input terminals receives the first reference clock signal or the second reference clock signal, the signals received by the plurality of signal input terminals are not identical, and the signal selection terminal is configured to control the multiplexing module to select one of the first reference clock signal and the second reference clock signal to obtain the signal of at least one channel of the four-phase clock signals.

5. The circuit of claim 1, wherein the frequency-division block comprises a synchronization signal terminal that receives a synchronization control signal for synchronously controlling the generation of the first reference clock signal and the second reference clock signal.

6. The circuit of claim 1, wherein the multi-phase clock generation module comprises a mode selection terminal, the mode selection terminal receiving a mode control signal for controlling generation of the four-phase clock signals in different modes, wherein the different modes correspond to different predetermined phase difference relationships.

7. The circuit of claim 4 or 6, further comprising:

8. The circuit of claim 1, wherein the circuit transmits signals differentially.

9. A multiphase clock generation method applied to the multiphase clock generation circuit according to any one of claims 1 to 8, the method comprising:

dividing a clock source signal by two through a frequency dividing module to generate a first reference clock signal and a second reference clock signal which are intersected with each other, wherein a signal input end of the frequency dividing module receives the clock source signal;

and receiving the first reference clock signal and the second reference clock signal through a multi-phase clock generation module and outputting a four-phase clock signal with a predetermined phase difference relation, wherein the multi-phase clock generation module is connected with the frequency division module.

10. The method of claim 9, wherein receiving the first reference clock signal and the second reference clock signal by a multi-phase clock generation module and outputting a four-phase clock signal having a predetermined phase difference relationship comprises:

directly outputting or turning over the first reference clock signal by each multiplexing module in a plurality of multiplexing modules to obtain a signal of at least one channel in the four-phase clock signal; and/or directly outputting or overturning the second reference clock signal through each multiplexing module in a plurality of multiplexing modules to obtain a signal of at least one channel in the four-phase clock signal.