JPS62264724A - Unit binary counter, synchronous binary counter and frequency divider to which the unit binary counter is applied - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a synchronous binary counter and a frequency synthesizer which can be produced on the basis of the synchronous binary counter. The frequency synthesizer divides the clock frequency of the synthesizer itself and uses only the highest number and winning outputs of a synchronous binary counter.

The binary counter of the present invention can be used in various ways, for example, in the form of a discrete element or in the form of an integrated circuit using bipolar transistors or field effect transistors. However, the main potential application is in the field of microwaves. In this case, the binary counter of the present invention is used in the form of an integrated circuit formed in a fast-acting material such as GaAs or other Group IV compounds.

Conventional technology Many methods of making binary counters are already known.

Among these, the simplest and easiest to use is a binary counter with a cascaded divider-by-2 divider. However, as the number of stages of the frequency divider increases, the final stage is required to be extremely stable. This is because the period becomes longer and longer with the number of stages. However, the conventionally used static fridip 70 tube is not necessarily stable enough.

Means for Solving the Problems The synchronous binary counter of the present invention uses not only static flip-flops, but also dynamic flip-flops, which are faster, consume less energy, and require fewer elements. Can be used. this is,
This is a major advantage in manufacturing integrated circuits. but,
A first advantage of the synchronous binary counter of the present invention is that it operates with a single high frequency clock signal. Therefore,
Improved stability. More specifically, the two clock signals that operate the synchronous binary counter of the present invention are two mutually complementary signals based on a single clock signal. Since the two signals are from a single clock signal, there is no relative shift between the two signals.

The synchronous binary counter of the present invention includes a plurality of mutually equivalent stages connected in cascade. Each stage comprises a unitary binary counter consisting of a half-adder and a master-slave flip-flop connected to the "sum" output of the half-adder. One input of the half adder is the input of a unitary binary counter.

The other input of the half adder is connected to the output of the slave flip-flop. The output of this slave flip-flop also serves as the output of the unit binary counter. The "carry" output of the half adder is the input to the next stage of the present synchronous binary counter.

More specifically, in accordance with the present invention, there is provided a two-input, single-output unitary binary counter comprising a half-adder and a master-slave flip-flop outputting a "sum" signal and a "carry" signal, comprising: The first input of the half-adder constitutes the input of a unitary binary counter, - the "sum" output of the half-adder is connected to the input of the master flip-flop, - the "carry" output of the half-adder is If several counters are connected in cascade, it outputs a signal that becomes the input signal of another counter, - the output of the slave flip-flop constitutes the binary output of the unitary binary counter, and the half adder - the master flip-flop and the slave flip-flop are further controlled by a single clock signal, the waveform of the clock signal input to the master flip-flop and the clock input to the slave flip-flop A unit binary counter is provided in which signal waveforms are inverted with respect to each other.

Embodiment FIG. 1 is a basic block diagram of a binary counter of the present invention. Although only three stages are drawn for the sake of clarity, it is clear that the invention is not limited thereby. By the way, the number N of stages is determined in relation to the number 2N to be counted.

In this counter, each stage consists of a unit counter constructed of a half-adder A+ and a master-slave flip-flop MI-E operated by mutually complementary signals from a single clock. Signal H2 is a control signal for the master flip-flop, and signal HE=H is a control signal for the slave flip-flop.

Half adder is AND with EXCLUSIVE-OR gate
This configuration has gates connected in parallel. The signals B and C to be added are input to two inputs of an EXCLUSIVE-OR gate and two inputs of an AND gate. EXCL
The output S of the US I VE-OR gate is the sum and
The output R of the gate is a carry.

Thus, each unit counter comprises a half adder Ai.

The "sum" which is the output S of 〇 to this half adder is copied to the mask slave flip-flop 7'' MI El.

Output Q8 of master-slave flip-flop M, -E,
is connected to the input CI of the half adder Δi to form a feedback loop.

The other input B of half adder A1 is the input to this unit counter or stage. The output Q of the slave flip-flop E is the output from this stage. The carry output R1 becomes an input to the next stage connected in a cascade manner.

When the circuit diagrammed in FIG. 1 is used as a binary counter, all outputs Q1, Q2, Q3 are used. When this circuit is used as a frequency divider, only the ## stage output Q3 is used.

The truth table for the half adder is as follows.

The master-slave flip-flop is a sum signal S.

and reproduce this sum signal at the output Q+ in the next clock cycle. The following relational expression holds true while the slave flip-flop is reading.

- When Ql=C in the first stage.

S + = B I (53C + = B + ■Q, (
EXCLtlSIVE-OR)R+ = 81・C+=
8+-Ql=82 (AND)-02 on second death = C
In case of 2.

52=B2eC2=R+'EjQz R2= B 2・C2=R,・Q 2 = B 3−
In the case of 03=c in the third stage.

53=B3eC3=R2■Q3 R3=B3・C3=R2・Q3 The next clock cycle will result in a new value at the output.

Ql" copies Sl.

Q2' copies S2.

Q3' copies S3.

In order to obtain a new value, Q of the previous relational expression, ,Q2゜Q
It is only necessary to replace 3 with Ql'', Q2', and Q3'.

S1°" B + eS + R% = B + 31 This is because Q becomes Q+'=S+.

S 2' = R + ° (9S2 R2' = R, '・S2 Because R1 becomes F2, l, Q2 becomes Q2' = 32
This is because it became.

83'=R2゛■83 R,'=R2''・S3 For the same reason as above.

Two cases are possible.

When B+=logic value 0, the following relationship is obtained according to the truth table of the half adder.

Sz' = St 32' = S2 S
3'=33R,'=OR2''=OR3'=0 Since all inputs B+ and R1 are at logic 0, the counter remains in exactly the same state as before.

If B, = logical value 1, the following relationship is obtained.

S1°"St R+'=S+ S2'=R,'■32=Sl■32 R2'=R1"・S2=S+・S2Others are the same.

Since the value changes in the first stage, the value on the counter increases by one.

The increase in the value of the counter is clearly seen from the table below for the three-stage counter. B, = logical value 1, and initially Q
, =Q2=Q, =O, then Sl, R5, B2, R2
, B3, and R1 can be calculated based on the truth table of the half adder. In the next cycle, Q, copies Sl, Q2 copies 82, and Q3 copies 83.

Therefore, R1, R2, and R3 are calculated, and the same is performed for each cycle.

If B1 is a logical 0, the counter remains unchanged, holding its last value.

In this table, the inputs and outputs of a unit counter or stage are shown enclosed in a rectangle. The arrow indicates that in one cycle, the output Q1 is the output S of the previous cycle.
Indicates that it is a copy of 1.

The counter reading appears at the outputs Q, , Q, , Qt of the mask slave free-knob flops. For example, in the sixth cycle, Q I = 0 weight 0, coefficient 0 Q2 = 1 weight 1, coefficient 1 Q, = 1 weight 2, coefficient 1 are obtained. As a result, the numerical value N=0.2°+1.21+1.22=6 is obtained.

The counter of the present invention, in which N stages of unit counters are connected in a cascade manner, can count up to 2N.

This counter also has the advantage of receiving a synchronization signal consisting of the "carry" output R, of the final stage. The output of this counter is never output to the next stage. This will be explained in detail with reference to FIG. 2 and subsequent figures. Synchronization is important to achieve an automatic zero-reset and programmable frequency divider.

Any suitable half adder and masked slave flip-flop may be used to construct the inventive counter that operates as described above. However, Figures 2 and 3 are
Two diagrams showing particularly preferred applications where the transistor is a two-dimensional electron gas transistor and the load resistor is a saturated load or gateless transistor.

FIG. 2 is an electrical diagram of a half adder with two inputs B and C and two outputs, a "sum" output S and a "carry" output R.

This half adder has a configuration in which eight transistors are connected in parallel. If the transistor is a field effect transistor, the source is connected to ground and the drain is connected to a voltage through a load resistor. .

is applied.

The AND function is realized by two inverters 1.2 and an OR inverter or NOR gate. Signal B is input to the gate of inverter 1.

An inverted signal B is output from the drain of the inverter 1 and input to the gate of the transistor 3 forming a NOR gate. Signal C is input to the gate of inverter 2. An inverted signal C is outputted from the drain of this inverter 2 and inputted to the gate of a transistor 4 forming a NOR gate. Therefore, the output signal of the NOR gate is B+C=B−C (AND function). This output signal becomes the output R of the half adder.

The EXCLUS IVE-OR function is implemented using two OR imparks, ie, two NOR gates.

Signals B and C are input to the gates of two transistors 5 and 6, respectively, forming the first NOR gate. The output of the first NOR gate is therefore B+C.

Finally, the signal B+C obtained from the AND function part and the first
The signals B+C obtained from the NOR gate of
The signal is input to the gates of two transistors 7 and 8 forming the second NOR gate. The “sum” signal is the second NO, R
The “carry” signal is output from the drain of the gate, and the AN
It is output from the D function part. Therefore, S= B-'-, C+ B+C= (B'', C)
- It is clearly seen that (B+C)(IEXCLUSIVE-OR) R= B+C=B-C(AND).

FIG. 3 is an electrical circuit diagram of a master-slave flip-flop to which a forced R/S (reset-set) input synchronized with clock H9 is input.

The master flip-flop has a configuration in which dual gate transistors 11 and 12 are connected in parallel.

The sources of both transistors are connected to ground and the drains are connected to each other.

The source-side gate of the transistor 11 serves as the input S of the master-slave flip-flop, and is connected to the output S of the half adder shown in FIG. The gate on the drain side of the transistor 11 is connected to two transistors 15 and 16.
It is controlled by the output signal of an OR inverter configured as follows. The gate of one transistor 16 of the OR inverter is controlled by the clock signal Hx, while the gate of the other transistor 15 is controlled by the synchronization signal SYN. This synchronization signal is a carry signal R9 from the first stage of the counter (see FIG. 4) M11J. The gate on the drain side of transistor 11 is therefore controlled by a signal HM + S Y N of the form:

The gate on the source side of transistor 12 is an R/S forced input. The gate on the drain side of transistor 12 is controlled by the output signal of an OR inverter made up of two transistors 17 and 18. By the way, the gate of the transistor 17 is controlled by the clock signal HH, whereas the gate of the transistor 18 is controlled by the synchronization signal SYN inputted via the inverter 19. The gate on the drain side of transistor 12 is therefore controlled by a signal of the form Hit+qYd, i.e., H.sub.SYN.

From the above, it can be seen that the conduction of transistors 11 and 12 occurs alternately.

The slave flip-flop consists of a dual gate transistor 13. The source of this transistor 13 is connected to ground, and the drain is connected to the output Q of the master-slave flip-flop. In the diagram of FIG. 1, the output Q is connected as a feedback loop to the input C of the half adder in each stage.

The source side gate of transistor 13 receives the output signal of the master flip-flop, that is, transistors 11 and 12.
is controlled by a signal from the drain of the

The gate on the drain side of transistor 13 is controlled by clock signal H6. This clock signal H2 is converted into a clock signal H by an inverter using a transistor 14.
M is the inverted signal.

Both in the case of master-slave flip-flops and in the case of half-adders, all transistors have a voltage
. It can be clearly seen that 0 or 0 is applied successfully.

However, there is no point in going into further detail about bias. This is because using bipolar transistors rather than field effect transistors changes the bias.

FIG. 4 is a diagram of a synchronous binary counter or frequency divider.

Converting from one to the other requires only minor changes. This point will be explained later. This fourth
The diagram is more detailed than Figure 1. However, similar to FIG. 1, the counter includes multiple stages in cascade. In each stage the half adder A1 has two inputs B+ and C
4 and two outputs, “sum” output S1 and “carry”
It has an output R1. Each master-slave flip-flop has one R/S forced input S1, one output Q,
and three control inputs H,, HE (=HM), S
Has YN. Within one membrane, the output S of the half-adder becomes the input of a master-slave flip-flop whose output Q is connected to the input C of the half-adder to form a feedback loop. Between the two stages, the output RM-1 of the upstream winning combination is connected in cascade to the input B8 of the next stage. Control signal H)!
, HE, and SYN are connected together for each control signal.

When the above circuit operates as a synchronous binary counter,
Input B1 is the count value input to this circuit. In this case, forced input R/S,..., R/SN
is connected to ground, and furthermore, the output R8 of the final stage is not used. The output of this counter is the output Q1 of each stage.
..., QH. This counter is reset to zero each time the synchronization signal has a logic value of "1".

When this circuit is used as a programmable frequency divider, input B; is fixed at a logic value of 1.

In this case, the forced inputs R/S, . . . , R/SN are enabled, so unlike when used as a counter, they are not connected to ground. Furthermore, the output Rw of the final stage
is connected to the synchronization input SYH as shown by the dotted line in FIG. This circuit divides the frequency of its own clock and outputs it from the only output terminals Q and I.

If we refer again to the table showing the increase in the numerical value in the counter shown above and consider the seventh cycle with R3=1 (considering, of course, a three-stage counter), we can see that there are two cases.

-R/S,=R/S2 If =R/S,=0, there is no forced input to the master flip-flop, so the above table becomes as follows.

Since the 8th cycle is the same as the 0th cycle, this frequency divider performs frequency division by 8.

−R/S,=1. If R/32 = R/33 = O,
Since a forced input is input to the master flip-flop M1, the above table becomes as follows.

Since the eighth cycle is the same as the first cycle, the frequency divider has a period of 7 and performs frequency division by 7.

Further, if N is the number of stages of the frequency divider and P is the binary number (0 or 1) of the forced input R/S, then the frequency divider of the present invention divides by (2''-P). Do laps.

This type of counter is versatile and operates over a wide frequency range. However, with integration in mind, we have specifically explained the application of this counter to high-speed data processing.

[Brief explanation of drawings]

FIG. 1 is a basic block diagram of the counter of the present invention, FIG. 2 is an electrical circuit diagram of a half adder used in the counter of the present invention, and FIG. 3 is a master circuit diagram of a half adder used in the counter of the present invention. FIG. 4 is an electrical circuit diagram of a slave flip-flop, and FIG. 4 is a block diagram of a synchronous counter of the present invention. (Main reference numbers) A 1. A2. A3. ..., AM...
Half adder, M+, M2. M*,...1
M9...Master flip-flop, E,, E2. E3. ..., E9 ... slave flip 70 knob,

Claims (6)

[Claims] (1) A two-input, single-output unitary binary counter comprising a half-adder and a master-slave flip-flop outputting a "sum" signal and a "carry" signal, comprising - a second half-adder; 1 input constitutes the input of the unitary binary counter, - the "sum" output of the half adder is connected to the input of the master flip-flop, - the "carry" output of the half adder constitutes the input of the unit binary counter, - the "carry" output of the half adder - the output of the slave flip-flop constitutes the binary output of the unitary binary counter, and the second input of the half-adder - the master flip-flop and the slave flip-flop are further controlled by a single clock signal, such that the waveform of the clock signal input to the master flip-flop and the waveform of the clock signal input to the slave flip-flop are inverted with respect to each other; A unit binary counter characterized by having a waveform. (2) a two-input, single-output unitary binary counter comprising a half-adder and a master-slave flip-flop outputting a "sum" signal and a "carry" signal, comprising - a second half-adder; 1 input constitutes the input of a unitary binary counter, - the "sum" output of the half-adder is connected to the input of the master flip-flop, - the "carry" output of the half-adder constitutes the input of the unit binary counter, - the "carry" output of the half-adder - the output of the slave flip-flop constitutes the binary output of the unitary binary counter, and the second input of the half-adder - the master flip-flop and the slave flip-flop are further controlled by a single clock signal, such that the waveform of the clock signal input to the master flip-flop and the waveform of the clock signal input to the slave flip-flop are inverted with respect to each other; A synchronous binary counter comprising a plurality of unit binary counters characterized by a waveform, in which the "carry" output of a half adder is the first half adder of the next half adder connected in a cascaded manner. 1, and the synchronous type 2
A synchronous binary counter characterized in that the binary output of the binary counter consists of the output of each unit binary counter. (3) In each unit binary counter, the master flip-flop has two inputs into which a clock signal and a synchronization signal are respectively input synchronously, and the "sum" output of the half adder of the unit binary counter. 3. A synchronous binary counter according to claim 2, comprising a first input that is connected and a second input that is a forced input of a master flip-flop. (4) The synchronous binary counter according to claim 3, wherein a logic value "1" is input to the synchronization signal input to perform zero reset. (5) a two-input, single-output unitary binary counter comprising a half-adder and a master-slave flip-flop outputting a "sum" signal and a "carry" signal, comprising - a second half-adder; 1 input constitutes the input of the unitary binary counter, - the "sum" output of the half adder is connected to the input of the master flip-flop, - the "carry" output of the half adder constitutes the input of the unit binary counter, - the "carry" output of the half adder - the output of the slave flip-flop constitutes the binary output of the unitary binary counter, and the second input of the half-adder - the master flip-flop and the slave flip-flop are further controlled by a single clock signal, such that the waveform of the clock signal input to the master flip-flop and the waveform of the clock signal input to the slave flip-flop are inverted with respect to each other; It has a plurality of unit binary counters characterized by waveforms, the "carry" output of the half adder is connected to the first input of the next stage half adder connected in cascade, and each In a unit binary counter, the master flip-flop is
two inputs into which a clock signal and a synchronization signal are input synchronously, a first input connected to the "sum" output of the half adder of the unitary binary counter, and a forced input of the master flip-flop. a programmable frequency divider with a second input, the inputs of all unitary binary counters being maintained at a logical value of 1, and the "carry" output of the final unitary binary counter being Connected to the signal input, the output signal of the unit binary counter at the final stage of the frequency divider is a value programmed based on the binary number input to the forced input of the frequency of the frequency divider's own clock. A frequency divider characterized by being compatible with a signal divided by . (6) Let the number of unit binary counters be N, and the forced input binary number be P (logical value "0" or logical value "1"),
6. A frequency divider according to claim 5, wherein the frequency is divided by (2^N-P).