WO2000001071A1

WO2000001071A1 - Static frequency divider with modifiable divider ratio

Info

Publication number: WO2000001071A1
Application number: PCT/DE1999/001714
Authority: WO
Inventors: Michael Pierschel
Original assignee: Infineon Technologies Ag
Priority date: 1998-06-29
Filing date: 1999-06-11
Publication date: 2000-01-06
Also published as: EP1095456A1; JP2002519923A

Abstract

The invention relates to a static frequency divider with a modifiable divider ratio for maximum frequencies and with a minimal overall power consumption. In a first divider stage, a T-flip-flop is provided with modified D-flip-flops which have an additional input transistor pair. If at any chosen time, the operating current of said input transistor pair is switched, exactly one input clock pulse period is suppressed and the divider ratio is modified. Almost any modifiable divider ratios can be produced with other divider flip-flops and a plurality of modifying operations.

Description

description

Static frequency divider with switchable divider ratio.

The invention relates to a static frequency divider which contains at least two synchronously clocked holding elements or two flip-flop circuits, which alternately switch on and off. The holding elements usually have a preparatory stage and a stage that holds the signal (master and slave). The individual stages are usually designed as differential stages, since, due to the parasitic capacitances, relatively low signal levels occur at high and very high frequencies, and due to the differential stages there is a significantly greater interference immunity. The working point current is between the preparatory one

Stage (master) and the stage holding the signal (slave) are switched, with a pair of transistors of each stage always carrying the usually constant operating point current and thus the operating point current of the holding elements is uniform during both clock phases. At least two such holding elements or D flip-flops are required for a static frequency divider. The operating point current must be large enough to generate a corresponding signal voltage swing on the load elements and to reload the parasitic capacitances which are always present and are connected to ground with the required signal voltage swing. A 2: 1 frequency divider can be interconnected in a manner known per se from two such holding elements in the form of a master-slave flip-flop, the clock control being designed such that either the master holding element or the slave holding element is activated and the outputs of the master holding element are connected to the inputs of the slave holding element. A U-switching flip-flop or a so-called T-flip-flop is produced by feedback of the outputs of the master-slave flip-flop in phase opposition to the inputs of the master-slave flip-flop. A binary static frequency divider with a divider ratio greater than 2: 1, for example, has a series connection of several ter flip-flops. If an odd-numbered division factor or a division factor deviating from a binary sequence is required, this can be achieved, for example, with appropriate logic which either resets the inputs or the holding elements before the next plate cycle. However, such logic circuits are not easy to implement, since the signal levels used are only in the range from 200 mV to 500 mV and a corresponding level increase must be carried out. The corresponding drivers and logic are operated at high frequencies and cause correspondingly high power losses. In addition, the use of logic gates is always associated with a delay time, which determines the so-called critical path. These additional delays due to the logic usually lower the achievable maximum divider frequency considerably, which is essentially due to the fact that the binary divider may only switch on after the logic decision regarding the acute state of the outputs has been made correctly and the corresponding signals have been reset.

The object on which the invention is based is to provide a static frequency divider with switchable divider ratios, in which no additional level drivers or logic circuits with a correspondingly high power loss are required.

This object is achieved according to the invention by the features of patent claim 1. Preferred developments of the invention result from the further claims.

The invention is explained in more detail below with reference to a preferred exemplary embodiment shown in the drawings. It shows

FIG. 1 shows a block diagram of a 2: 1/3: 1 divider according to the invention, Figure 2 is a circuit diagram of the modified master-slave flip-flops of Figures 1 and

3 shows a timing diagram to explain the mode of operation of the circuits shown in FIGS. 1 and 2.

In the invention it is essentially brought about that modified D-flip-flops are present through additional input transistor pairs and switching transistors and a switchover takes place between two, so to speak, interlocking divider rings, the two part sets only being exchanged by a direct and a crosswise connection between the respective ones Distinguish the outputs of a first D flip-flop with the inputs of the second D flip-flop. This switchover between the two divider rings suppresses an input clock period or extends the output clock period. Since the switchover time is typically much shorter than the period of the input clock with which both holding elements are clocked synchronously, the switchover from one divider ring to the other suppresses exactly one period of the input clock. Since the additional transistors in the modified master-slave flip-flop require the same operating currents, the static frequency divider, despite a switchable divider ratio, requires the same power loss as a static frequency divider with a correspondingly large fixed divider ratio. A critical path does not exist, since no logic in the speed-determining divider ring can lead to time delays. Such a circuit according to the invention can in principle be operated up to the highest frequencies that can be achieved with the respective technology. To do this, however, the individual edges on the control inputs must be as steep as possible in order to achieve the very short changeover time required for the operating current.

In Figure 1, two D flip-flops 1 and 2 m of a master-slave arrangement as a T flip-flop and as a switch flip-flop switched, with a regular, a signal C leading output Q of the flip-flop 1 with a regular input Dl of the flip-flop 2 and an inverted, a signal D leading output QN with an inverted input D1N of the flip-flop 2, that is, corresponding Outputs are connected to corresponding inputs, and wherein a regular output Q of the flip-flop 2 carrying a signal A via a signal crossing XI with an inverting input D1N of the flip-flop 1 and an inverting output B leading to a signal B of the flip-flop 1 Flops 2 is connected via a signal crossing XI to a regular input D1 of the flip-flop 1. In addition, on the basis of the modified D flip-flops 1 and 2, a second part is realized in that the output Q of the flip-flop 1 with the inverting input D2N and the output QN of the flip-flop are connected via a signal crossing X3 1 is connected to the regular input D2 of the flip-flop 2 and that the output Q of the flip-flop 2 via the signal crossings XI and X2 provided here with the input D2 of the flip-flop 1 and the output QN2 of the flip-flop 2 also are directly connected to input D2N via signal crossings XI and X2. In this context, a direct connection means that a non-inverted output is connected to a corresponding non-inverted input and an inverted output is connected to a corresponding inverted input. Correspondingly, a crosswise connection here means that a non-inverted output is connected to an inverted input and an inverted output is connected to a corresponding non-inverted input. In addition to a supply voltage VDD and GND, both flip-flops 1 and 2 are switched on at their clock outputs CLK and CLKN

Input clock signal T fed. The flip-flops 1 and 2 each have a regular and an inverted control input ST and STN, which are each connected to a control unit 3. The control unit 3 generates changeover signals for the inputs ST and STN depending on a selection signal M for the divider ratio, as a result of which the inputs are selected for a respective divider ring. In the simplest case, only the two flip-flops 1 and 2 are provided, but further divider stages can be connected in order to obtain higher divider ratios. To form the signals for the inputs ST and STN, the control unit 3 can be supplied with the input clock T and also output signals E and F from these further stages.

In Figure 2, a detailed circuit diagram for the modified D flip-flops 1 and 2 is shown, the modification consisting primarily in that in addition to a first pair of input transistors T3 and T4, a second pair of input transistors T9 and T10 is provided, with a common connection of the Transistors T3 and T4 can be connected to a node Kl via a switching transistor T7, the gate of which is connected to the input ST, and first connections of the transistors T9 and T10 can be connected via a further switching transistor T8, the gate of which is connected to the input STN, are also connectable to the node Kl. The gate of transistor T3 is connected to the first inverting input DIN, the gate of transistor T4 to input D1, the gate of transistor T9 to input D2N and the gate of transistor T10 to input D2. The second connections of the transistors T3 and T9 are with the output Q and the second connections of the transistors T4 and T10 with the inverted one

QN output connected. A transistor T5 is connected with a first connection to a node K2 and with a second connection via a load resistor RL1 to VDD. A transistor T6, which forms a pair of transistors with transistor T5, is connected at a first connection to node K2 and via a load resistor RL2 to VDD. The connection point between the transistor T5 and the resistor RL1 represents the output Q, which is fed back to the gate of the transistor T6. Correspondingly, the connection point between the transistor T6 and the load resistor RL2 represents the inverting output QN, which is fed back to the gate of the transistor T5. Coupled crosswise by the two Transistors T5 and T6 result in a bistable multivibrator. The node K1 can be connected via a switching transistor T1 and the node K2 can be connected via a switching transistor T1 via a common resistor R1 with reference potential GND, the gate of the transistor T1 being connected to the regular clock input CLK and the gate of the transistor T2 being connected to the inverted clock input CLKN is.

3 shows the signals T, A ... D in the upper part of this figure for the case without a signal change at the control inputs ST and STN and in the lower part of the figure for the case of a signal change at the control inputs ST and STN . Drawn arrows show the takeover of signals C and D as signals A and B and the dotted characters show the takeover of signals A and B as signals C and D. The input clock T has a period duration PO and signals A. .. D a period Pl = 2 * P0 and thus a divider ratio 2: 1, provided there is no signal change at the control inputs ST or STN. A corresponding signal change at the inputs ST and STN suppresses a 2: 1 division for the time period PO and a switchover of the smale C and D, which means that a period change of P2 = 3 * due to a signal change at the inputs ST and STN P0, i.e. a 3: 1 division ratio, arises.

To generate higher plate ratios such a switchable frequency divider z. B. further conventional divider flip-flops can be connected downstream.

Furthermore, the control unit 3 can be provided in such a way that in one case there is no switchover and the output period Pl = n * P0 and in the other case there are m switchovers, so that an output period of P2 = (n + m) * P0 and thus an n : l / (n + m): 1-frequency divider arises. Finally, there is also the possibility that, depending on the selection signal M, either k switches or m switches take place during n periods PO, k of course not equal to m. In a corresponding manner, this leads to an (n + k): l / (n + m): 1 frequency divider.

Claims

claims

1. Static frequency divider with switchable divider behavior

in which, in a first divider ring, the outputs (Q, QN) of a first holding member (1) with the corresponding inputs (Dl, DIN) of a second holding member (1) directly and the outputs of the second holding member crosswise (XI) with the corresponding ones Inputs of the first holding member are connected, in which in a second divider ring, instead of the crosswise connection (XI) there is a direct connection (XI, X2) and vice versa (X3), in which there is a control device (3) which is dependent on one Selection signal (M) for a desired divider ratio causes a switchover between the first and second divider ring.

2. Static frequency divider according to claim 1, in which the first and second holding elements in addition to a first input transistor pair (T3,

T4) has an additional pair of input transistors (T9, T10) belonging to the second divider ring, in which, depending on the selection signal (M), with the aid of

Selection transistors (T7, T8) either the first pair of input transistors or the second pair of input transistors can be activated and in which the first and second holding elements contain further circuit parts which are part of both divider rings.

3. Static frequency divider according to claim 2, wherein the further circuit parts include a first transistor (Tl) and a second transistor (T2), which depending on the received clock signal (T) either a first node (Kl) or a second node (K2) Connect to the reference potential (GND) via a resistor (R1), in which the other circuit parts have a bistable multivibrator (T5, T6, RL1,) connected to the outputs of the holding element. RL2) include, which is connected to the second node (K2), and in which either the first or second pair of input transistors can be activated in that either the first or the second pair of input transistors via a respective selection transistor depending on a control signal (ST, STN) the first node (Kl) is connectable.

4. Static frequency divider according to one of the preceding claims, in which a control unit (3) is present which within n periods of an input clock (PO) of the static frequency divider depending on the selection signal (M) for a desired division ratio either k times or n times toggles, where k is not equal to m and where k and m are integer values between 0 and n.

5. Static frequency divider according to Claim 4, in which further divider stages are connected downstream of the first or second divider ring and output signals (E, F) of these further divider stages are fed to the control unit (3).