JPS622719A - Test circuit for dividing counter - Google Patents

Abstract

PURPOSE:To shorten the test time of a dividing counter by decreasing the number of input clock pulses. CONSTITUTION:In a test mode of a dividing counter, the output of a delay circuit 7 is supplied to a flip-flop 4 through a selector circuit 8. An input signal 21 of an input terminal 1 is divided into half by a flip-flop 2 and turned into a signal 22. The signal 22 is divided into half by a flip-flop 3 and turned into a signal 23. While the signal 21 is turned into a signal 24 through the circuit 7 and then divided into half by a flip-flop 4 to be turned into a signal 25. Then the signal 25 is divided into half by a flip-flop 5 and turned into a signal 26. The output signal 23 of a flip-flop 3 and the output 26 of the flip-flop 5 are supplied to an exclusive OR circuit 10. The output of the circuit 10 is turned into a signal 27 and delivered to a test output terminal 1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a frequency division test circuit.

[Conventional technology]

Conventionally, in the test of an n-divider cuff/resistance circuit in which m seven rig flops are connected in series, n clock pulses are input and the output waveform corresponding to the clock pulses is observed. (n, m
is a natural number, 2m=n) This example will be explained below with reference to the block diagram of the divide-by-16 counter in FIG. 4 and the time chart in FIG.

The clock signal 41 inputted to the input side child 31 is frequency-divided by 172 in the flip-flop 32 to become a signal 42, and further divided by 1/2 in the flip-flop 33 to become a signal 43. Similarly, the frequency is divided by 1/2 by 7 lip-flops 34.35 to obtain a signal 44.45, and a signal 45 frequency-divided by 16 is outputted to the output terminal 36.

That is, in testing the frequency division by 16 counter, 16 clock pulses were input and all waveforms divided by 16 were observed.

[Problem that the invention seeks to solve]

In the test of the conventional divide-by-n counter described above, as n becomes larger, n input clock pulses are required, and
The disadvantage is that the test time is long.

[Means for solving problems]

According to the invention of Wooden Tablet 1, a selector circuit that divides a flip-flop constituting a frequency division counter into multiple stages, a delay circuit that delays an input signal of the frequency division counter and guides it to the selector circuit, and a delay circuit on the input side of the selector circuit. A frequency division counter test circuit is obtained which includes a logic circuit that performs a logical operation on a flip-flop output signal and an output signal of the frequency division counter.

According to the invention of Wooden Tablet 2, a selector circuit that divides a flop-flop constituting a frequency division counter into multiple stages, a delay circuit that delays a flip-flop output signal on the input side of the selector circuit, and an output signal of the frequency division counter. A frequency division counter test circuit is obtained, which is characterized in that it includes a logic circuit that performs a logical operation on the output signal of the delay circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the invention of Wooden Tablet 1, and FIG. 2 is a time chart thereof, showing the case of a 6#)16 frequency division circuit. Input side 1 is connected to the human power of 7 lip flops r2-/n, 4 frequency divided by 7 lip flops 2°3/
configure the The input terminal 1 is connected to the input of the delay circuit 70, and its output is input to the l selector circuit 8. The output of the selector circuit 8 is connected to the input of the flip-flop 4.
1 flip 70 knobs 4 and 5 constitute a 4 frequency division counter,
Output to output terminal 6. The outputs of flip-flops 3 and 5 are input to an exclusive OR circuit 10, and the test output terminal 1)
Output to.

The selector control terminal 9 controls the selector circuit 8, and when the 16 frequency division counter is operating, the output of the flip-flop 3 and the input of the flip-flop 40 are electrically connected, resulting in the same circuit operation as shown in FIG. When testing the frequency dividing counter, the output of the delay circuit 7 is input to the selector circuit 8t-through flip 70g 4.

The input signal 21 of the input side terminal l is 1/
The frequency is divided by 2 to become an n signal 22, and the frequency is further divided by 172 by the flip-flop 3 to become a signal 23.

In addition, the input signal 21 becomes a signal 24 through the delay circuit 7,
The frequency is divided by 172 by flip-flop 4, resulting in signal 25,
Furthermore, the frequency is divided by 1/2 by the flip-flop 5 to obtain a signal 26. The output signal 23 of the flip-flop 3 and the output 2G of the flip-flop 5 are exclusively input to the JRIgi path 10, and the output thereof becomes a signal 27 and is output to the test output terminal 1.

FIG. 3 is a block diagram of one embodiment of the invention of wooden tablet 2.

The circuit is the same as that shown in FIG. 1, except that the delay circuit 7 is provided on the output side of the flip-flop 3.

In addition, in this explanation, an exclusive OR circuit is used as an exclusive OR circuit.
Although this is explained in Section '3, it is clear that the same is possible with an exclusive NOR circuit.

〔Effect of the invention〕

As explained above, the present invention reduces the number of input clock pulses and has the effect of shortening the test time.

[Brief explanation of drawings]

1 and 3 are block diagrams of the embodiments of the frequency dividing counter test circuit of the first and second inventions, FIG. 2 is the time chart of FIG. 1, and FIG. 4 is the conventional frequency dividing counter test circuit. The block diagram of FIG. 5 is the time chart of FIG. 1...Input side child, 2-5...FJip
-Flop, 6... Output terminal, 7...
Delay circuit, 8...Selector circuit, 9...Selector circuit control terminal, 10...Excl
usive -OR circuit, 1) -=-・Test output terminal, 21...Input clock pulse signal, 22
...Flip-Flop 2 output signal, 23
...Flip-Flop 3 output signal, 2
4... Output signal of delay circuit 7, 25...
・Flip-Flop 4 output signal, 26----・F
Output signal of l i p-F op 5, 27・mountain...
------Exclusive-ORIO output signal, 31-...Input side child, 32-35-mountain, -Fl
i p-F op 136...output terminal,
41...Input clock pulse signal, 42-...
-Flip-Flop 32 O output signal, 43-・-
---Output signal of Fl i p-Flo op 33, 4
4-...---Fl 1p-Flop 34 output signal, 45-=-Flip-Flop 35 listening signal. 8 l Ward Waka 2 Ward 27---几-JL 4th Zuman 5 Ward Company

Claims (2)

[Claims] (1) A selector circuit that divides a flip-flop constituting a frequency division counter into multiple stages, a delay circuit that delays the input signal of the frequency division counter and leads it to the selector circuit, and a flip-flop output on the input side of the selector circuit. A frequency division counter test circuit comprising a logic circuit that performs a logical operation on a signal and an output signal of the frequency division counter. (2) a selector circuit that divides a flip-flop constituting a frequency division counter into multiple stages; a delay circuit that delays a flip-flop output signal on the input side of the selector circuit; and an output signal of the frequency division counter and the delay circuit. A frequency division counter test circuit comprising a logic circuit that performs a logical operation on an output signal.