JPH01303926A - Frequency divider circuit for switching two coefficients - Google Patents

Abstract

PURPOSE:To reduce the delay time by providing a gate switch between the output of a 5th D latch and the input of a 6th stage so as to avoid the connection between the D type latches passing through the gate switch and the input gate circuit at the same time. CONSTITUTION:Latch type flip-flop circuit DL1-DL6 are in latch operation when the CP is at an H level and in holding operation when the CP is at an L level. In a 1/4 frequency divider . 1/5 frequency divider operation switching signal MODE, the 1/5 frequency divider is attained at an L level and 1/4 frequency divider operation is attained at the H level of the MODE. Since the connection is not passed through the gate circuit duplicatedly in the connection between the flip-flops, the frequency division operating frequency is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a two-coefficient switching frequency divider circuit used in high frequency PLL control circuits and the like.

(Prior Art) As shown in FIG. 5, this type of conventional circuit consists of three stages of cascade-connected D-type circuits that operate simultaneously using two-phase clocks.
It consists of a flip-flop, a gate switch, and a two-way gate circuit, and the output of the third stage of the D-type flip-flop is connected to the D-type flip-flop through the gate switch and two-way gate circuit.
A circuit configuration in which the input of the first stage of the D-type flip-flop is fed back with a reverse polarity, and the output of the second stage of the D-type flip-flop is fed back with the reverse polarity to the input of the first stage of the D-type flip-flop via the two-person gate circuit. It is.

(Problem to be Solved by the Invention) Due to this circuit configuration, the output waveform of the third stage of the D-type flip-flop passes through the gate switch and the two-person gate circuit before reaching the input of the first stage, resulting in a large delay time. Therefore, there was a drawback that the maximum operating frequency was lowered.

Note that one stage of the D type flip-flop is composed of two stages of cascaded D type latches that alternately perform latching and holding operations based on two-phase clocks.

(Means for Solving the Problems) Against this background, the present invention provides a D type
A gate switch is provided between the output of the 5th stage of the latch and the input of the 6th stage, and by avoiding passing through the gate switch and the input gate circuit at the same time in the connection between the D type latches, the delay time is reduced and the maximum operating frequency is reduced. This will be explained in detail below with reference to the drawings.

(Embodiment) FIG. 1 shows an embodiment of the present invention, in which DL1 to DL6 are D type latch circuits, D is a data input, Q is a data output,
Each has opposite polarity data output, CP is clock input, CP is opposite phase clock input, G1 and G6 are gate circuits, AM
PI is the output data of the two-phase clock buffer circuit, 91
~q5 is the output data of D type latch circuits DLI~DL5, 1 is the reverse polarity output data of DL4, 〒100 is DL6
, dl is the input data of DLL (OR
d6 is the input data of DL6 (output data of OR gate circuit G6), ck and ck
are two-phase clocks with opposite polarities, CLOCK is the input frequency signal, MODE is the 4/15 frequency division operation switching signal,
OUT is a frequency-divided output signal and is connected as shown in the figure.

Next, regarding the operation, all of the latch type flip-flop circuits DLI to DL6 perform a latch operation (transmit the state of input data D to output data Q) when CP is at H level.
,, When CP is at L level, a hold operation (holds output data Q during a latch operation) is performed.

By adding input frequency No. 43 CL [lCK to the two-phase clock buffer circuit AMPI, ck
and i, and when ckfJ<H level, DLL.

3.5 performs a latch operation DL2, 4.6 performs a hold operation, and when ck is at L level, the DLL, 3.5 represents a hold operation DL2, and 4.6 performs a latch operation.

In addition, OR gate G1 adds the signal d1 obtained by ORing G4 and G6 to the data output of DL1, and
DL the signal d6 obtained by ORing G5 and MODE using 6.
6, the circuit in Figure 1 operates as shown in Figure 2, and when the 4/15 frequency division operation switching signal MODE is at L level, the circuit in Figure 1 operates as shown in Figure 2.
When the frequency is divided and )lODE is at H level, the circuit in Figure 1 is 4
Performs frequency division operation.

Since the latch operation time of the D type latch circuit is 1/2 of the input clock cycle, the operation delay time of the D type latch circuit is τ and the delay time of the OR gate circuit is τ. Then, the maximum operating frequency fH is given by 2(τL+τG).

On the other hand, in the conventional circuit, since the signal passes through two OR gate circuits, 2 (τ, +2・τG) given by , and the maximum operating frequency decreases.

By feeding back to MODE the signal obtained by roughly dividing the 4/15 output by another frequency divider, it is possible to create a 32/33 switching frequency divider, a 64/65 switching frequency divider, and a 100/101 frequency divider.
Can be expanded to switching frequency dividers, etc.

Figure 3 shows a 32/33 two-coefficient switching frequency divider circuit according to the present invention.
This is an example of a circuit extended to a switching frequency divider, D-F/Fl 1
~D-F/F13 is a D-type flip-flop and configures a T-type flip-flop by feeding back the Q output to the D terminal.

qll~q13 is Q of DF/Fil-D-F/F13
Terminal output, 011 to G13 are OR gate circuits, dm is O
This is the output of the R gate circuit Gll.

The operation of the circuit in Figure 3 is shown in Figure 4. < MODE is L
At level, it moves by 333, and when MODE is at H level, it moves by 333.
Performs frequency division by 22 motion.

(Effects of the Invention) As explained above, since the connection between flip-flops does not pass through the gate circuit twice, there is an advantage that the frequency division operation frequency becomes high.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a circuit diagram of another embodiment of the present invention, and FIG. The waveform diagram of each part, FIG. 5, shows a conventional example. DLI to DL6...D type latch circuit, Gl, G
6. Gl 1~G13φ...OR gate circuit, AMPI
...2-phase clock buffer circuit, D-F/Fl 1
~D-F/F13...D type flip-flop.

Claims (2)

[Claims] (1) Six stages of cascaded D-type latches that alternately perform latch and hold operations using a two-phase clock;
In the clock divider-by-5 circuit, the D-type latch 4th-stage output and the 6th-stage output are both fed back to the D-type latch 1st-stage input with opposite polarities by an input gate circuit. A 2-coefficient switching frequency divider circuit that switches between clock frequency division by 5 operation and clock frequency division by 4 operation by providing a switch using a gate circuit between the fifth stage output and the sixth stage input. (2) 2-coefficient switching frequency division made by successively dividing the frequency of the clock divided by 4/5 by another frequency divider, and returning each frequency-divided signal to the MODE terminal of the switch via a gate circuit. circuit.