JPH06260930A - 5-division circuit - Google Patents

Abstract

PURPOSE:To provide a 5-division circuit which has a duty ratio of 50%, can facilitate the correction of delay, and can freely set a sequence of combinations with other circuits. CONSTITUTION:The clock pulses inputted from a CLK are inputted to two AND gates 2 and 6, four D type flip-flops 3, 4, 5 and 7, and an OR gate 8 respectively via a buffer 1 consisting of a NOT gate. Then the 1:1 relation is secured between H and L levels of output QE of the gate 8 which has the inputs from the flip-flop circuits 4 and 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for operating a duty ratio in a divide-by-5 circuit used in a gate array of communication equipment or the like.

[0002]

2. Description of the Related Art In a gate array used for communication equipment, a high frequency is divided to create a desired frequency,
We are using. Of the frequency dividers used at this time, 5
A frequency dividing circuit that divides each clock is called a frequency dividing circuit, and in a gate array of a communication device, it is usually a frequency dividing circuit of five or a combination of a frequency dividing circuit of five and a frequency dividing circuit of two. Frequently a divide-by-10 circuit is used.

Conventionally, the following is known as this type of configuration. FIG. 3 shows the configuration of a conventional 5 frequency dividing circuit. FIG. 4 is a timing chart of the circuit of FIG. As shown in FIG. 3, one buffer and two A
It is composed of an ND gate and three D-type flip-flop circuits. The output from the flip-flop 3 is QB, the output from the flip-flop 4 is QC, and the output from the flip-flop 5 is QD.

A timing chart of output when a clock pulse is input from CLK is shown in FIG. RST
Input is connected to R of three flip-flops. Input of clock pulse from CLK is buffer 1
Is connected to C of the flip-flop 3 and C of the flip-flop 5. Output Q of flip-flop 3
Is shown in FIG. The output bar Q of the flip-flop 3 is connected to the AND gate 2 and C of the flip-flop 4. The output bar Q of the flip-flop 4 is connected to D of the flip-flop 4, and the output Q is shown in FIG. 4 (d). Output QB and output QC are connected to AND gate 6,
The output of the AND gate 6 is connected to D of the flip-flop 5. The output Q of the flip-flop 5 is (e) in FIG.
Shown in. The output bar Q is connected to the AND gate 2,
The output of the AND gate 2 is connected to D of the flip-flop 3.

The ratio of the H level to one cycle is called the duty ratio, and the ratio between the H level and the L level is 1: 4, as can be seen from the QD of FIG. 4 (e), so the duty ratio is 20. %.

[0006]

The duty ratio is 50.
%, The H level and the L level have the same time, so that there is a feature that the delay can be easily corrected to some extent. But,
When the duty ratio is low or high, the time difference between the H level and the L level is large, so that it is difficult to correct the delay and malfunction may occur. In the frequency dividing circuit having such a configuration, the QC output and the Q output of FIG.
The duty ratio of the D output became low, and it was difficult to correct the phase delay. Further, in the case where the frequency division is performed in combination with the frequency division circuit by 2, the frequency division cannot be performed unless the frequency is divided by 5 and then the frequency is divided by 2, resulting in a low degree of freedom in circuit design. The present invention has been made in order to solve the above-mentioned problems, and makes it possible to easily correct delays by setting the duty ratio to 50% and to divide a circuit that can be divided in any order even when combined with other circuits. The purpose is to provide.

[0007]

In order to achieve the above object, the present invention adds a D type flip-flop and an OR gate to the conventional divide-by-5 circuit.

[0008]

Operation: Input of clock pulse is one buffer, two AND gates, four D type flip-flops, 1
The duty ratio is set to 50% by dividing the frequency by 5 with one OR gate.

[0009]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a timing chart of FIG. The operation of the embodiment will be described below with reference to the timing chart of FIG. The divide-by-5 circuit of the present invention comprises one buffer consisting of a NOT gate, two AND gates, four D-type flip-flops and one OR gate. The AND gates 2 and 6 both have a two-line input and have the same configuration. Further, the D-type flip-flops 3, 4, 5, and 7 have the same configuration and R terminals.

The input from the RST terminal is input to R of four flip-flops. The input of the clock pulse from CLK is input to C of the flip-flop 7. Further, the signal input from CLK is passed through the buffer 1 to the C of the flip-flop 3 and the C of the flip-flop 5.
Entered in. The output Q of the flip-flop 3 is shown in FIG.
It is shown in the output QB of (c). The output bar Q of the flip-flop 3 is input to the AND gate 2 and C of the flip-flop 4. Output Q of flip-flop 4, FIG. 2 (d)
Output QC of the flip-flop 4 output bar Q
Is input to D of the flip-flop 4. The output QB and the output QC are input to the AND gate 6, and the output of the AND gate 6 is input to D of the flip-flop 5. The output QC is also input to the D of the flip-flop 7 and the OR gate 8. The output Q of the flip-flop 5 is shown in FIG.
It is shown in the output QD of (e). The output bar Q is input to the AND gate 2, and the output of the AND gate 2 is input to D of the flip-flop 3. The output Q of the flip-flop 7 is shown as the output 7Q of FIG. The output of the OR gate 8 is shown at the output QE of FIG.

As shown in FIG. 2 (g), H level and L level of QE
The time ratio of levels is 1: 1. That is, the duty ratio of this frequency dividing circuit is 50%.

[0012]

As described above in detail, according to the present invention, the duty ratio of the output due to QE is 50%, and the H level and L level times are equal, so there is some phase shift due to delay. It's easy to fix. Also, the degree of freedom in circuit design is increased when combined with other frequency dividing circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of a divide-by-5 circuit of the present invention.

FIG. 2 is a timing chart of the present invention.

FIG. 3 is a block diagram of a conventional divide-by-5 circuit.

FIG. 4 is a timing chart of a conventional technique.

[Explanation of symbols]

 1 buffer 2, 6 AND gate 3, 4, 5, 7 D type flip-flop 8 OR gate

Claims (1)

[Claims] 1. A buffer to which an input clock is supplied, a first flip-flop having an output of the buffer and an output of a first AND gate as inputs, and a self-inversion output as an input, A second flip-flop having an inverted output of the flip-flop as a clock input; and a third flip-flop having an output of the buffer and an output of the second AND gate as inputs, The inverting output and the inverting output of the third flip-flop are input to the first AND gate, and the output of the first flip-flop and the output of the second flip-flop are input to the second AND gate. And a fourth flip-flop having the input of the input clock and the output of the second flip-flop as input, and the second flip-flop. 5 frequency divider circuit, characterized in that it comprises an OR gate having input and output of the flop the output of the fourth flip-flop.