JPH05102844A - Frequency divider circuit - Google Patents

Abstract

PURPOSE:To provide the frequency divider circuit able to frequency-divide a frequency of an input signal into 1/10 or 1/11 in which a delay margin is larger than that of a conventional frequency divider circuit and malfunction at changeover of a frequency division ratio is suppressed. CONSTITUTION:An input signal is given from an input terminal 9 to a CL input terminal of D flip-flop circuits 4, 5, 6. NAND circuits 1, 3 and a NOR circuit 2 give a switching signal given to a changeover terminal 8 and a signal based on an output of the D flip-flop circuits 5, 6 and an output of a T flip-flop circuit 7 to a D flip-flop circuit 4. An output of the D flip-flop circuit 4 is given to the T flip-flop circuit 7. Thus, even when a high frequency signal whose frequency exceeds 1GHz is received, the malfunction at changeover of a frequency division ratio is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency dividing circuit for dividing an input signal into 1/10 or 1/11 based on a switching signal, and more particularly to a frequency dividing circuit suitable as a prescaler for high frequency signals.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional frequency dividing circuit of this type. The input signal input from the input terminal 19 is applied to each CL input terminal of the D type flip-flop circuits 14, 15 and 16. Further, the Q output of the D type flip-flop circuit 14 is given to the D input terminal of the D type flip-flop circuit 15, and the Q output of this D type flip-flop circuit 15 is given to the D input terminal of the D type flip-flop circuit 16. .. Further, the Q output of the D type flip-flop circuit 16 is given to the CL input terminal of the T type flip-flop circuit 17. The Q output of the T type flip-flop circuit is output to the outside via the output terminal 20. The inverted Q output of the T type flip-flop circuit 17 is applied to the D input terminal of the T type flip-flop circuit 17.

A switching signal is applied to one input terminal of the NAND circuit 11 from the switching terminal 18, and the Q output of the T-type flip-flop circuit 17 is applied to the other input terminal. Further, the output of the NAND circuit 11 is given to one input end of the NOR circuit 12, and the Q output of the D type flip-flop circuit 15 is given to the other input end. Further, the output of the NOR circuit 12 is given to one input terminal of the NAND circuit 13, and the Q output of the D type flip-flop circuit 16 is given to the other input terminal. The output of this NAND circuit 13 is
It is applied to the inverted D input terminal of the D type flip-flop circuit 14.

In the frequency dividing circuit thus configured, the signal applied to the input terminal 19 is divided into 1/10 or 1/11 based on the switching signal applied to the switching terminal 18, and the divided signal is output.

FIG. 4 is a timing chart showing the operation of the above circuit.

When the input signal is divided into 1/10, the switching signal supplied to the switching terminal 18 is set to "H". As a result, the output of the NAND circuit 11 is always "H" regardless of the output state of the T-type flip-flop circuit 17.
Therefore, the output of the NOR circuit 12 becomes the same as the output of the D type flip-flop circuit 15. NAND circuit 13
Outputs "L" when both the output of the NOR circuit 12 and the Q output of the D-type flip-flop circuit 16 are "L", and otherwise outputs "H".

In this way, the outputs of the D type flip-flop circuits 14, 15 and 16 are all input terminals 19.
The frequency of the signal input from is divided into ⅕. Therefore, the output of the T-type flip-flop circuit 17 becomes a signal obtained by dividing the frequency of the input signal by 1/10.

When the input signal is divided into 1/11, the switching signal supplied to the switching terminal 18 is set to "L". As a result, the output of the NAND circuit 11 becomes the same as the Q output of the T type flip-flop circuit 17. This NAND circuit 1
When the output of 1 is "L", the output of the NOR circuit 12 is always "L" regardless of the Q output of the D-type flip-flop circuit 15. Therefore, the outputs of the D-type flip-flop circuits 14, 15 and 16 are signals obtained by dividing the frequency of the signal given from the input terminal 19 into 1/6.

On the other hand, when the output of the NAND circuit 11 is "H", the output of the NOR circuit 12 becomes the same as the output of the D type flip-flop circuit 15. At this time, the outputs of the D-type flip-flop circuits 14, 15 and 16 are signals obtained by dividing the input signal by ⅕. Therefore, the output of the T-type flip-flop circuit 17 becomes a signal obtained by dividing the frequency of the input signal by 1/11.

[0010]

However, the above-mentioned conventional frequency dividing circuit has a problem that the delay margin with respect to the timing of changing the switching signal is small. That is, in the above-described conventional frequency dividing circuit, when the frequency dividing ratio is switched from 1/10 to 1/11, the delay margin when inverting the switching signal is such that the Q output of the T type flip-flop circuit 17 is "L". There are only 4 clocks from the time when the D type flip-flop circuit 15 becomes "H" to the time when the D type flip-flop circuit 15 becomes "H". Therefore, for example, if the frequency of the input signal is 1G
4 for high-frequency signal prescaler above Hz
With the delay margin of the clock, the operation is divided into 1/10
There is a problem that a malfunction tends to occur when switching to an operation of dividing by / 11.

The present invention has been made in view of the above problems, and has a larger delay margin than the conventional one, can suppress malfunctions at the time of switching the frequency division ratio, and is suitable as a prescaler for high frequency signals. The purpose is to provide a circuit.

[0012]

A frequency dividing circuit according to the present invention comprises first, second and third D type flip-flop circuits to which an input signal is applied, a T type flip-flop circuit, a switching signal, and A logic circuit for giving a signal based on the output of the T-type flip-flop circuit and the outputs of the second and third D-type flip-flop circuits to the first D-type flip-flop circuit,
The output of the D-type flip-flop circuit of
It is provided to the type flip-flop circuit and the T-type flip-flop circuit, and the output of the second D-type flip-flop circuit is given to the third D-type flip-flop circuit.

[0013]

In the present invention, the first D-type flip-flop circuit, the second D-type flip-flop circuit to which the output of the first D-type flip-flop circuit is given, and the second D-type flip-flop circuit are provided. A third D-type flip-flop circuit to which an output is given and a logic circuit for giving a signal based on a switching signal etc. to the first D-type flip-flop circuit are provided, and the T-type flip-flop circuit is provided with the first D-type. The output of the type flip-flop circuit is given. In this case, the logic circuit outputs, for example, a switching signal and a signal based on the output of the T-type flip-flop circuit to the first NAND.
Circuit, the output of the first NAND circuit and the second D
It is composed of a NOR circuit that outputs a signal based on the output of the type flip-flop circuit, and a second NAND circuit that outputs a signal based on the output of the NOR circuit and the output of the second D-type flip-flop circuit.
As a result, the frequency dividing circuit according to the present invention reduces the frequency division ratio to 1/1.
It is possible to switch to 0 or 1/11, the delay margin at the time of switching can be made larger than that of the conventional one, and the malfunction at the time of switching can be suppressed even when the frequency of the input signal is extremely high.

[0014]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a frequency dividing circuit according to an embodiment of the present invention.

The signal applied to the input terminal 9 is applied to the CL input terminals of the D type flip-flop circuits 4, 5 and 6. The Q output of the D type flip-flop circuit 4 is T
It is given to the CL input terminal of the type flip-flop circuit 7 and the D input terminal of the D type flip-flop circuit 5, and the Q output of this D type flip-flop circuit 5 is given to the D input terminal of the D type flip-flop circuit 6.

The Q output of the T-type flip-flop circuit 7 is sent to the outside through the output terminal 10. The inverted Q output of the T type flip-flop circuit 7 is given to the D input terminal of the T type flip-flop circuit 7.

A switching signal is applied from the switching terminal 8 to one input end of the NAND circuit 1, and the Q output of the T type flip-flop circuit 7 is applied to the other input end. The output of the NAND circuit 1 is applied to one input end of the NOR circuit 2, and the Q output of the D-type flip-flop circuit 5 is applied to the other input end. Further, the output of the NOR circuit 2 is given to one input end of the NAND circuit 3, and the D type flip-flop circuit 6 is given to the other input end.
Q output is provided. The output of the NAND circuit 3 is given to the inverting D input terminal of the D type flip-flop circuit 4.

FIG. 2 is a timing chart showing the operation of the circuit of this embodiment.

When the input signal is divided into 1/10, the switching signal supplied to the switching terminal 8 is set to "H". As a result, the output of the NAND circuit 1 is always "H" regardless of the output state of the T-type flip-flop circuit 7. Therefore, the output of the NOR circuit 2 becomes the same as the output of the D type flip-flop circuit 5. The NAND circuit 3 outputs "L" when the output of the NOR circuit 2 and the Q output of the D-type flip-flop circuit 6 are both "L", and otherwise outputs "H".

In this way, the outputs of the D type flip-flop circuits 4, 5 and 6 are signals obtained by dividing the frequency of the signal input from the input terminal 9 into 1/5. Therefore, the output of the T-type flip-flop circuit 7 becomes a signal obtained by dividing the frequency of the input signal by 1/10.

When the input signal is divided into 1/11, the switching signal applied to the switching terminal 8 is set to "L". As a result, the output of the NAND circuit 1 becomes the same as the Q output of the T type flip-flop circuit 7.

When the output of the NAND circuit 1 is "H", the output of the NOR circuit 2 becomes the same as the Q output of the D type flip-flop circuit 5. At this time, the outputs of the D-type flip-flop circuits 4, 5 and 6 are signals obtained by dividing the input signal by ⅕.

On the other hand, when the output of the NAND circuit 1 is "L", the output of the NAND circuit 3 becomes the same as the Q output of the D type flip-flop circuit 6. Therefore, at this time, the rise of the output of the NAND circuit 3 is delayed by one clock as compared with the output of the D-type flip-flop circuit 5. As a result, the D-type flip-flop circuit 4,
The outputs of 5 and 6 are signals obtained by dividing the input signal by 1/6.

Since the T type flip-flop circuit 7 operates based on the Q output of the D type flip-flop circuit 4, the Q output of the T type flip-flop circuit 7 is a signal obtained by dividing the frequency of the input signal by 1/11. Becomes

In this case, the division ratio is 1/10 to 1/1.
The delay margin when switching to 1 is such that the output of the NOR circuit 2 becomes "L" and then the Q output of the T type flip-flop circuit 7 becomes "L", and the D type flip-flop circuit 5
It is 8 clocks until the Q output of rises.
That is, the circuit of this embodiment has a delay margin twice as large as that of the conventional circuit. As a result, the circuit according to the present embodiment can suppress the malfunction at the time of switching even when the frequency of the input signal exceeds 1 GHz, for example.

[0027]

As described above, according to the present invention,
Since the output of the first D-type flip-flop circuit is given to the input end of the T-type flip-flop circuit, the delay margin is larger than in the conventional case, and the malfunction at the time of switching the division ratio can be suppressed. Therefore, the frequency dividing circuit according to the present invention is extremely useful, for example, as a high-frequency signal prescaler in which the frequency of the input signal exceeds 1 GHz.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a frequency dividing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart diagram showing the same operation.

FIG. 3 is a circuit diagram showing a conventional frequency dividing circuit.

FIG. 4 is a timing chart showing the operation of the same.

[Explanation of symbols]

1, 3, 11, 13; NAND circuit 2, 12; NOR circuit 4, 5, 6, 14, 15, 16; D type flip-flop circuit 7, 17; T type flip-flop circuit 8, 18; Switching terminal 9, 19; Input terminal 10, 20; Output terminal

Claims (2)

[Claims] 1. A first, second, and third D-type flip-flop circuit to which an input signal is applied, a T-type flip-flop circuit, a switching signal, an output of the T-type flip-flop circuit, and the second and third The signal based on the output of the D-type flip-flop circuit of
A logic circuit for giving to a type flip-flop circuit, the output of the first D-type flip-flop circuit is given to the second D-type flip-flop circuit and the T-type flip-flop circuit, and the second D-type flip-flop circuit is provided. A frequency divider circuit, wherein the output of the type flip-flop circuit is given to the third D-type flip-flop circuit. 2. The first logic circuit, wherein the logic circuit outputs a signal based on the switching signal and the output of the T-type flip-flop circuit, an output of the first NAND circuit, and the second D-type circuit. NOR circuit for outputting a signal based on the output of the flip-flop circuit, and this NOR circuit
A second NAND circuit that outputs a signal based on the output of the circuit and the output of the third D-type flip-flop circuit, and the first D-type flip-flop circuit has an output of the second NAND circuit. The frequency dividing circuit according to claim 1, wherein