JPH0523626U - Clock duty adjustment circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To variably control the duty of the clock. [Structure] An input clock a input to an input terminal 1 includes a plurality of (3 in the figure) delay elements (D) 2 connected in cascade.
4 each delayed by a time T3. AND gate 5
7 to 7 are input clock a and outputs b to d of the delay elements 2 to 4.
One of the input. The OR gates 8 to 10 receive the input clock a and one of the outputs b to d of the delay elements 2 to 4. The selection circuit 11 inputs the input clock a, the outputs e to j of the AND gates 5 to 7 and the OR gates 8 to 10 to each of the input ends, and selects the input end by the selection signal input to the external selection terminal 12. One of them is selected, and the duty-adjusted clock k input to the input terminal is output to the output terminal 13.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a clock duty adjustment circuit that adjusts the duty of a clock.

[0002]

[Prior Art]

 The first example of the conventional clock duty adjusting circuit is, as shown in the block diagram of FIG. 3, an AND gate 22 that connects an input clock 20 and a clock 20 that has been delayed for a certain time by passing through a delay element (D) 21. To enter. Then, at the output terminal 23 of the AND gate 22, a clock having a reduced time ratio (duty) of the logic level "1" of the clock 20 is obtained.

A second example of the conventional clock duty adjusting circuit is, as shown in the block diagram of FIG. 4, an input clock 24 and a clock 24 delayed by a certain time after passing through a delay element (D) 25. Input to the OR gate 26. Then, at the output terminal 27 of the OR gate 26, a clock in which the time ratio (duty) of the logic level "1" of the clock 24 is increased is obtained.

A third example of the conventional clock duty adjusting circuit is, as shown in the block diagram of FIG. 4, inputs an input clock 30 into a tank drive circuit (TANK) 31 and converts it into a sine wave, Is input to the comparator (COMP) 32 and the threshold voltage is adjusted to obtain a clock having a desired duty at the output terminal 33.

[0005]

[Problems to be solved by the device]

 The duty adjusting circuits of the first and second conventional examples described above have a drawback that they are not very flexible with respect to changing the duty of the input clock, and in the third conventional example, the tank drive circuit used is expensive. However, it had the disadvantage of being large in volume.

[0006]

[Means for Solving the Problems]

 The clock duty adjusting circuit of the present invention receives N (N is a plurality) delay elements connected in cascade for sequentially delaying an input clock, and inputs one of the input clock and the output of the N delay elements. N 2-input AND gates, N 2-input OR gates that receive the input clock and one of the outputs of the N delay elements, and 2 N + 1 input terminals each have the input clock and A selection circuit for receiving the outputs of the N 2-input AND gates and the outputs of the N 2-input OR gates and selecting one of the 2 N + 1 input terminals according to a control signal.

[0007]

【Example】

 Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment according to the present invention.

In the clock duty adjusting circuit 100, the input clock a input to the input terminal 1 is composed of N delay elements connected in cascade, in the figure, N = 3 delay elements (D) 2, Each of 3 and 4 is delayed by a specific time T3. The N two-input AND gates, AND gates 5, 6 and 7 in the figure, receive the input clock a and one of the outputs of the N delay elements. The N 2-input OR gates, OR gates 8, 9 and 10 in the figure, receive the input clock a and one of the outputs of the N delay elements. The selection circuit 11 inputs the input clock a 1, the output of the N 2-input AND gates and the output of the N 2-input OR gates to each of the 2N + 1 (7) input terminals, and inputs them to the external selection terminal 12. One of the 2N + 1 input terminals is selected by the selected signal, and the duty-adjusted clock k input to the input terminal is output to the output terminal 13.

Clock waveforms of respective portions of the embodiment shown in FIG. 1 will be described below with reference to the waveform chart shown in FIG. The input clock a is a clock having a repetition period T, T 1 during the period of logic level “1”, and T 2 during the period of logic level “0”. The rising time of the input clock a is t1 and t3, and the falling time thereof is t2. The clocks b, c and d output to each of the delay elements 2, 3 and 4 are sequentially delayed from the clock a by the rising and falling of T3. The rising edges of the clocks g, f and e output from the AND gates 7, 6 and 5 which receive the input clock a and one of the above clocks b, c and d start from the time t1 or t3. And d, respectively, by delay times T3, 2T3 and 3t3. On the other hand, the falling edges of the clocks g, f, and e coincide with the falling time t2 of the input clock a. In this way, the clocks e, f and g output from the AND gates 5, 6 and 7 are reduced in the period of the logic level "1", that is, the duty. The falling edges of the clocks h, i and j output from the OR gates 8, 9 and 10 which receive the input clock a and one of the clocks b, c and d described above, start from the time t2 and are clocks b, c and. d Delay by the respective delay times T3, 2T3 and 3t3. On the other hand, the rising edges of the clocks h, i, and j coincide with the rising time t1 or t3 of the input clock a. In this way, the clocks h 1, i and j output from the OR gates 8, 9 and 10 increase in the period of the logic level “1”, that is, the duty. The input clock a and the clocks e to j are input to different input terminals of the selection circuit 11. The selection circuit 11 selects the clock f whose duty is adjusted by the selection signal input to the external selection terminal 12, and outputs it to the output terminal 13 as the selected clock k.

By the method described above, the clock duty adjusting circuit 10 of the embodiment shown in FIG. 1 can variably control the clock duty by giving a selection signal to the external selection terminal 12. Further, this clock duty adjusting circuit can be easily integrated in the IC.

[0011]

[Effect of the device]

 As described above, the present invention takes AND and OR gates of the respective outputs of a plurality of delay elements for sequentially delaying the input clock and the input clock, and thereby generates one of the duty-adjusted clocks. By selecting one of them, it is possible to variably control the duty of the clock.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a clock waveform diagram of each part of the embodiment of FIG.

FIG. 3 is a block diagram of a first conventional example.

FIG. 4 is a block diagram of a second conventional example.

FIG. 5 is a block diagram of a third conventional example.

[Explanation of symbols]

 1 input terminal 2-4,21,25 delay element (D) 5-7,22 AND gate 8-10,26 OR gate 11 selection circuit 12 external selection terminal 13,23,27,33 output terminal 20,24,30 Input clock 31 Tank drive circuit (TANK) 32 Comparator (COMP) 100 Clock duty adjustment circuit a Input clock b to k clock

Claims (1)

[Scope of utility model registration request] 1. N (N is a plurality) delay elements connected in cascade for sequentially delaying an input clock, and N input elements each of which is one of the input clock and the output of the N delay elements. A 2-input AND gate, and N 2-input ORs that receive the input clock and one of the outputs of the N delay elements
A gate and 2N + 1 input terminals each receive the input clock, the outputs of the N 2-input AND gates and the outputs of the N 2-input OR gates, and one of the 2N + 1 input terminals is controlled by a control signal. And a selection circuit for selecting one of them.