CN109302166B - Pulse width modulation circuit and device - Google Patents
Pulse width modulation circuit and device Download PDFInfo
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- CN109302166B CN109302166B CN201811041822.9A CN201811041822A CN109302166B CN 109302166 B CN109302166 B CN 109302166B CN 201811041822 A CN201811041822 A CN 201811041822A CN 109302166 B CN109302166 B CN 109302166B
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- H—ELECTRICITY
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- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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Abstract
The invention discloses a pulse width modulation circuit and a pulse width modulation device. The pulse width modulation circuit comprises a time sequence control circuit, a digital selection circuit, a delay trigger circuit and a pulse output circuit, wherein a selection signal control end of the digital selection circuit is electrically connected with a selection signal line, a plurality of alternative phase input ends are respectively and electrically connected with a plurality of corresponding alternative phase output ends, and the digital selection circuit outputs a phase selection pulse signal at the phase selection output end according to a selection control signal on the selection signal line; and a phase selection input end of the delay trigger circuit is electrically connected with a phase selection output end, an adjusting signal input end is electrically connected with the first adjusting signal line, the delay trigger circuit delays the phase selection pulse signal for an adjustable time according to the first adjusting signal on the first adjusting signal line, and a reset signal is output from the reset signal output end. The invention effectively improves the precision of the pulse width modulation circuit through the rough adjustment and the fine adjustment of the duty ratio.
Description
Technical Field
The embodiment of the invention relates to the technical field of electronics, in particular to a pulse width modulation circuit and a pulse width modulation device.
Background
The main function of a Digital Pulse Width Modulation (DPWM) circuit is to convert an input Digital control signal into a Pulse signal with a corresponding Pulse Width. If the frequency of the pulse signal is fixed, the duty ratio of the pulse signal can be adjusted by adjusting the pulse width.
DPWM circuits are widely used in the field of electronics, for example, in lighting control systems, different duty cycles correspond to different luminances, and digital control of the luminance of the lighting system can be achieved by the DPWM circuits, and for example, in direct current-to-direct current (DC-DC) converters, different duty cycles correspond to different output voltages, and digital control of the DC-DC converters can be achieved by the DPWM circuits. However, the resolution ratio of the existing DPWM circuit for duty ratio adjustment is low, and the requirement of duty ratio adjustment with higher precision cannot be met.
Disclosure of Invention
The invention provides a pulse width modulation circuit and a pulse width modulation device, which aim to improve the precision of duty ratio regulation.
In a first aspect, an embodiment of the present invention provides a pulse width modulation circuit, where the pulse width modulation circuit includes:
the time sequence control circuit comprises a first clock signal input end and a plurality of alternative phase output ends, wherein the first clock signal input end is electrically connected with a clock signal line, and the time sequence control circuit is used for outputting alternative pulse signals with sequentially delayed phases at the alternative phase output ends according to an input clock signal on the clock signal line;
the digital selection circuit comprises a selection signal control end, a plurality of alternative phase input ends and a selection phase output end, wherein the selection signal control end is electrically connected with the selection signal line, the alternative phase input ends are respectively and electrically connected with the corresponding alternative phase output ends, and the digital selection circuit is used for outputting a selection phase pulse signal at the selection phase output end according to a selection control signal on the selection signal line;
the delay trigger circuit comprises a selection phase input end, an adjusting signal input end and a reset signal output end, wherein the selection phase input end is electrically connected with the selection phase output end, the adjusting signal input end is electrically connected with a first adjusting signal line, and the delay trigger circuit is used for delaying the selection phase pulse signal for an adjustable time according to a first adjusting signal on the first adjusting signal line and outputting a reset signal from the reset signal output end;
the pulse output circuit comprises a second clock signal input end, a reset signal input end and a pulse signal output end, the second clock signal input end is electrically connected with the phase comparison signal line, the reset signal input end is electrically connected with the reset signal output end, the pulse signal output end is electrically connected with the pulse output signal line, and the pulse output circuit is used for controlling the duty ratio of the pulse signal output by the pulse signal output end according to the phase comparison signal input by the phase comparison signal line and the reset signal input by the reset signal input end.
In a second aspect, embodiments of the present invention further provide a digital pulse width modulation apparatus, where the digital pulse width modulation apparatus includes a pulse width modulation circuit as provided in any of the embodiments of the present invention.
The digital selection circuit is electrically connected with a selection signal line through a selection signal control end provided with the digital selection circuit, a plurality of alternative phase input ends are respectively electrically connected with a plurality of corresponding alternative phase output ends, and the digital selection circuit outputs a phase selection pulse signal at the phase selection output end according to a selection control signal on the selection signal line; compared with the prior art, the pulse width modulation circuit realizes a plurality of pulse width modulation circuits with the combined action of phase selection and time delay, namely, the precision of the pulse width modulation circuit is effectively improved through rough adjustment and fine adjustment of duty ratio.
Drawings
Fig. 1 is a schematic structural diagram of a pwm circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram of a PWM circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a duty cycle output of a pwm circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another pulse width modulation circuit according to an embodiment of the present invention;
fig. 5 is a circuit diagram of a first time delay circuit according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
The embodiment of the invention provides a pulse width modulation circuit. Fig. 1 is a schematic structural diagram of a pulse width modulation circuit according to an embodiment of the present invention. Referring to fig. 1, the pulse width modulation circuit includes: a timing control circuit 100, a digital selection circuit 200, a delay trigger circuit 300, and a pulse output circuit 400. The timing control circuit 100 includes a first clock signal input terminal 101 and a plurality of alternate phase output terminals 102 (exemplarily including 8 alternate phase output terminals 102 in fig. 1, i.e., 8-phase timing output), the first clock signal input terminal 101 being electrically connected to the clock signal line 10. The timing control circuit 100 is configured to output alternate pulse signals with sequentially delayed phases at a plurality of alternate phase output terminals 102 according to an input clock signal on the clock signal line 10. The digital selection circuit 200 includes a selection signal control terminal 201, a plurality of candidate phase input terminals 202 (exemplarily, 8 candidate phase input terminals 202 are included in fig. 1), and a selection phase output terminal 203, the selection signal control terminal 201 is electrically connected to the selection signal line 20, and the plurality of candidate phase input terminals 202 are electrically connected to the corresponding plurality of candidate phase output terminals 102, respectively. The digital selection circuit 200 is arranged to output a selection phase pulse signal at a selection phase output 203 in response to a selection control signal on a selection signal line 20. The delay flip-flop circuit 300 includes a selection phase input terminal 301, an adjustment signal input terminal 302, and a reset signal output terminal 303, the selection phase input terminal 301 being electrically connected to the selection phase output terminal 203, and the adjustment signal input terminal 302 being electrically connected to the first adjustment signal line 30. The delay trigger circuit 300 is used for delaying the phase selection pulse signal for an adjustable time according to the first adjustment signal on the first adjustment signal line 30 and outputting the reset signal from the reset signal output terminal 303. The pulse output circuit 400 includes a second clock signal input terminal 401, a reset signal input terminal 402, and a pulse signal output terminal 403, the second clock signal input terminal 401 being electrically connected to the phase comparison signal line 40, the reset signal input terminal 402 being electrically connected to the reset signal output terminal 303, and the pulse signal output terminal 403 being electrically connected to the pulse output signal line 50. The pulse output circuit 400 is configured to control the duty ratio of the pulse signal output from the pulse signal output terminal 403 according to the phase comparison signal input from the phase comparison signal line 40 and the reset signal input from the reset signal input terminal 402.
Exemplarily, FIG. 2 is the bookThe embodiment of the invention provides a timing diagram of a pulse width modulation circuit. Referring to fig. 1 and fig. 2, the operation process of the pulse width modulation circuit is that the timing control circuit 100 outputs alternative pulse signals with sequentially delayed phases at a plurality of alternative phase output terminals 102 according to the input clock signal on the clock signal line 10, and the phase differences of the alternative pulse signals of adjacent phases are equal, i.e. the time differences of the delays are equal. Taking an 8-phase candidate pulse signal as an example, the phase difference is 45 °, and the phases of the 8 candidate pulse signals are 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, and 315 ° in sequence. The digital selection circuit 200 outputs a selection phase pulse signal F at a selection phase output 203 according to a selection control signal on a selection signal line 20 D In FIG. 2, a third pulse signal (i.e., a pulse signal with a phase of 135 DEG, which is delayed by a time t compared to the 0 th pulse signal) is selected as an example c ) Therefore, a plurality of phases are preliminarily selected, and coarse adjustment of the duty ratio is realized. The delay trigger circuit 300 selects the phase pulse signal F according to the first adjustment signal on the first adjustment signal line 30 D Delaying an adjustable time t w Obtaining a delayed selective phase pulse signal F YD And outputs a reset signal, i.e., a pair of selective phase pulse signals F, from a reset signal output terminal 303 D And carrying out controllable time delay and using the time delay as the fine tuning time of the pulse width modulator to realize the fine tuning of the duty ratio. Optionally, the phase pulse signal F is selected D The maximum delay time of (2) is the time corresponding to the phase difference between two adjacent candidate pulse signals. Illustratively, the phase-selective pulse signal F of the pulse width modulation circuit shown in FIG. 1 D The minimum delay time range of the pulse width modulation circuit can correspond to the phase of 0-45 degrees, so that the fine tuning range of the pulse width modulation circuit can be ensured to fully cover the duty ratio of 0-1. Alternatively, the phase comparison signal line 40 is electrically connected to the 0-phase signal candidate pulse signal output terminal of the timing control circuit 100, so that the 0-phase signal candidate pulse signal is input to the second clock signal input terminal 401. The pulse output circuit 400 outputs the 0-phase signal F according to the second clock signal input terminal 401 Y0 And a reset signal control pulse signal inputted from a reset signal input terminal 402The pulse signal output by the output terminal 403. Wherein the delayed selective phase pulse signal F YD And 0 phase signal F Y0 With a fixed phase difference therebetween, forming an output pulse signal with an output time span t c +t w The duty ratio is (t) c +t w ) and/T, wherein T is the period of the output pulse signal. In particular, the reset signal may be delayed by a time t by a coarse adjustment of the duty cycle c The reset signal can be delayed for a further time t by fine-tuning the duty cycle w . If the reset signal is not delayed, the duty ratio of the output pulse signal is 0, and if the reset signal is delayed by a time T of one cycle, the duty ratio of the output pulse signal is 1.
Fig. 3 is a schematic diagram of a duty cycle output of a pulse width modulation circuit according to an embodiment of the present invention. Referring to fig. 3, a point a, a point B, a point C, a point D, a point E, a point F, a point G, and a point H are duty ratios output at the pulse signal output terminal 403 only by coarse adjustment, and duty ratios output at the pulse signal output terminal 403 by coarse adjustment and fine adjustment are between the points, respectively, so that it can be seen that the embodiment of the present invention implements fine adjustment of the duty ratio at the full phase by coarse adjustment and fine adjustment.
In the embodiment of the present invention, a selection signal control terminal 201 of a digital selection circuit 200 is arranged to be electrically connected to a selection signal line 20, a plurality of candidate phase input terminals 202 are respectively electrically connected to a plurality of corresponding candidate phase output terminals 102, and the digital selection circuit 200 outputs a selection phase pulse signal at a selection phase output terminal 203 according to a selection control signal on the selection signal line 20; and the selective phase input terminal 301 of the delay trigger circuit 300 is electrically connected with the selective phase output terminal 203, the adjusting signal input terminal 302 is electrically connected with the first adjusting signal line 30, the delay trigger circuit 300 delays the selective phase pulse signal for an adjustable time according to the first adjusting signal on the first adjusting signal line 30, and outputs the reset signal from the reset signal output terminal 303.
Fig. 4 is a schematic structural diagram of another pulse width modulation circuit according to an embodiment of the present invention. Referring to fig. 4, on the basis of the above embodiments, the timing control circuit 100 optionally includes 2 N-1 And a first D flip-flop 110, N is an integer and N is greater than or equal to 2. 2 N-1 Clock pulse ends of the first D flip-flops 110 are electrically connected to a clock signal line 10, 2 N-1 The first output terminal Q and the second output terminal Qb of the first D flip-flop 110 are used as the alternative phase output terminal 102 of the timing control circuit 100, and the trigger signal input terminals D and 2 of the 1 st first D flip-flop 110 N-1 The second output Qb of the ith first D flip-flop 110 is electrically connected, the trigger signal input D of the ith first D flip-flop 110 is electrically connected with the first output Q of the (i-1) th first D flip-flop 110, and i is more than or equal to 2 and less than or equal to 2 N-1 . The operation process of the timing control circuit 100 is that after the clock signal on the clock signal line 10 enters the timing control circuit 100, it is controlled by 2 N-1 The circuit formed by the first D flip-flops 110 is an N-bit timing control circuit, and since the first D flip-flop 110 includes a first output terminal Q and a second output terminal Qb, and phases of the first output terminal Q and the second output terminal Qb are opposite (for example, a phase of the alternative pulse signal output by the first output terminal Q of the 1 st first D flip-flop 110 is 0 °, and a phase of the alternative pulse signal output by the second output terminal Qb is 180 °), therefore, the 2 nd D flip-flop 110 has a phase shift of N + Q + N + Q + N + Q + N + z + N-1 The circuit composed of the first D flip-flops 110 is an N-bit sequential control circuit, which can generate 2 N The candidate pulse signals have a fixed phase difference, and the number of the first D flip-flops 110 determines the coarse tuning accuracy of the pwm modulator. The value of the phase difference is determined by the number of the first D flip-flops 110, and taking N-3 as an example, the number of the first D flip-flops 110 is 4, the number of the candidate pulse signals is 8, and the phase difference is 45 °. The timing control circuit 100 of the embodiment of the invention comprises a circuit 2 N-1 A first D flip-flop 110, implementing 2 N An output of a candidate pulse signal, and 2 N The phase difference between the alternative pulse signals is equal, and the precision of the pulse width modulation circuit is further improved. In addition, the embodiment of the invention also carries out fine adjustment after coarse adjustment, and does not need to control the time sequence in order to improve the control precisionThe number of the first D flip-flops 110 in the circuit 100 is too many, and the arrangement of more first D flip-flops 110 may complicate a circuit structure and signal processing, and increase a circuit volume and a signal processing time, so that the embodiment of the present invention has a simpler circuit structure and a faster signal processing speed on the basis of improving the accuracy of the pwm circuit.
With continued reference to fig. 4, optionally, the digital selection circuit 200 is 2 N : 1, selection control signal DS inputted from selection signal control terminal [N-1:0] Can be from 2 N And selecting and outputting the phase selection pulse signal from the candidate pulse signals.
With continued reference to fig. 4, based on the above embodiments, the delay trigger circuit 300 optionally includes a first time delay circuit 310 and a rising edge trigger circuit 320. The first input terminal of the first time delay circuit 310 serves as the selection phase input terminal 301 of the delay trigger circuit 300, and the second input terminal serves as the adjustment signal input terminal 302 of the delay trigger circuit 300. The input terminal of the rising edge trigger circuit 320 is electrically connected to the output terminal of the first time delay circuit 310, and the output terminal is used as the reset signal output terminal 303 of the delay trigger circuit 300. The delay trigger circuit 300 operates by selecting the phase pulse signal F output from the phase selection output terminal 203 of the digital selection circuit 200 D After being input to the first time delay circuit 310, the first time delay circuit 310 delays the phase of the selected phase pulse signal by an adjustable time F according to the first adjustment signal on the first adjustment signal line 30 D And outputs the delayed selective phase pulse signal F from the output terminal YD . The input terminal of the rising edge trigger circuit 320 receives the delayed selection phase pulse signal F YD And outputs a reset signal from a reset signal output terminal 303, and a trigger edge (rising edge or falling edge) of the reset signal and the delayed selection phase pulse signal F YD Are equal in phase. According to the embodiment of the invention, the delay trigger circuit 300 comprises the first time delay circuit 310 and the rising edge trigger circuit 320, so that a stable and reliable reset signal can be output at the reset signal output end 303.
With continued reference to fig. 4, on the basis of the above embodiments, optionally, the pulse width modulation circuit further includes a second time delay circuit 500. The second time delay circuit 500 has a first input terminal electrically connected to the phase comparison signal line 40 and an output terminal electrically connected to the second clock signal input terminal 401 of the pulse output circuit 400. The second time delay circuit 500 is arranged such that the delayed selection phase pulse signal F YD The phase comparison signal on the phase comparison signal line adopts a time delay difference obtaining mode, and the time delay difference of the second time delay circuit 500 and the first time delay circuit 310 in the delay trigger circuit 300 is used as the pulse width of the output signal, so that the error existing in the first time delay circuit is eliminated, and the modulation precision of the pulse width modulation circuit is further improved.
With continued reference to fig. 4, based on the above embodiments, the rising edge trigger circuit 320 optionally includes a first inverter, an amplifier, and a nand gate. The input of the first inverter serves as the input of the rising edge trigger circuit 320. The input end of the amplifier is electrically connected with the output end of the first inverter. The first input terminal of the nand gate is electrically connected to the output terminal of the amplifier, the second input terminal is electrically connected to the input terminal of the first inverter, and the output terminal is used as the output terminal of the rising edge trigger circuit 320, so as to select the phase pulse signal F according to the delayed selection phase pulse signal F YD The trigger pulse signal is output at the output of the rising edge trigger circuit 320.
With continued reference to fig. 4, based on the above embodiments, optionally, the pulse output circuit 400 includes a second D flip-flop. The trigger signal input terminal D of the second D flip-flop is electrically connected to the second power signal line 60, the clock pulse terminal Clk serves as a second clock signal input terminal 401 of the pulse output circuit 400, the reset terminal R serves as a reset signal input terminal 402 of the pulse output circuit 400, and the first output terminal Q serves as a pulse signal output terminal 403 of the pulse output circuit 400. That is, the second D flip-flop is a D flip-flop with a reset function, and the pulse output circuit 400 operates when the phase of the 0 phase signal F is 0 Y0 After the clock pulse is input to the clock pulse terminal Clk of the second D flip-flop, the first output terminal Q of the second D flip-flop outputs highLevel, passing delay time t c +t w Then, a reset signal is input to a reset end R of the second D trigger, and a first output end Q of the second D trigger outputs a low level, so that the output pulse width is t c +t w Of the signal of (1).
Fig. 5 is a circuit diagram of a first time delay circuit according to an embodiment of the invention. Referring to fig. 5, the first time delay circuit 310 includes a digital control circuit 311 and a phase conversion circuit 316. The digital control circuit 311 includes an input terminal and 2P output terminals, the input terminal of the digital control circuit 311 is used as the second input terminal of the first time delay circuit 310 (i.e. the adjustment signal input terminal 302 of the delay trigger circuit 300), and the digital control circuit 311 is configured to adjust the current magnitude output by the 2P output terminals according to the first adjustment signal input by the input terminal thereof. The phase conversion circuit 316 includes an input terminal, an output terminal, and 2P phase control terminals, the input terminal of the phase conversion circuit 316 is used as the first input terminal of the first time delay circuit 310 (the selective phase input terminal 301 of the delay trigger circuit 300), the output terminal is used as the output terminal of the first time delay circuit 310, the 2P phase control terminals are electrically connected to the output terminals of the corresponding digital control circuits 311, respectively, the phase conversion circuit 316 is configured to control the phase of the reset signal output from the output terminal thereof according to the magnitude of the current input from the phase control terminal; wherein P is a natural number.
With reference to fig. 5, based on the foregoing embodiments, optionally, the 2P output terminals of the digital control circuit 311 respectively include a first output terminal and a second output terminal, the 2P phase control terminals of the phase transformation circuit 316 respectively include a first phase control terminal and a second phase control terminal, the first phase control terminal is electrically connected to the corresponding first output terminal, and the second phase control terminal is electrically connected to the corresponding second output terminal. Illustratively, the digital control circuit 311 in fig. 5 includes 2 output terminals, wherein the first output terminal 3111 and the second output terminal 3112 constitute one output terminal of the digital control circuit 311, and the first output terminal 3113 and the second output terminal 3114 constitute another output terminal of the digital control circuit 311. Correspondingly, the phase converting circuit 316 includes 2 phase control terminals, wherein the first phase control terminal 3161 and the second phase control terminal 3162 form one phase control terminal of the phase converting circuit 316, and the first phase control terminal 3163 and the second phase control terminal 3164 form the other phase control terminal of the phase converting circuit 316. The first phase control terminal 3161 is electrically connected to the first output terminal 3111, the second phase control terminal 3162 is electrically connected to the second output terminal 3112, the first phase control terminal 3163 is electrically connected to the first output terminal 3113, and the second phase control terminal 3164 is electrically connected to the second output terminal 3114.
The digital control circuit 311 includes: a first resistor R a A first current mirror set 312, a second resistor R b A second current mirror group 313, a third current mirror group 314 and a fourth current mirror group 315. A first resistor R a Is electrically connected to the ground line. The control terminal of the first current mirror group 312 is electrically connected to the input terminal of the digital control circuit 311, the current input terminal is electrically connected to the first power signal line, and the first current output terminal is electrically connected to the first resistor R a The second end of the first current mirror is electrically connected, the second current output end of the first current mirror is electrically connected to the first current input end of the second current mirror, and the first current mirror group 312 is configured to adjust the magnitude of the current output by the current output end of the first current mirror according to the first adjustment signal. A second resistor R b Is electrically connected to the first power signal line. The first current input terminal of the second current mirror group 313 and the second resistor R b The second end of the current output end is electrically connected with the grounding wire. The third current mirror group 314 includes a current input terminal, a first current output terminal, a second current output terminal, and 2P third current output terminals, the current input terminal of the third current mirror group 314 is electrically connected to the first power signal line, the first current output terminal is electrically connected to the second current input terminal of the second current mirror group 313, and the 2P third current output terminals are electrically connected to the 2P first output terminals of the digital control circuit 311, respectively. The fourth current mirror group 315 includes a first current input terminal, a current output terminal, and 2P second current input terminals, the first current input terminal of the fourth current mirror group 315 is electrically connected to the second current output terminal of the third current mirror group 314, the 2P second current input terminals are respectively and correspondingly electrically connected to the 2P second output terminals of the digital control circuit 311, and the current output terminal is electrically connected to the ground line.
Exemplarily, a numberThe control circuit 311 has a control accuracy of M bits, where M is greater than or equal to 1. The digital control circuit 311 works in such a way that the current output from the first current output terminal of the first current mirror group 312 is I b The first current mirror group 312 is coupled to the first adjustment signal DT [M:1] Controlling the current output from the second current output terminal to be
A second resistor R b The current on the branch electrically connected to the first current input terminal of the second current mirror group 313 is I a According to kirchhoff's current law, the current flowing into the first current input terminal of the second current mirror group 313 is
The first current output terminal of the third current mirror group 314 outputs a current of
The current output by the 2P second current output terminals is
The current inputted from the first current input terminal of the fourth current mirror group 315 is
The current input by the 2P second current input terminals is
I.e. the digital control circuit 311 implements the regulation according to the first regulation signal DT [M:1] The current output by the output end of the power supply is adjusted.
With continued reference to fig. 5, optionally, the first current mirror group 312 includes a first transistor M P1 、2 M+1 A second transistor and 2 M+1 Switches (i.e. switches D1, … …, switch D2) M+1 ) First transistor M P1 Is shorted with the gate and is connected with the first resistor R a And a source is electrically connected to the first power signal line 70. 2 M+1 A second crystalThe grid electrodes of the transistors are all connected with the first transistor M P1 And the sources are both electrically connected to the first power signal line 70. 2 M+1 The first ends of the switches are respectively connected with 2 M+1 The drains of the second transistors are electrically connected, and the first ends of the second transistors are electrically connected to the second current output end of the first current mirror group 312. Wherein 2 M+1 A second transistor and a first transistor M P1 Form a (2) M+1 A current mirror, 2 M+1 The current output from the drain of the second transistor and the first transistor M P1 The currents output by the drains are equal. A first resistor R a And the first transistor M in the first current mirror group 312 P1 Form a current source with an output current of I b ，2 M+1 A switch control 2 M+1 Whether the current output by the drain of the second transistor flows into the second current mirror group 313. When the switch is turned off, the current of the second transistor corresponding to the switch cannot enter the second current mirror group 313, and when the switch is turned off, the current of the second transistor controlled by the switch enters the second current mirror group 313.
With continued reference to fig. 5, optionally, the third current mirror group 314 includes a third transistor M P2 A fourth transistor M P3 And 2P fifth transistors (exemplarily including 2 fifth transistors, respectively M, in FIG. 5) P4 And a transistor M P5 ) A third transistor M P2 A fourth transistor M P3 And a source of the fifth transistor are electrically connected to the first power supply signal line 70, and the third transistor M P2 A fourth transistor M P3 And the grid of the fifth transistor is connected with the third transistor M P2 Is electrically connected to the drain of the third transistor M P2 The drain of the first transistor M is used as the first current output terminal of the third current mirror group 314 P3 The drains of the second transistors are used as the second current output terminals of the third current mirror group 314, and the drains of the 2P fifth transistors are respectively used as the 2P third current output terminals of the third current mirror group 314. The fourth current mirror group 315 comprises a sixth transistor M N3 And 2P seventh transistors (exemplarily including 2 seventh transistors, respectively, transistors M in fig. 5) N4 And a transistor M N5 ) The sixth transistor M N3 And 2P seventh transistorsThe source electrodes are all electrically connected with the grounding wire, and the sixth transistor M N3 And 2P seventh transistors each having a gate connected to the sixth transistor M N3 Is electrically connected to the drain of the sixth transistor M N3 The drains of the seventh transistors are used as the first current input terminals of the fourth current mirror group 315, and the drains of the seventh transistors 2P are respectively used as the second current input terminals 2P of the fourth current mirror group 315. Wherein the fourth transistor M P3 And 2P drain output currents of the fifth transistors and the third transistor M P2 Is equal to the current output by the drain of the 2P seventh transistor, the current input by the drain of the seventh transistor is equal to the current input by the sixth transistor M N3 That is, the current output from the first output terminal 3111 is equal to the current input from the second output terminal 3112, and the current output from the first output terminal 3113 is equal to the current input from the second output terminal 3114, both of which are equal to each other
With continued reference to fig. 5, optionally, the digital control circuit 311 further includes a binary to thermometer circuit 307, and the binary to thermometer circuit 307 is configured to convert the binary code on the first adjustment signal into a thermometer code, so as to improve the control accuracy of the digital control circuit 311.
Alternatively, the first time delay circuit 310 and the second time delay circuit 500 have the same circuit structure, and in the second time delay circuit 500, the selection control signal controls the delay time to be 0.
With continuing reference to fig. 5, based on the above embodiments, the phase transformation circuit 316 optionally includes 2P inverters (exemplarily including 2 inverters in fig. 5) connected in series. The input terminal of the 1 st inverter is used as the input terminal of the phase transformation circuit 316, and the output terminal of the 2P th inverter is used as the output terminal of the phase transformation circuit 316. The control terminals of the 2P inverters are respectively used as 2P phase control terminals of the phase converting circuit 316. The inverter has time delay in the process of inverting the input signal, the time delay is determined by the size of current which is input into the control end of the inverter, and the larger the current is, the smaller the time delay is. The time delay formula of the phase conversion circuit 316 can be expressed as follows:
wherein, C L Is a load capacitance of an inverter, V DD Is the supply voltage on the first power supply signal line 70.
Since the first time delay circuit 310 and the second time delay circuit 500 are included in the embodiment of the present invention, by using the time delay difference between the second time delay circuit 500 and the first time delay circuit 310 in the delay trigger circuit 300 as the pulse width of the output signal, specifically, when duty ratio fine adjustment is performed, the phase delay time of the selected phase pulse signal can be expressed by the following equation:
in the formula (2), the second term is the inherent error of the time delay circuit, that is, the second time delay circuit is arranged to eliminate the error existing in the first time delay circuit, and further improve the modulation precision of the pulse width modulation circuit.
The embodiment of the invention also provides a digital pulse width modulation device. The digital pulse width modulation device comprises a pulse width modulation circuit provided by any embodiment of the invention. The digital pulse width modulation device may be, for example, a lighting control system or a DC-DC converter. The display device comprises the pulse width modulation circuit provided by any embodiment of the invention, the technical principle and the generated technical effect are similar, and the description is omitted here.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A pulse width modulation circuit, comprising:
the time sequence control circuit comprises a first clock signal input end and a plurality of alternative phase output ends, wherein the first clock signal input end is electrically connected with a clock signal line, and the time sequence control circuit is used for outputting alternative pulse signals with sequentially delayed phases at the alternative phase output ends according to an input clock signal on the clock signal line;
the digital selection circuit comprises a selection signal control end, a plurality of alternative phase input ends and a selection phase output end, wherein the selection signal control end is electrically connected with the selection signal line, the alternative phase input ends are respectively and electrically connected with the corresponding alternative phase output ends, and the digital selection circuit is used for outputting a selection phase pulse signal at the selection phase output end according to a selection control signal on the selection signal line;
the delay trigger circuit comprises a selection phase input end, an adjusting signal input end and a reset signal output end, wherein the selection phase input end is electrically connected with the selection phase output end, the adjusting signal input end is electrically connected with a first adjusting signal line, and the delay trigger circuit is used for delaying the selection phase pulse signal for an adjustable time according to a first adjusting signal on the first adjusting signal line and outputting a reset signal from the reset signal output end;
the pulse output circuit comprises a second clock signal input end, a reset signal input end and a pulse signal output end, wherein the second clock signal input end is electrically connected with the phase comparison signal line, the reset signal input end is electrically connected with the reset signal output end, the pulse signal output end is electrically connected with the pulse output signal line, and the pulse output circuit is used for controlling the duty ratio of the pulse signal output by the pulse signal output end according to the phase comparison signal input by the phase comparison signal line and the reset signal input by the reset signal input end;
the delay trigger circuit includes: a first time delay circuit, wherein a first input end of the first time delay circuit is used as a selection phase input end of the delay trigger circuit, and a second input end of the first time delay circuit is used as an adjustment signal input end of the delay trigger circuit;
the first time delay circuit includes: the phase conversion circuit comprises an input end, an output end and 2P phase control ends, wherein the input end of the phase conversion circuit is used as the first input end of the first time delay circuit, the output end of the phase conversion circuit is used as the output end of the first time delay circuit, the 2P phase control ends are respectively and electrically connected with the output ends of the corresponding digital control circuits, and the phase conversion circuit is used for controlling the phase of a reset signal output by the output end of the phase conversion circuit according to the current input by the phase control end; wherein P is a natural number.
2. The pwm circuit according to claim 1, wherein the timing control circuit comprises 2 N-1 A first D trigger, N is an integer and N is more than or equal to 2;
2 is described N-1 Clock pulse ends of the first D flip-flops are electrically connected to the clock signal line, 2 N-1 The first output end and the second output end of a first D trigger are used as alternative phase output ends of the sequential control circuit, and the triggering signal input end and the 2 nd triggering signal input end of the 1 st first D trigger N-1 The second output end of the first D trigger is electrically connected, the trigger signal input end of the ith first D trigger is electrically connected with the first output end of the i-1 th first D trigger, and i is more than or equal to 2 and less than or equal to 2 N-1 。
3. The pulse width modulation circuit of claim 1, wherein the delay trigger circuit further comprises:
and the input end of the rising edge trigger circuit is electrically connected with the output end of the first time delay circuit, and the output end of the rising edge trigger circuit is used as the reset signal output end of the delay trigger circuit.
4. The pulse width modulation circuit of claim 1, wherein the first time delay circuit further comprises:
and the digital control circuit comprises an input end and 2P output ends, the input end of the digital control circuit is used as the second input end of the first time delay circuit, and the digital control circuit is used for adjusting the current output by the 2P output ends according to a first adjusting signal input by the input end of the digital control circuit.
5. The PWM circuit according to claim 1 or 4, wherein the 2P outputs of the digital control circuit respectively comprise a first output and a second output, the 2P phase control terminals of the phase transformation circuit respectively comprise a first phase control terminal and a second phase control terminal, the first phase control terminal is electrically connected with the first output terminal of the corresponding digital control circuit, and the second phase control terminal is electrically connected with the second output terminal of the corresponding digital control circuit;
the digital control circuit includes: the first resistor, the first current mirror group, the second resistor, the second current mirror group, the third current mirror group and the fourth current mirror group;
the first end of the first resistor is electrically connected with a grounding wire;
the control end of the first current mirror group is electrically connected with the input end of the digital control circuit, the current input end is electrically connected with the first power signal wire, the first current output end is electrically connected with the second end of the first resistor, the second current output end is electrically connected with the first current input end of the second current mirror, and the first current mirror group is used for adjusting the current output by the current output end according to the first adjusting signal;
a first end of the second resistor is electrically connected to the first power signal line;
a first current input end of the second current mirror group is electrically connected with a second end of the second resistor, and a current output end of the second current mirror group is electrically connected with the grounding wire;
the third current mirror group comprises a current input end, a first current output end, a second current output end and 2P third current output ends, the current input end of the third current mirror group is electrically connected with the first power signal wire, the first current output end is electrically connected with the second current input end of the second current mirror group, and the 2P third current output ends are respectively and correspondingly electrically connected with the 2P first output ends of the digital control circuit;
the fourth current mirror group comprises a first current input end, a current output end and 2P second current input ends, the first current input end of the fourth current mirror group is electrically connected with the second current output end of the third current mirror group, the 2P second current input ends are respectively and correspondingly electrically connected with the 2P second output ends of the digital control circuit, and the current output ends are electrically connected with the grounding wire.
6. The pulse width modulation circuit of claim 1, wherein the phase transformation circuit comprises 2P series-connected inverters;
the input end of the 1 st inverter is used as the input end of the phase transformation circuit, and the output end of the 2P th inverter is used as the output end of the phase transformation circuit;
and the control ends of the 2P inverters are respectively used as 2P phase control ends of the phase transformation circuit.
7. The pulse width modulation circuit of claim 3, wherein the rising edge trigger circuit comprises:
the input end of the first inverter is used as the input end of the rising edge trigger circuit;
an amplifier, an input end of the amplifier being electrically connected to an output end of the first inverter;
and the first input end of the NAND gate is electrically connected with the output end of the amplifier, the second input end of the NAND gate is electrically connected with the input end of the first phase inverter, and the output end of the NAND gate is used as the output end of the rising edge trigger circuit.
8. The pulse width modulation circuit of claim 1, further comprising a second time delay circuit;
and a first input end of the second time delay circuit is electrically connected with the phase comparison signal line, and an output end of the second time delay circuit is electrically connected with a second clock signal input end of the pulse output circuit.
9. The pulse width modulation circuit of claim 1, wherein the pulse output circuit comprises a second D flip-flop;
the trigger signal input end of the second D trigger is electrically connected with the second power signal wire, the clock pulse end is used as the second clock signal input end of the pulse output circuit, the reset end is used as the reset signal input end of the pulse output circuit, and the first output end is used as the pulse signal output end of the pulse output circuit.
10. A digital pulse width modulation device, comprising: the pulse width modulation circuit of any one of claims 1-9.
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| EP1794872A1 (en) * | 2004-10-01 | 2007-06-13 | Aleksandar Prodic | A digital controller for dc-dc switching converters for operation at ultra-high constant switching frequencies |
| CN102394643A (en) * | 2011-11-16 | 2012-03-28 | 东南大学 | Digital pulse width modulator based on digital delayed-locked loop (DLL) |
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| EP1794872A1 (en) * | 2004-10-01 | 2007-06-13 | Aleksandar Prodic | A digital controller for dc-dc switching converters for operation at ultra-high constant switching frequencies |
| CN102394643A (en) * | 2011-11-16 | 2012-03-28 | 东南大学 | Digital pulse width modulator based on digital delayed-locked loop (DLL) |
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