CN109302166A - A kind of pulse width modulation circuit and device - Google Patents
A kind of pulse width modulation circuit and device Download PDFInfo
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- CN109302166A CN109302166A CN201811041822.9A CN201811041822A CN109302166A CN 109302166 A CN109302166 A CN 109302166A CN 201811041822 A CN201811041822 A CN 201811041822A CN 109302166 A CN109302166 A CN 109302166A
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- 210000001367 artery Anatomy 0.000 claims description 8
- 210000003462 vein Anatomy 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 10
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- 229910002056 binary alloy Inorganic materials 0.000 description 2
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
- H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K7/00—Modulating pulses with a continuously-variable modulating signal
- H03K7/08—Duration or width modulation ; Duty cycle modulation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/40—Control techniques providing energy savings, e.g. smart controller or presence detection
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Abstract
The invention discloses a kind of pulse width modulation circuit and devices.The pulse width modulation circuit includes sequential control circuit, digital selection circuit, delay trigger circuit and impulse output circuit, the selection signal control terminal of digital selection circuit is electrically connected with selection signal line, multiple alternative phase inputs are respectively with corresponding multiple alternative phase output electrical connections, and digital selection circuit is according to the selection control signal on selection signal line in selected phase output end one selected phase pulse signal of output；And the selected phase input terminal of delay trigger circuit is electrically connected with selected phase output end, adjustment signal input terminal is electrically connected with the first adjustment signal line, postpone trigger circuit according to the first adjustment signal on the first adjustment signal line for one time regulatable of delay of selected phase pulse signal, and from reset signal output end output reset signal.Coarse adjustment and fine tuning of the present invention Jing Guo duty ratio effectively increase the precision of pulse width modulation circuit.
Description
Technical field
The present embodiments relate to electronic technology field more particularly to a kind of pulse width modulation circuits and device.
Background technique
The major function of digital pulsewidth modulation (Digital Pulse Width Modulation, DPWM) circuit is
The digital controlled signal of input is converted to the pulse signal of corresponding pulse width.If the frequency of the pulse signal is fixed,
The adjusting of pulse-width can realize the duty ratio for adjusting the pulse signal.
DPWM circuit is widely used in electronic technology field, for example, different accounts in lighting control system
The sky brightness more different than correspondence, may be implemented to the digital control of illumination system brightness by DPWM circuit, for another example, in direct current pair
In direct current (DC-DC) converter, different duty ratios corresponds to different output voltages, may be implemented by DPWM circuit to DC-
DC converter it is digital control.However, the resolution ratio that existing DPWM circuit carries out duty cycle adjustment is lower, it is unable to satisfy essence
Spend the demand of higher duty cycle adjustment.
Summary of the invention
The present invention provides a kind of pulse width modulation circuit and device, to realize the precision for improving duty cycle adjustment.
In a first aspect, the embodiment of the invention provides a kind of pulse width modulation circuit, the pulse width modulation circuit
Include:
Sequential control circuit, the sequential control circuit include the first clock signal input terminal and multiple alternative phase outputs
End, first clock signal input terminal are electrically connected with clock cable, and the sequential control circuit is used for according to the clock
The alternative pulse signal that input clock signal on signal wire successively postpones in the multiple alternative phase output output phase；
Digital selection circuit, the digital selection circuit include selection signal control terminal, multiple alternative phase inputs and
One selected phase output end, the selection signal control terminal are electrically connected with selection signal line, the multiple alternative phase input
End is respectively with corresponding the multiple alternative phase output electrical connection, and the digital selection circuit is for according to selection signal line
On selection control signal the selected phase output end export a selected phase pulse signal；
Postpone trigger circuit, the delay trigger circuit includes selected phase input terminal, adjustment signal input terminal and resets
Signal output end, the selected phase input terminal are electrically connected with the selected phase output end, the adjustment signal input terminal with
The electrical connection of first adjustment signal line, the delay trigger circuit, which is used to be adjusted according to first on the first adjustment signal line, to be believed
Number by one time regulatable of selected phase pulse delay signal, and from the reset signal output end output reset signal；
Impulse output circuit, the impulse output circuit include second clock signal input part, reset signal input terminal and
Pulse signal output end, the second clock signal input part are electrically connected with comparison of signal phase line, the reset signal input
End is electrically connected with the reset signal output end, and the pulse signal output end is electrically connected with pulse output signals line, the arteries and veins
It is defeated to rush comparison of signal phase and the reset signal input terminal of the output circuit for inputting according to the comparison of signal phase line
The reset signal entered controls the duty ratio of the pulse signal of the pulse signal output end output.
Second aspect, the embodiment of the invention also provides a kind of digital pulsewidth modulation device, the digit pulse is wide
Spending modulating device includes such as pulse width modulation circuit provided by any embodiment of the invention.
The present invention is electrically connected by the selection signal control terminal of setting digital selection circuit with selection signal line, multiple alternative
Phase inputs are respectively with corresponding multiple alternative phase output electrical connections, and digital selection circuit is according on selection signal line
Selection control signal exports a selected phase pulse signal in selected phase output end；And the selection phase of delay trigger circuit
Position input terminal is electrically connected with selected phase output end, and adjustment signal input terminal is electrically connected with the first adjustment signal line, delay triggering
Circuit according to the first adjustment signal on the first adjustment signal line by one time regulatable of selected phase pulse delay signal, and from multiple
Position signal output end output reset signal, compared with prior art, the embodiment of the present invention realizes multiple Selecting phasings and time
Postpone coefficient pulse width modulation circuit, i.e. the coarse adjustment Jing Guo duty ratio and fine tuning effectively increases pulse width modulation
The precision of circuit.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of pulse width modulation circuit provided in an embodiment of the present invention；
Fig. 2 is a kind of timing diagram of pulse width modulation circuit provided in an embodiment of the present invention；
Fig. 3 is that a kind of duty ratio of pulse width modulation circuit provided in an embodiment of the present invention exports schematic diagram；
Fig. 4 is the structural schematic diagram of another pulse width modulation circuit provided in an embodiment of the present invention；
Fig. 5 is a kind of circuit diagram of first time delay circuit provided in an embodiment of the present invention.
Specific embodiment
The present invention is described in further detail with reference to the accompanying drawings and examples.It is understood that this place is retouched
The specific embodiment stated is used only for explaining the present invention rather than limiting the invention.It also should be noted that in order to just
Only the parts related to the present invention are shown in description, attached drawing rather than entire infrastructure.
The embodiment of the invention provides a kind of pulse width modulation circuits.Illustratively, Fig. 1 provides for the embodiment of the present invention
A kind of pulse width modulation circuit structural schematic diagram.Referring to Fig. 1, which includes: timing control electricity
Road 100, digital selection circuit 200, delay trigger circuit 300 and impulse output circuit 400.Sequential control circuit 100 includes the
One clock signal input terminal 101 and multiple alternative phase outputs 102 (illustratively include 8 alternative phase outputs in Fig. 1
102, i.e. 8 phase sequential exports), the first clock signal input terminal 101 is electrically connected with clock cable 10.Sequential control circuit
100 according to the input clock signal on clock cable 10 in multiple alternative 102 output phases of phase output for successively prolonging
Slow alternative pulse signal.Digital selection circuit 200 includes selection signal control terminal 201, multiple alternative phase inputs 202
(illustratively including 8 alternative phase inputs 202 in Fig. 1) and a selected phase output end 203, selection signal control terminal
201 are electrically connected with selection signal line 20, multiple alternative phase inputs 202 respectively with corresponding multiple alternative phase outputs
102 electrical connections.Digital selection circuit 200 is used for according to the selection control signal on selection signal line 20 in selected phase output end
203 one selected phase pulse signal of output.Postponing trigger circuit 300 includes selected phase input terminal 301, adjustment signal input
End 302 and reset signal output end 303, selected phase input terminal 301 are electrically connected with selected phase output end 203, adjustment signal
Input terminal 302 is electrically connected with the first adjustment signal line 30.Postpone trigger circuit 300 to be used for according on the first adjustment signal line 30
One time regulatable of selected phase pulse delay signal is exported from reset signal output end 303 and resets letter by the first adjustment signal
Number.Impulse output circuit 400 includes second clock signal input part 401, reset signal input terminal 402 and pulse signal output end
403, second clock signal input part 401 is electrically connected with comparison of signal phase line 40, reset signal input terminal 402 and reset signal
Output end 303 is electrically connected, and pulse signal output end 403 is electrically connected with pulse output signals line 50.Impulse output circuit 400 is used for
The reset signal that the comparison of signal phase and reset signal input terminal 402 inputted according to comparison of signal phase line 40 inputs controls arteries and veins
Rush the duty ratio of the pulse signal of the output of signal output end 403.
Illustratively, Fig. 2 is a kind of timing diagram of pulse width modulation circuit provided in an embodiment of the present invention.Referring to Fig. 1
And Fig. 2, the course of work of the pulse width modulation circuit are that sequential control circuit 100 is according to the input on clock cable 10
The alternative pulse signal that clock signal successively postpones in multiple alternative 102 output phases of phase output, and adjacent phase is standby
Select the phase difference of pulse signal equal, that is, the time difference postponed is equal.By taking the alternative pulse signal of 8 phases as an example, phase difference is
45 °, the phase of 8 alternative pulse signals is followed successively by 0 °, 45 °, 90 °, 135 °, 180 °, 225 °, 270 ° and 315 °.Number selection
Circuit 200 exports a selected phase arteries and veins in selected phase output end 203 according to the selection control signal on selection signal line 20
Rush signal FD, illustratively have selected in Fig. 2 the alternative pulse signal of third (i.e. phase be 135 ° alternative pulse signal, with
0th alternative pulse signal is compared, and the time of delay is tc), to carry out initial option to multiple phases, realize duty ratio
Coarse adjustment.Postpone trigger circuit 300 according to the first adjustment signal on the first adjustment signal line 30 for selected phase pulse signal FD
Postpone a time regulatable tw, selected phase pulse signal F after being postponedYD, and export and reset from reset signal output end 303
Signal, i.e., to selected phase pulse signal FDControllable time delay, and the fine tuning time as pulse-width modulator are carried out,
Realize the fine tuning of duty ratio.Optionally, selected phase pulse signal FDMaximum delay time be two neighboring alternative pulse letter
Number the phase difference corresponding time.Illustratively, the selected phase pulse signal F of pulse width modulation circuit as shown in Figure 1D
The range minimum of delay time can correspond to 0 °~45 ° of phase, may insure the fine tuning of pulse width modulation circuit in this way
The duty ratio of range all standing 0~1.Optionally, comparison of signal phase line 40 and 0 phase signal of sequential control circuit 100 are standby
Pulse signal output end is selected to be electrically connected, so that the alternative pulse signal of 0 phase signal inputs second clock signal input part 401.Arteries and veins
Rush the 0 phase signal F that output circuit 400 is inputted according to second clock signal input part 401Y0It is defeated with reset signal input terminal 402
The pulse signal that the reset signal control wave output end 403 entered exports.Wherein, the selected phase pulse signal after delay
FYDWith 0 phase signal FY0Between have a fixed phase difference, constitute output pulse signal output time span be tc+
tw, duty ratio is (tc+tw)/T, wherein T is the period of output pulse signal.Specifically, it can be incited somebody to action by the coarse adjustment of duty ratio
Reset signal delay time tc, reset signal can be continued by delay time t by the fine tuning of duty ratiow.If reset signal is not prolonged
The duty ratio of slow available output pulse signal is 0, if by the available output of time T of reset signal delay a cycle
The duty ratio of pulse signal is 1.
Fig. 3 is that a kind of duty ratio of pulse width modulation circuit provided in an embodiment of the present invention exports schematic diagram.Referring to figure
3, point A, point B, point C, point D, point E, point F, point G and point H are respectively only accounted for by coarse adjustment what pulse signal output end 403 exported
Empty ratio, the duty ratio between each point export by coarse adjustment and fine tuning in pulse signal output end 403, it can be seen that, it is of the invention
Embodiment realizes the duty cycle trimmer in all phase by coarse adjustment and fine tuning.
The selection signal control terminal 201 and selection signal line 20 that the embodiment of the present invention passes through setting digital selection circuit 200
Electrical connection, multiple alternative phase inputs 202 are electrically connected with corresponding multiple alternative phase outputs 102 respectively, number selection
Circuit 200 exports a selected phase arteries and veins in selected phase output end 203 according to the selection control signal on selection signal line 20
Rush signal；And the selected phase input terminal 301 of delay trigger circuit 300 is electrically connected with selected phase output end 203, adjusts letter
Number input terminal 302 is electrically connected with the first adjustment signal line 30, and delay trigger circuit 300 is according to the on the first adjustment signal line 30
One adjustment signal is by one time regulatable of selected phase pulse delay signal, and from 303 output reset signal of reset signal output end,
Compared with prior art, the embodiment of the present invention realizes multiple Selecting phasings and the coefficient pulse width of time delay is modulated
The precision that circuit, the i.e. coarse adjustment Jing Guo duty ratio and fine tuning effectively increase pulse width modulation circuit.
Fig. 4 is the structural schematic diagram of another pulse width modulation circuit provided in an embodiment of the present invention.Referring to fig. 4, exist
On the basis of the various embodiments described above, optionally, sequential control circuit 100 includes 2N-1A first d type flip flop 110, N are integer and N
≥2。2N-1The clock pulse terminal of a first d type flip flop 110 is electrically connected with clock cable 10, and 2N-1A first d type flip flop 110
Alternative phase output 102 as sequential control circuit 100 of the first output end Q and second output terminal Qb, the 1st the first D
The trigger signal input terminal D of trigger 110 and the 2ndN-1The second output terminal Qb of a first d type flip flop 110 is electrically connected, and i-th the
The trigger signal input terminal D of one d type flip flop 110 is electrically connected with the first output end Q of (i-1)-th the first d type flip flop 110,2≤i
≤2N-1.The course of work of the sequential control circuit 100 is that the clock signal on clock cable 10 enters sequential control circuit
After 100, by 2N-1The circuit that a first d type flip flop 110 forms is N bit timing control circuit, since the first d type flip flop 110 includes
First output end Q and second output terminal Qb, and the opposite in phase of the first output end Q and second output terminal Qb output is (for example, the 1st
The phase of the alternative pulse signal of the first output end Q output of a first d type flip flop 110 is 0 °, second output terminal Qb output
The phase of alternative pulse signal is 180 °), therefore, this 2N-1The circuit that a first d type flip flop 110 forms is N bit timing control electricity
Road can produce 2NA alternative pulse signal, and multiple alternative pulse signals have fixed phase difference, and the first d type flip flop
110 quantity determines the coarse adjustment precision of pulse width modulationmodulator.The value of phase difference by the first d type flip flop 110 quantity
It determines, by taking N=3 as an example, the quantity of the first d type flip flop 110 is 4, and the quantity of alternative pulse signal is 8, and phase difference is
45°.The embodiment of the present invention includes 2 by setting sequential control circuit 100N-1A first d type flip flop 110, realizes 2NIt is a alternative
The output of pulse signal, and 2NPhase difference between a alternative pulse signal is equal, further improves pulse width modulation electricity
The precision on road.In addition, the embodiment of the present invention is also finely adjusted after coarse adjustment, without controlling precision for timing control to be promoted
The quantity setting of the first d type flip flop 110 in circuit 100 is excessive, and more 110 meeting of the first d type flip flop is arranged so that circuit
Structure and signal processing are complicated, increase the volume and signal processing time of circuit, therefore, the embodiment of the present invention is improving arteries and veins
It rushes on the basis of the precision of width modulation circuit, there is simpler circuit structure and faster conversion speed.
With continued reference to Fig. 4, optionally, digital selection circuit 200 is 2N: 1 digital selection circuit, selection signal control terminal
The selection of input controls signal DS[N-1:0]It can be from 2NSelected phase pulse signal is selected in a alternative pulse signal and is exported.
With continued reference to Fig. 4, on the basis of the various embodiments described above, optionally, delay trigger circuit 300 includes at the first time
Delay circuit 310 and rising edge trigger circuit 320.The first input end of first time delay circuit 310 is as delay triggering electricity
The selected phase input terminal 301 on road 300, adjustment signal input terminal 302 of second input terminal as delay trigger circuit 300.On
The input terminal risen along trigger circuit 320 is electrically connected with the output end of first time delay circuit 310, and output end is as delay triggering
The reset signal output end 303 of circuit 300.The course of work of the delay trigger circuit 300 is the choosing of digital selection circuit 200
Select the selected phase pulse signal F of the output of phase output 203DAfter inputting first time delay circuit 310, postpone at the first time
Circuit 310 is adjustable by the phase delay one of selected phase pulse signal according to the first adjustment signal on the first adjustment signal line 30
Time FDPhase, and from output end output delay after selected phase pulse signal FYD.The input of rising edge trigger circuit 320
End receives the selected phase pulse signal F after the delayYD, and from 303 output reset signal of reset signal output end, and the reset
Selected phase pulse signal F of the triggering of signal after (rising edge or failing edge) and delayYDPhase it is equal.The present invention is implemented
Example includes first time delay circuit 310 and rising edge trigger circuit 320 by setting delay trigger circuit 300, can be multiple
Position signal output end 303 exports reliable and stable reset signal.
With continued reference to Fig. 4, on the basis of the various embodiments described above, optionally, which further includes
Two time delay circuits 500.The first input end of second time delay circuit 500 is electrically connected with comparison of signal phase line 40, defeated
Outlet is electrically connected with the second clock signal input part 401 of impulse output circuit 400.Second time delay circuit 500 is set in this way
It sets, so that the selected phase pulse signal F after delayYDTime delay is used with the comparison of signal phase on comparison of signal phase line
The acquisition modes of difference utilize the second time delay circuit 500 and the first time delay circuit 310 in delay trigger circuit 300
Pulse width of the time delay difference as output signal, eliminate error present in first time delay circuit, further
Improve the modulation accuracy of pulse width modulation circuit.
With continued reference to Fig. 4, on the basis of the various embodiments described above, optionally, rising edge trigger circuit 320 includes first anti-
Phase device, amplifier and NAND gate.Input terminal of the input terminal of first phase inverter as rising edge trigger circuit 320.Amplifier
Input terminal is electrically connected with the output end of the first phase inverter.The first input end of NAND gate is electrically connected with the output end of amplifier, the
Two input terminals are electrically connected with the input terminal of the first phase inverter, output end of the output end as rising edge trigger circuit 320, with basis
Selected phase pulse signal F after delayYDStart pulse signal is exported in the output end of rising edge trigger circuit 320.
With continued reference to Fig. 4, on the basis of the various embodiments described above, optionally, impulse output circuit 400 is touched including the 2nd D
Send out device.The trigger signal input terminal D of second d type flip flop is electrically connected with second source signal wire 60, and clock pulse terminal Clk is as arteries and veins
The second clock signal input part 401 of output circuit 400 is rushed, reset terminal R is inputted as the reset signal of impulse output circuit 400
End 402, pulse signal output end 403 of the first output end Q as impulse output circuit 400.That is the second d type flip flop is a tool
The d type flip flop of standby function of reset, illustratively, the course of work of the impulse output circuit 400 is, as 0 phase signal FY0Input
To the clock pulse terminal Clk of the second d type flip flop, the first output end Q of the second d type flip flop exports high level, when by delay
Between tc+twAfterwards, reset signal is input to the reset terminal R of the second d type flip flop, and the first output end Q of the second d type flip flop exports low electricity
It is flat, to realize that output pulse width is tc+twSignal.
Fig. 5 is a kind of circuit diagram of first time delay circuit provided in an embodiment of the present invention.Referring to Fig. 5, at the first time
Delay circuit 310 includes digital control circuit 311 and phase shift circuitry 316.Digital control circuit 311 includes input terminal and 2P
A output end, the input terminal of digital control circuit 311 is as (the i.e. delay triggering of 310 second input terminal of first time delay circuit
The adjustment signal input terminal 302 of circuit 300), digital control circuit 311 is used for the first adjustment signal inputted according to its input terminal
Adjust the size of current of 2P output end output.Phase shift circuitry 316 includes input, output end and 2P phase controlling
End, first input end (delay trigger circuit 300 of the input terminal of phase shift circuitry 316 as first time delay circuit 310
Selected phase input terminal 301), output end of the output end as first time delay circuit 310,2P phase controlling end difference
It is electrically connected with the output end of corresponding digital control circuit 311, what phase shift circuitry 316 was used to be inputted according to phase controlling end
Size of current controls the phase of the reset signal of its output end output；Wherein, P is natural number.
With continued reference to Fig. 5, on the basis of the various embodiments described above, optionally, 2P output end of digital control circuit 311
The first output end and second output terminal are respectively included, 2P phase controlling end of phase shift circuitry 316 respectively includes the first phase
Position control terminal and second phase control terminal, first phase control terminal are electrically connected with corresponding first output end, second phase control
End is electrically connected with corresponding second output terminal.Illustratively, the digital control circuit 311 in Fig. 5 includes 2 output ends, wherein
First output end 3111 and second output terminal 3112 constitute an output end of digital control circuit 311, the first output end 3113
The another output of digital control circuit 311 is constituted with second output terminal 3114.Correspond ground, phase shift circuitry
316 include 2 phase controlling ends, wherein first phase control terminal 3161 and second phase control terminal 3162 constitute phse conversion
One phase controlling end of circuit 316, first phase control terminal 3163 and second phase control terminal 3164 constitute phse conversion electricity
Another phase controlling end on road 316.And first phase control terminal 3161 is electrically connected with the first output end 3111, second phase
Control terminal 3162 is electrically connected with second output terminal 3112, and first phase control terminal 3163 is electrically connected with the first output end 3113, the
The electrical connection of 3164 second output terminal 3114 of two phase control terminal.
Digital control circuit 311 includes: first resistor Ra, the first electric current microscope group 312, second resistance Rb, the second electric current microscope group
313, third electric current microscope group 314 and the 4th electric current microscope group 315.First resistor RaFirst end with ground line be electrically connected.First electricity
The control terminal of stream microscope group 312 is electrically connected with the input terminal of digital control circuit 311, current input terminal and the first power signal line electricity
Connection, the first current output terminal and first resistor RaSecond end electrical connection, the of the second current output terminal and the second current mirror
The electrical connection of one current input terminal, the first electric current microscope group 312 are used to adjust the output of its current output terminal according to the first adjustment signal
Size of current.Second resistance RbFirst end be electrically connected with the first power signal line.First electric current of the second electric current microscope group 313 is defeated
Enter end and second resistance RbSecond end electrical connection, current output terminal be grounded be electrically connected.Third electric current microscope group 314 includes electricity
Input terminal, the first current output terminal, the second current output terminal and 2P third current output terminal are flowed, third electric current microscope group 314
Current input terminal is electrically connected with the first power signal line, and the first current output terminal and the second electric current of the second electric current microscope group 313 are defeated
Enter end electrical connection, the electrical connection corresponding with the 2P of digital control circuit 311 the first output ends respectively of 2P third current output terminal.
4th electric current microscope group 315 includes the first current input terminal, current output terminal and 2P the second current input terminal, the 4th electric current microscope group
315 the first current input terminal is electrically connected with the second current output terminal of third electric current microscope group 314,2P the second current input terminals
Electrical connection corresponding with 2P second output terminal of digital control circuit 311, current output terminal are electrically connected with ground line respectively.
Illustratively, the control precision of digital control circuit 311 is M, M >=1.The work of the digital control circuit 311
Process is that the electric current of the first current output terminal output of the first electric current microscope group 312 is Ib, the first electric current microscope group 312 is according to first
Adjustment signal DT[M:1], controlling the electric current that the second current output terminal exports isSecond resistance RbWith the second electricity
The electric current for flowing the branch road of the first current input terminal electrical connection of microscope group 313 is Ia, according to Kirchhoff's current law (KCL), flow into the
The electric current of first current input terminal of two electric current microscope groups 313 isFirst electricity of third electric current microscope group 314
Flowing the electric current that output end exports isThe electric current of 2P the second current output terminals output is4th electric current microscope group 315 the first current input terminal input electric current be
The electric current of 2P the second current input terminals input isI.e. the digital control circuit 311 realizes basis
First adjustment signal DT[M:1]Adjust the size of current of its output end output.
With continued reference to Fig. 5, optionally, the first electric current microscope group 312 includes the first transistor MP1、2M+1A second transistor and
2M+1A switch (i.e. switch D1 ... ..., switch D2M+1), the first transistor MP1Drain and gate be shorted, and with first resistor Ra
Second end electrical connection, source electrode is electrically connected with the first power signal line 70.2M+1The grid of a second transistor is and first crystal
Pipe MP1Grid electrical connection, source electrode is electrically connected with the first power signal line 70.2M+1The first end of a switch is respectively with 2M+1It is a
The drain electrode of second transistor is electrically connected, and first end is electrically connected with the second current output terminal of the first electric current microscope group 312.Wherein,
2M+1A second transistor and the first transistor MP1Constitute 2M+1A current mirror, 2M+1The electricity of the drain electrode output of a second transistor
Stream and the first transistor MP1The electric current exported that drains is equal.First resistor RaWith the first transistor in the first electric current microscope group 312
MP1Current source is constituted, output electric current is Ib, 2M+1A switch control 2M+1Whether the electric current of the drain electrode output of a second transistor flows
Enter the second electric current microscope group 313.When the switches are opened, the electric current of the corresponding second transistor of the switch cannot be introduced into the second current mirror
Group 313, when the switch is closed, the electric current of the second transistor of the switch control enter the second electric current microscope group 313.
With continued reference to Fig. 5, optionally, third electric current microscope group 314 includes third transistor MP2, the 4th transistor MP3And 2P
A 5th transistor (illustratively includes 2 the 5th transistors, respectively transistor M in Fig. 5P4With transistor MP5), third is brilliant
Body pipe MP2, the 4th transistor MP3It is electrically connected with the first power signal line 70 with the source electrode of the 5th transistor, third transistor
MP2, the 4th transistor MP3With the grid of the 5th transistor with third transistor MP2Drain electrode electrical connection, third transistor MP2's
The first current output terminal to drain as third electric current microscope group 314, the 4th transistor MP3Drain electrode as third electric current microscope group 314
The second current output terminal, the drain electrode of 2P the 5th transistors is defeated respectively as 2P third electric current of third electric current microscope group 314
Outlet.4th electric current microscope group 315 includes the 6th transistor MN3It (illustratively include 2 the 7th in Fig. 5 with 2P the 7th transistors
Transistor, respectively transistor MN4With transistor MN5), the 6th transistor MN3With the source electrode of 2P the 7th transistor with ground connection
Line electrical connection, the 6th transistor MN3With the grid of 2P the 7th transistor with the 6th transistor MN3Drain electrode electrical connection, the 6th
Transistor MN3First current input terminal of the drain electrode as the 4th electric current microscope group 315, the drain electrode of a 7th transistors of 2P makees respectively
For 2P the second current input terminals of the 4th electric current microscope group 315.Wherein, the 4th transistor MP3With the drain electrode of 2P the 5th transistors
The electric current and third transistor M of outputP2Drain electrode output electric current it is equal, the electric current of the drain electrode input of 2P the 7th transistors with
6th transistor MN3Drain electrode input electric current it is equal, i.e. the first output end 3111 output electric current and second output terminal 3112 it is defeated
The electric current entered is equal, and the electric current that the electric current and second output terminal 3114 of the output of the first output end 3113 input is equal, is
With continued reference to Fig. 5, optionally, digital control circuit 311 further includes that binary system turns thermometer circuit 307, binary system
Turn thermometer circuit 307 for the binary code in the first adjustment signal to be converted to thermometer-code, improves digital control electricity
Road 311 controls precision.
Optionally, first time delay circuit 310 is identical with the circuit structure of the second time delay circuit 500, second
In time delay circuit 500, selecting control signal control delay time is 0.
With continued reference to Fig. 5, on the basis of the various embodiments described above, optionally, phase shift circuitry 316 includes 2P series connection
The phase inverter (illustratively including 2 phase inverters in Fig. 5) of connection.The input terminal of 1st phase inverter is as phase shift circuitry
316 input terminal, output end of the output end of the 2P phase inverter as phase shift circuitry 316.The control of 2P phase inverter
Hold the 2P phase controlling end respectively as phase shift circuitry 316.Wherein, phase inverter is during by input signal reverse phase
Having time delay, time delay determine that electric current is bigger by the size of current for importing its control terminal, and time delay is smaller.Phase becomes
The time delay formula for changing circuit 316 can state as follows:
Wherein, CLFor the load capacitance of phase inverter, VDDFor the supply voltage on the first power signal line 70.
Due to including in embodiments of the present invention first time delay circuit 310 and the second time delay circuit 500, pass through
Time delay difference using the second time delay circuit 500 and the first time delay circuit 310 in delay trigger circuit 300 is made
For the pulse width of output signal, specifically, when carrying out duty cycle trimmer, the phase delay time of selected phase pulse signal
It can be stated by following formula:
In formula (2), Section 2 is time delay circuit constant error, that is, the second time delay circuit is arranged and eliminates
Error present in first time delay circuit further improves the modulation accuracy of pulse width modulation circuit.
The embodiment of the invention also provides a kind of digital pulsewidth modulation devices.The digital pulsewidth modulation device packet
It includes such as pulse width modulation circuit provided by any embodiment of the invention.The digital pulsewidth modulation device for example can be
Lighting control system or DC-DC converter.The display device includes pulse width modulation provided by any embodiment of the invention
The technical effect of circuit, technical principle and generation is similar, and which is not described herein again.
Note that the above is only a better embodiment of the present invention and the applied technical principle.It will be appreciated by those skilled in the art that
The invention is not limited to the specific embodiments described herein, be able to carry out for a person skilled in the art it is various it is apparent variation,
It readjusts and substitutes without departing from protection scope of the present invention.Therefore, although being carried out by above embodiments to the present invention
It is described in further detail, but the present invention is not limited to the above embodiments only, without departing from the inventive concept, also
It may include more other equivalent embodiments, and the scope of the invention is determined by the scope of the appended claims.
Claims (10)
1. a kind of pulse width modulation circuit characterized by comprising
Sequential control circuit, the sequential control circuit include the first clock signal input terminal and multiple alternative phase outputs,
First clock signal input terminal is electrically connected with clock cable, and the sequential control circuit is used for according to the clock signal
The alternative pulse signal that input clock signal on line successively postpones in the multiple alternative phase output output phase；
Digital selection circuit, the digital selection circuit include selection signal control terminal, multiple alternative phase inputs and one
Selected phase output end, the selection signal control terminal are electrically connected with selection signal line, the multiple alternative phase inputs point
It is not used for corresponding the multiple alternative phase output electrical connection, the digital selection circuit according on selection signal line
Selection control signal exports a selected phase pulse signal in the selected phase output end；
Postpone trigger circuit, the delay trigger circuit includes selected phase input terminal, adjustment signal input terminal and reset signal
Output end, the selected phase input terminal are electrically connected with the selected phase output end, the adjustment signal input terminal and first
The electrical connection of adjustment signal line, the delay trigger circuit is used for will according to the first adjustment signal on the first adjustment signal line
One time regulatable of selected phase pulse delay signal, and from the reset signal output end output reset signal；
Impulse output circuit, the impulse output circuit include second clock signal input part, reset signal input terminal and pulse
Signal output end, the second clock signal input part are electrically connected with comparison of signal phase line, the reset signal input terminal with
The reset signal output end electrical connection, the pulse signal output end are electrically connected with pulse output signals line, and the pulse is defeated
What the comparison of signal phase and the reset signal input terminal that circuit is used to be inputted according to the comparison of signal phase line out inputted
Reset signal controls the duty ratio of the pulse signal of the pulse signal output end output.
2. pulse width modulation circuit according to claim 1, which is characterized in that the sequential control circuit includes 2N-1
A first d type flip flop, N are integer and N >=2；
Described 2N-1The clock pulse terminal of a first d type flip flop is electrically connected with the clock cable, and described 2N-1A first D touching
Send out the alternative phase output as the sequential control circuit of the first output end and second output terminal of device, the 1st described the
The trigger signal input terminal of one d type flip flop and the 2ndN-1The second output terminal of a first d type flip flop is electrically connected, and i-th described first
The trigger signal input terminal of d type flip flop is electrically connected with the first output end of (i-1)-th first d type flip flop, 2≤i≤2N-1。
3. pulse width modulation circuit according to claim 1, which is characterized in that the delay trigger circuit includes:
First time delay circuit, choosing of the first input end of the first time delay circuit as the delay trigger circuit
Select phase inputs, adjustment signal input terminal of second input terminal as the delay trigger circuit；
The output end electricity of rising edge trigger circuit, the input terminal of the rising edge trigger circuit and the first time delay circuit
Connection, reset signal output end of the output end as the delay trigger circuit.
4. pulse width modulation circuit according to claim 3, which is characterized in that the first time delay circuit packet
It includes:
Digital control circuit, including input terminal and 2P output end, the input terminal of the digital control circuit is as described first
The second input terminal of time delay circuit, the first adjustment signal that the digital control circuit is used to be inputted according to its input terminal are adjusted
The size of current of the 2P output end output；
The input terminal of phase shift circuitry, including input, output end and 2P phase controlling end, the phase shift circuitry is made
For the first input end of the first time delay circuit, output end of the output end as the first time delay circuit, 2P
A phase controlling end is electrically connected with the output end of the corresponding digital control circuit respectively, and the phase shift circuitry is used
The phase of the reset signal of its output end output is controlled in the size of current inputted according to the phase controlling end；Wherein, P is certainly
So number.
5. pulse width modulation circuit according to claim 4, which is characterized in that 2P of the digital control circuit are defeated
Outlet respectively includes the first output end and second output terminal, and 2P phase controlling end of the phase shift circuitry respectively includes
One phase controlling end and second phase control terminal, the first phase control terminal and the first of the corresponding digital control circuit
Output end electrical connection, the second phase control terminal are electrically connected with the second output terminal of the corresponding digital control circuit；
The digital control circuit includes: first resistor, the first electric current microscope group, second resistance, the second electric current microscope group, third electric current
Microscope group and the 4th electric current microscope group；
The first end of the first resistor is electrically connected with ground line；
The control terminal of the first electric current microscope group is electrically connected with the input terminal of the digital control circuit, current input terminal and first
Power signal line electrical connection, the first current output terminal is electrically connected with the second end of the first resistor, the second current output terminal and
First current input terminal of second current mirror is electrically connected, and the first electric current microscope group is used for according to first adjustment signal
Adjust the size of current of its current output terminal output；
The first end of the second resistance is electrically connected with first power signal line；
First current input terminal of the second electric current microscope group is electrically connected with the second end of the second resistance, current output terminal with
The ground line electrical connection；
The third electric current microscope group includes current input terminal, the first current output terminal, the second current output terminal and 2P third electricity
Output end is flowed, the current input terminal of the third electric current microscope group is electrically connected with first power signal line, the output of the first electric current
End is electrically connected with the second current input terminal of the second electric current microscope group, and 2P third current output terminal is controlled with the number respectively
The corresponding electrical connection of 2P the first output ends of circuit processed；
The 4th electric current microscope group includes the first current input terminal, current output terminal and 2P the second current input terminals, and described the
First current input terminal of four electric current microscope groups is electrically connected with the second current output terminal of the third electric current microscope group, 2P second electricity
Flow input terminal electrical connection corresponding with 2P second output terminal of the digital control circuit respectively, current output terminal and the ground connection
Line electrical connection.
6. pulse width modulation circuit according to claim 4, which is characterized in that the phase shift circuitry includes 2P
The phase inverter of series connection；
Input terminal of the input terminal of 1st phase inverter as the phase shift circuitry, the 2P phase inverter it is defeated
Output end of the outlet as the phase shift circuitry；
2P phase controlling end of the control terminal of the 2P phase inverters respectively as the phase shift circuitry.
7. pulse width modulation circuit according to claim 3, which is characterized in that the rising edge trigger circuit includes:
First phase inverter, input terminal of the input terminal of first phase inverter as the rising edge trigger circuit；
Amplifier, the input terminal of the amplifier are electrically connected with the output end of first phase inverter；
NAND gate, the first input end of the NAND gate are electrically connected with the output end of the amplifier, the second input terminal with it is described
The input terminal of first phase inverter is electrically connected, output end of the output end as the rising edge trigger circuit.
8. pulse width modulation circuit according to claim 1, which is characterized in that further include the second time delay circuit；
The first input end of second time delay circuit is electrically connected with the comparison of signal phase line, output end and the arteries and veins
Rush the second clock signal input part electrical connection of output circuit.
9. pulse width modulation circuit according to claim 1, which is characterized in that the impulse output circuit includes second
D type flip flop；
The trigger signal input terminal of second d type flip flop is electrically connected with second source signal wire, described in clock pulse terminal conduct
The second clock signal input part of impulse output circuit, reset signal input terminal of the reset terminal as the impulse output circuit,
Pulse signal output end of first output end as the impulse output circuit.
10. a kind of digital pulsewidth modulation device characterized by comprising such as the described in any item pulses of claim 1-9
Width modulation circuit.
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| CN201811041822.9A CN109302166B (en) | 2018-09-07 | 2018-09-07 | Pulse width modulation circuit and device |
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| CN201811041822.9A CN109302166B (en) | 2018-09-07 | 2018-09-07 | Pulse width modulation circuit and device |
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| WO2022198894A1 (en) * | 2021-03-26 | 2022-09-29 | 长鑫存储技术有限公司 | Signal generation circuit and memory |
| US11715503B2 (en) | 2021-03-26 | 2023-08-01 | Changxin Memory Technologies, Inc. | Signal generation circuit and memory |
| WO2023221252A1 (en) * | 2022-05-17 | 2023-11-23 | 华中科技大学 | Pulse voltage generation apparatus having adjustable pulse width |
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| WO2022198894A1 (en) * | 2021-03-26 | 2022-09-29 | 长鑫存储技术有限公司 | Signal generation circuit and memory |
| US11715503B2 (en) | 2021-03-26 | 2023-08-01 | Changxin Memory Technologies, Inc. | Signal generation circuit and memory |
| WO2023221252A1 (en) * | 2022-05-17 | 2023-11-23 | 华中科技大学 | Pulse voltage generation apparatus having adjustable pulse width |
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| CN109302166B (en) | 2022-08-23 |
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