WO2023221252A1

WO2023221252A1 - Pulse voltage generation apparatus having adjustable pulse width

Info

Publication number: WO2023221252A1
Application number: PCT/CN2022/102736
Authority: WO
Inventors: 何强; 程晓敏; 张峻铭; 罗茂源; 葛翔; 缪向水
Original assignee: 华中科技大学; 湖北江城实验室
Priority date: 2022-05-17
Filing date: 2022-06-30
Publication date: 2023-11-23
Also published as: CN114629468B; CN114629468A

Abstract

Disclosed in the present invention is a pulse voltage generation apparatus having an adjustable pulse width. The apparatus comprises: a switch control circuit, which is used for generating a control signal; a clock generation circuit, which is used for generating a 50 MHz clock signal; and an adjustable-pulse-width generation integrated circuit, which comprises a phase-locked loop (PLL), a first trigger, a second trigger, a row trigger array, a selector and an XOR gate, wherein the PLL is used for processing the 50 MHz clock signal and then outputting a 400 MHz high-speed clock signal and a 50 MHz clock signal; the first trigger is used for performing rising edge synchronization processing on the control signal to output a synchronization signal; the second trigger is used for performing 20 ns delay processing on the synchronization signal; and each trigger in the row trigger array is used for outputting, under the control of the 400 MHz high-speed clock signal, a plurality of adjustable-pulse-width pulse signals having a stepping precision of 2.5 ns, and then selecting, by means of the selector, a pulse voltage signal of a required pulse width and sending same to a phase change memory. By means of the present invention, a highly precise pulse voltage signal having a rising edge and a falling edge within a range from 20 ns to 100 ns can be generated, the pulse width is adjustable, and the flexibility is high.

Description

A pulse voltage generating device with adjustable pulse width

【Technical field】

The present invention belongs to the technical field of pulse voltage generators, and more specifically, relates to a pulse voltage generating device with adjustable pulse width.

【Background technique】

Phase-change memory has become the most promising next-generation mainstream non-volatile storage technology due to its advantages of fast read and write speed, high storage density, and compatibility with traditional CMOS processes. Different from traditional semiconductor memory, phase change memory is a resistive memory. What is special about it is that it can be stored stably in a crystalline or amorphous state for a long time at an appropriate temperature, and it can quickly change from a crystalline state to a crystalline state under specific conditions. The working mechanism of one phase state changing to another is to utilize the difference in resistance between the low resistance of the phase change material in the crystalline state and the high resistance in the amorphous state to achieve data storage.

The process of realizing phase change is generally to apply an electrical pulse signal to the memory cell. For example, applying an electrical pulse with a narrow pulse width, high amplitude, and fast falling edge to perform a RESET operation, which melts the ordered crystalline phase change material and rapidly Cooling transforms into a disordered amorphous state, achieving a phase change from low resistance state "0" to high resistance state "1"; conversely, applying an electrical pulse with a wide pulse width and low amplitude can perform a SET operation on the phase change unit , does the amorphous phase change material crystallize after undergoing the annealing process, and then becomes crystalline to achieve the phase change from "1" to "0"; and the specific process of reading the phase change memory cell is: applying a pair of A low-amplitude electrical pulse that does not affect the state of the phase-change material, or a low-amplitude electrical pulse scan signal, reads the state of the device by measuring its resistance.

The current method of reading, writing and erasing phase change memory cells requires the use of ns-level pulse voltage signals, and the rising and falling edge times of the pulse signals are required to be less than 10ns, the pulse width is adjustable from 20 to 100ns, and the accuracy is relatively high. High, faster speed and better signal stability.

Pulse signal generating devices currently on the market are mainly implemented through digital and analog methods. The digital method is mainly implemented using a delay method and is implemented through the connection of different chips. This digital method is more expensive and may occur for systems with different pulse requirements. The situation cannot be adapted, and the accuracy of general digital pulse generators is not enough. The rising and falling edge times are too long, usually greater than 10ns, and cannot be used to test equipment such as phase change memories that require high-precision signal pulses. The simulation method is mainly implemented by building transistors to generate pulse signals through analog circuits, or by filtering. It is inflexible and inconvenient to modify the pulse parameters. It has major limitations and cannot be flexible for different test systems. Make modifications and other defects.

Therefore, developing a high-precision pulse voltage generating device with adjustable pulse width to realize the read, write and erase operations of phase change memory cells is an urgent problem that those skilled in the art need to solve.

[Content of the invention]

In view of the shortcomings of the existing technology, the purpose of the present invention is to provide a pulse voltage generating device with adjustable pulse width, which can generate a pulse voltage signal with high precision of 20 to 100 ns rising and falling edges, and has adjustable pulse width and high flexibility. .

In order to achieve the above object, the present invention provides a pulse voltage generating device with adjustable pulse width for performing read, write and erase operations on phase change memory, including:

A switch control circuit is used to receive operating instructions input by the user and generate control signals;

Clock generation circuit, used to generate 50MHZ clock signal;

The adjustable pulse width generating integrated circuit includes a PLL phase-locked loop, a first flip-flop, a second flip-flop, a row flip-flop array, a selector and an XOR gate, the first flip-flop, the second flip-flop and Each flip-flop in the row flip-flop array is a flip-flop prepared by a 28nm transistor process;

Wherein, the PLL phase-locked loop is used to multiply and divide the 50MHZ clock signal and then output a 400MHZ high-speed clock signal and a 50MHZ clock signal; the first flip-flop is used to operate under the control of the 50MHZ clock signal. Perform rising edge synchronization processing on the control signal to output a synchronization signal; the second flip-flop is used to perform a 20ns delay processing on the synchronization signal under the control of the 50MHZ clock signal and output a 20ns pulse width pulse signal; Each trigger in the trigger array is used to sequentially perform 2.5ns delay processing on the 20ns pulse width pulse signal under the control of the 400MHZ high-speed clock signal, and output multiple adjustable pulse widths with a step accuracy of 2.5ns. Pulse signal; the selector is used to receive a pulse width selection signal input by the user, and select a pulse signal with a required pulse width from a plurality of adjustable pulse width pulse signals; the XOR gate receives and combines the synchronization signal with The pulse signal of the required pulse width is XOR-processed, and the pulse voltage signal of the required pulse width is output to the phase change memory.

The pulse voltage generating device with adjustable pulse width provided by the present invention integrates the main adjustable pulse width generating integrated circuit on a chip. Compared with the traditional digital method that uses discrete devices to connect the circuits, the speed of the signal can be improved. and accuracy, and compared with the analog method, the use of PLL phase-locked loops, multiple flip-flops triggered by different clocks and XOR gates can modify and adjust the pulse width, making the device more flexible; and the first flip-flop provided by the present invention , the second flip-flop and each flip-flop in the row flip-flop array can use flip-flops prepared by 28nm transistor technology, which can ensure that the rising edge and falling edge time of the output pulse signal is within 10ns, which is sufficient for reading phase change memory. Accuracy requirements for write and erase operations.

In one embodiment, the row flip-flop array includes a plurality of cascaded flip-flops, and the input terminal of the first cascaded flip-flop in the row flip-flop array and the output terminals of all cascaded flip-flops are are connected to the signal input end of the selector.

In one embodiment, a host computer is used to input the pulse width selection signal to the selector.

In one embodiment, the host computer adopts Labview host computer.

In one embodiment, the clock generation circuit uses an active crystal oscillator.

In one embodiment, the XOR gate adopts a high-speed 2-input XOR gate.

In one embodiment, an indicator light circuit is further included. When the switch control circuit receives an operation instruction input by a user, the indicator light in the indicator light circuit turns on.

[Picture description]

Figure 1 is a functional block diagram of a pulse voltage generating device with adjustable pulse width provided by an embodiment of the present invention;

Figure 2 is a waveform diagram of an adjustable pulse width pulse signal with a step accuracy of 2.5ns from 20 to 100ns output by a row flip-flop array according to an embodiment of the present invention;

Figure 3 is a waveform diagram of a 20 ns pulse width pulse voltage signal output by a pulse width adjustable pulse voltage generating device provided by an embodiment of the present invention;

Figure 4 is a waveform diagram of a 40ns pulse width pulse voltage signal output by a pulse width adjustable pulse voltage generating device provided by an embodiment of the present invention;

FIG. 5 is a waveform diagram of an 80 ns pulse width pulse voltage signal output by a pulse width adjustable pulse voltage generating device according to an embodiment of the present invention.

【Detailed ways】

In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

It should be noted that the technical indicators for read, write and erase operations of phase change memory are: under the voltage amplitude condition of 0 to 5V, the pulse width of the pulse required for read operation of phase change memory is about 20ns. The pulse width required for memory writing operations is between 20 and 50 ns, and the pulse width required for phase change memory erasing operations is between 60 and 100 ns.

Figure 1 is a schematic block diagram of a pulse voltage generation device with adjustable pulse width provided by the present invention. As shown in Figure 1, the pulse voltage generation device includes a switch control circuit 10, a clock generation circuit 20 and an adjustable pulse width generation integrated circuit 30 , the adjustable pulse width generating integrated circuit 30 includes a PLL phase-locked loop, a first flip-flop, a second flip-flop, a row flip-flop array, a selector and an XOR gate.

Wherein, the clock output terminal of the clock generation circuit 20 is connected to the input terminal of the PLL phase-locked loop, and the first output terminal of the PLL phase-locked loop is connected to the clock input terminal of the first flip-flop and the clock input terminal of the second flip-flop respectively. The second output terminal of the PLL phase-locked loop is connected to the clock input terminal of each flip-flop cascaded in the row flip-flop array; the output terminal of the switch control circuit 10 is connected to the signal input terminal of the first flip-flop. The output terminal is connected to the signal input terminal of the second flip-flop and an input terminal of the XOR gate respectively; the output terminal of the second flip-flop is connected to the signal input terminal of the first flip-flop in the row flip-flop array, and the row flip-flop The signal input terminal of each flip-flop in the array except the first flip-flop is connected to the output terminal of the previous stage flip-flop; the output terminals of all cascaded flip-flops in the row flip-flop array are connected to the signal input terminal of the selector. Connected, the signal selection end of the selector is used to receive the pulse width selection signal input by the user, the output end of the selector is connected to the other input end of the XOR gate, and the output end of the XOR gate is connected to the phase change memory through a high-speed interface.

In this embodiment, the switch control circuit 10 is used to receive the operation instructions input by the user and generate a control signal, that is, a step signal from 0 to 1 or from 1 to 0. The control signal can be realized through the control switch. Press the control switch Realize the generation of control signals. Specifically, the switch control circuit 10 includes a control switch, one end of the control switch is connected to a power supply end, and the other end of the control switch is connected to ground. The power supply end can use a 3.3V or 5V power supply voltage. Specifically, the pulse voltage signal can be adjusted according to the phase change memory. The amplitude requires that the power supply voltage value be set accordingly.

The clock generation circuit 20 can use an active crystal oscillator commonly used in this field to generate a clock signal with a frequency of 50MHZ. This frequency can make the triggering interval of the first flip-flop and the second flip-flop at the backend 20ns, and the 20ns time interval can be used as an adjustable The pulse width generates the initial output of the integrated circuit, which can adjust the output pulse width pulse voltage starting from 20ns.

In the adjustable pulse width generation integrated circuit 30, the PLL phase-locked loop is used to multiply and divide the 50MHZ clock signal generated by the clock generation circuit 20 and then output it. Then the PLL phase-locked loop can output two different clocks. signals, one is a 400MHZ high-speed clock signal, and the other is a 50MHZ clock signal with the same frequency as the active crystal oscillator. The PLL phase-locked loop can output multiple clock signals and can effectively ensure that the phases of the multiple output clock signals are the same without delay. This ensures that the output clock is more accurate, that is, multiple output clocks are highly synchronously output.

After the control signal is input from the switch control circuit 10, it first passes through the first flip-flop, which is used to synchronize the control signal that is not input on the rising edge of the clock with the 50MKZ clock, and convert the asynchronous control signal into a synchronous signal. After passing through the second flip-flop, since the trigger clock of this flip-flop is also 50MHZ, the synchronization signal can be delayed by 20ns through this flip-flop. After the 20ns delay, it passes through the row flip-flop array, and the row triggers The trigger array trigger clock is generated by the PLL phase-locked loop, and the frequency is 400MHZ, so the clock triggered by each flip-flop in the row flip-flop array is 2.5ns, that is, the synchronization signal can be delayed by 2.5ns each time it passes through a flip-flop. The continuous cascading of triggers in the row trigger array can achieve delays of 2.5ns, 5ns, 10ns, 12.5ns, etc. That is, the row trigger array can output a step accuracy of 2.5ns from 22.5 to 100ns. adjustable pulse width pulse signal.

The selector is used to receive the pulse width selection signal input by the user. Specifically, the host computer can be used to input the pulse width selection signal to the selector. The selector selects the required pulse width pulse signal from 22.5 to 100ns based on the pulse width selection signal. Pulse signal with pulse width. It should be noted that the selector provided in this embodiment can identify the pulse width selection signal sent by the host computer. If the host computer sends an all-0 signal, the selector will not select the pulse for output. Does not work. At the same time, when the pulse width selection signal received by the selector exceeds the number of current pulses, the selector also does not select pulses for output. The selector does not work. Only within the normal input range, the selector performs identification. Finally, select the required pulse width for output. Specifically, the host computer provided in this embodiment can use Labview host computer, which can realize waveform display of the output pulse width pulse signal and improve operability.

The XOR gate receives and performs XOR processing on the synchronization signal output by the first flip-flop and the pulse signal of the required pulse width, and then outputs the pulse voltage signal of the required pulse width to the phase change memory, thereby realizing corresponding processing of the phase change memory. operate. Specifically, the XOR gate can use a high-speed 2-input XOR gate, which can reduce the delay caused by the output passing through the XOR gate, further ensuring that the rising edge and falling edge of the output pulse width pulse signal are around 3ns, effectively improving accuracy. .

Since the pulse width required for a phase change memory read operation is about 20ns, in order to accurately control the starting pulse width of the phase change memory output, the signal input end of the selector is in addition to the output of each flip-flop cascaded in the row flip-flop array. In addition to being connected to the terminal, it also needs to be connected to the input terminal of the first cascaded flip-flop in the row flip-flop array, so that the selector can select the 20ns pulse width pulse signal, so that the step can be output through the row flip-flop array. The pulse signal with adjustable pulse width from 20 to 100ns can be processed with an accuracy of 2.5ns, as shown in Figure 2. Specifically, to output a pulse signal with a pulse width of 20ns, the first flip-flop in the row flip-flop array selected by the selector inputs a pulse signal with a pulse width of 20ns, as shown in Figure 3; to output a pulse signal with a pulse width of 40ns, Then the selector selects the delayed signal output by the 8th flip-flop in the row flip-flop array, that is, n=(40-20)/2.5, as shown in Figure 4; to output a pulse signal with a pulse width of 80ns, select The trigger selects the delayed signal output by the 24th flip-flop in the row flip-flop array, that is, n=(80-20)/2.5, as shown in Figure 5. In the same way, we can know the selection method of each pulse width pulse signal, which will not be described again in this embodiment.

Moreover, the first flip-flop, the second flip-flop and each flip-flop in the row flip-flop array provided in this embodiment are all flip-flops prepared by a 28nm transistor process. The small channel length makes the transistor charge and discharge faster. When the process is very small, the delay required for triggering is almost negligible, and because the delay is very small, after the trigger is triggered, the time for signal conversion and flipping is very small, thus ensuring the rising edge of the pulse signal. The falling edge time is within 10ns, which meets the accuracy requirements of phase change memory for read, write and erase operations.

The pulse voltage generating device with adjustable pulse width provided in this embodiment has the main adjustable pulse width generating integrated circuit built on a chip. Compared with the traditional digital method that uses discrete devices to connect the circuits, it can improve the signal. Speed and accuracy, and compared with the analog method, the use of PLL phase-locked loops, multiple flip-flops triggered by different clocks and XOR gates can modify and adjust the pulse width, making the device more flexible; and this embodiment provides the first The flip-flop, the second flip-flop and each flip-flop in the row flip-flop array can all use flip-flops manufactured by the 28nm transistor process, which can ensure that the rising edge and falling edge time of the output pulse signal is within 10ns, which meets the requirements of phase change memory. Accuracy requirements for read, write and erase operations.

In one embodiment, in order to output a pulse signal with a higher pulse width, multiple configurable flip-flops can be reserved in the row flip-flop array, and the number of row flip-flops used in the row flip-flop array can be increased or reduced according to actual pulse width requirements. The number of flip-flops can be changed to change the range of output pulse width. For example, by increasing the number of flip-flops in the row flip-flop array, pulses with a pulse width of more than 100ns can be output. Furthermore, the row flip-flop array can also be operated cyclically to extend the pulse width of the output pulse signal to 20 ns to 200 ns.

In one embodiment, the pulse voltage generating device with adjustable pulse width provided by the present invention may also include an indicator light circuit. When the switch control circuit 10 receives an operation instruction input by the user, that is, when the control switch is pressed by the user, The indicator light in the indicator circuit lights up to indicate the output of pulse width, which serves as an indication.

It is easy for those skilled in the art to understand that the above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions and improvements, etc., made within the spirit and principles of the present invention, All should be included in the protection scope of the present invention.

Claims

A pulse voltage generating device with adjustable pulse width, used for reading, writing and erasing operations on phase change memory, which is characterized by including:

A switch control circuit is used to receive operating instructions input by the user and generate control signals;

Clock generation circuit, used to generate 50MHZ clock signal;

The adjustable pulse width generating integrated circuit includes a PLL phase-locked loop, a first flip-flop, a second flip-flop, a row flip-flop array, a selector and an XOR gate, the first flip-flop, the second flip-flop and Each flip-flop in the row flip-flop array is a flip-flop prepared by a 28nm transistor process;

Wherein, the PLL phase-locked loop is used to multiply and divide the 50MHZ clock signal and then output a 400MHZ high-speed clock signal and a 50MHZ clock signal; the first flip-flop is used to operate under the control of the 50MHZ clock signal. Perform rising edge synchronization processing on the control signal to output a synchronization signal; the second flip-flop is used to perform a 20ns delay processing on the synchronization signal under the control of the 50MHZ clock signal and output a 20ns pulse width pulse signal; Each trigger in the trigger array is used to sequentially perform 2.5ns delay processing on the 20ns pulse width pulse signal under the control of the 400MHZ high-speed clock signal, and output multiple adjustable pulse widths with a step accuracy of 2.5ns. Pulse signal; the selector is used to receive a pulse width selection signal input by the user, and select a pulse signal with a required pulse width from a plurality of adjustable pulse width pulse signals; the XOR gate receives and combines the synchronization signal with The pulse signal of the required pulse width is XOR-processed, and the pulse voltage signal of the required pulse width is output to the phase change memory.
The pulse voltage generating device with adjustable pulse width according to claim 1, wherein the row flip-flop array includes a plurality of cascaded flip-flops, and the first trigger of the cascade in the row flip-flop array The input terminal of the selector and the output terminals of all flip-flops in the cascade are connected to the signal input terminal of the selector.
The pulse voltage generating device with adjustable pulse width according to claim 1, characterized in that a host computer is used to input the pulse width selection signal to the selector.
The pulse voltage generating device with adjustable pulse width according to claim 3, characterized in that the host computer adopts Labview host computer.
The pulse voltage generating device with adjustable pulse width according to claim 1, characterized in that the clock generating circuit adopts an active crystal oscillator.
The pulse voltage generating device with adjustable pulse width according to claim 1, characterized in that the XOR gate adopts a high-speed 2-input XOR gate.
The pulse voltage generating device with adjustable pulse width according to claim 1, further comprising an indicator light circuit. When the switch control circuit receives an operation instruction input by a user, the indication in the indicator light circuit Light.