WO2008095508A1

WO2008095508A1 - Pulse generator

Info

Publication number: WO2008095508A1
Application number: PCT/EP2007/000946
Authority: WO
Inventors: Rui Tao; Djordje Simic; Can Bingoel
Original assignee: Tes Electronic Solutions Gmbh
Priority date: 2007-02-05
Filing date: 2007-02-05
Publication date: 2008-08-14

Abstract

A pulse generator (100) for generating pulses (SF) with tuneable pulse width and tuneable pulse repetition rate. The pulse generator (100) can for example be used in impulse radio based Ultra-Wide-Bandwidth (UWB) wireless transceivers for high data rate (HDR) as well as for low data rate (LDR) applications. The low cost and compact pulse generator (100) is able to generate symmetrical pulses with tuneable pulse duration and sufficient swing for UWB applications. The pulse duration variations are achieved by electrically controlling the frequency of the input clock signal SAl which leads to more accurate and technology independent solutions compared to the conventional pulse generators. The wide bandwidth master-slave D-flip- flop structure is used to get the tuneable time delay. An XOR-block or subtracter is utilized to generate the narrow pulse.

Description

Pulse generator

Conventional pulse generators with fixed pulse width typically comprise a delay circuit and an XOR gate. A reference signal is sent to the delay circuit and the delayed reference signal is applied to the XOR gate together with the reference signal. At the output of the XOR gate pulses with fixed duration are generated. The pulse width is determined by the delay time of the delay circuit.

One of the main drawbacks of such conventional pulse generators using such delay circuits is the narrow operating frequency range because the delay time is depending on the operating frequency and the circuit parameters of the delay circuit. In order to get the accurate delay time which determines the pulse duration e.g. transistor sizes and parameters of the delay circuit have to be optimized. Thus, the delay time is technology dependent. The pulse generator can only work at a single frequency to generate the predetermined delay time which determines the basically fixed pulse duration. For the design of Ultra-Wide-Bandwidth (UWB) transceivers using different technologies, the delay circuits or delay cells must therefore be redesigned and re-simulated for each technology, which increases the design time.

Further it is difficult to implement a tuneable pulse width and a tuneable pulse repetition rate of a generated pulse train by modifying a conventional pulse generator comprising such delay circuits.

It is the technical problem underlying the invention to provide for a pulse generator for generating pulses with tuneable pulse width and tuneable pulse repetition rate which allows an accurate pulse generation, which is basically technology independent and which can be implemented at low costs. The invention solves this problem by providing a pulse generator having the features of claim 1.

The pulse generator for generating pulses or a pulse train with tuneable pulse width and tuneable pulse repetition rate comprises a first flip-flop with a clock input terminal, a data input terminal and an output terminal, wherein the first flip-flop is arranged to receive a clock signal with variable frequency at the clock input terminal for tuning the pulse width, and is arranged to receive a data signal with variable frequency at the data input terminal for tuning the pulse repetition rate. The pulse generator further comprises a second flip-flop with a clock input terminal, a data input terminal and an output terminal, wherein the output terminal of the first flip-flop is connected to the data input terminal of the second flip flop and the second flip-flop is arranged to receive the inverted clock signal at the clock input terminal. The pulse generator further comprises a signal processing means or logic circuit with a first input terminal connected to the output terminal of the first flip-flop, a second input terminal connected to the output terminal of the second flip-flop and an output terminal for outputting the pulses or pulse train. The tuneable mono or doublet pulse generator architecture principle according to the invention uses the first and second flip-flops, which are triggered by the clock signal and the inverted clock signal, respectively, for pulse generation. Compared to the conventional narrow band delay cell or delay circuit structure, the first and second flip-flops are used to adjust or tune the pulse width by shifting the frequency of the clock signal and to adjust or tune the pulse repetition rate by shifting or adjusting the frequency and/or the duty cycle of the data signal.

In a further embodiment the signal processing means is an XOR-gate or a subtracter. The XOR-gate is used to generate a pulse train with mono pulses, i.e. pulses with only one polarity. The subtracter subtracts the signal at the output of the first flip-flop and the signal at the output of the second flip-flop to generate a pulse train with doublet pulses, i.e. pulses with a positive and a negative polarity.

In a further embodiment the first flip-flop and/or the second flip-flop are D-flip-flops. The D-flip-flops may be e.g. master-slave D-flip-flops.

In a further embodiment the first flip-flop and/or the second flip-flop are arranged such that data from the data input terminal are transferred to the output terminal on a positive edge of the clock signal applied to the clock input terminal.

In a further embodiment the clock input terminals of the first and the second flip-flops each comprise a noninverted clock input terminal and an inverted clock input terminal and the clock signal is a differential clock signal comprising an inverted part and a noninverted part, wherein the noninverted clock input terminal of the first flip-flop is adapted to receive the noninverted part of the differential clock signal and the inverted clock input terminal of the first flip-flop is adapted to receive the inverted part of the differential clock signal. The noninverted clock input terminal of the second flip-flop is adapted to receive the inverted part of the differential clock signal and the inverted clock input terminal of the second flip- flop is adapted to receive the noninverted part of the differential clock signal. The first and second flip-flops according to this embodiment are so called differential flip-flops. By permutation of the coupling of the differential clock signal to the differential clock input terminals the clock signal can be inverted between the flip-flops without requiring a dedicated inverter for inverting the clock signal.

Advantageous embodiments of the invention, as described in detail below, are shown in the drawings, in which: Fig. 1 shows a principle block diagram of a pulse generator for generating pulses with tuneable pulse width and tuneable pulse repetition rate according to an embodiment of the invention,

Fig. 2 shows signal waveforms of the pulse generator of Fig. 1 ,

Fig. 3 shows a principle block diagram of a pulse generator for generating pulses with tuneable pulse width and tuneable pulse repetition rate according to a further embodiment of the invention,

Fig. 4 shows signal waveforms of the pulse generator of Fig. 3,

Fig. 5 shows a schematic of a summing amplifier acting as a subtracter of the pulse generator of Fig. 3 and

Fig. 6 shows a block diagram of an embodiment of the pulse generator of Fig. 3.

Fig. 1 shows a principle block diagram of a pulse generator 100 for generating pulses with tuneable pulse width and tuneable pulse repetition rate according to an embodiment of the invention.

The pulse generator 100 comprises a first D-flip-flop 101 with a clock input terminal CLK, a data input terminal D and an output terminal Q. A clock signal SA with variable frequency and a duty cycle of 50% is applied at the clock input terminal CLK for tuning the pulse width of a pulse train signal SF generated by the pulse generator 100. A data signal SC with variable frequency and a duty cycle of 50% is applied at the data input terminal D for tuning the pulse repetition rate of pulses SF generated by the pulse generator 100. The pulse generator 100 further comprises a second D-flip-flop 103 with a clock input terminal CLK, a data input terminal D and an output terminal Q. The output terminal Q of the first D-flip-flop 101 is connected to the data input terminal D of the second D-flip flop 103. An inverter 102 is used to invert the clock signal SA to generate an inverted clock signal SB which is applied at the clock input terminal CLK of the second D-flip- flop 103.

A signal processing means implemented in form of an XOR-gate 104 comprises a first input terminal connected to the output terminal Q of the first D-flip-flop 101 , a second input terminal connected to the output terminal Q of the second D-flip-flop 103 and an output terminal for output- ting the pulses or the pulse train SF.

Fig. 2 shows signal waveforms of the pulse generator of Fig. 1. The clock signal SA and the data signal SC are applied at the clock input terminal CLK and the data input terminal D of the first D-flip-flop 101 , respectively. The frequency of the clock signal SA determines the pulse width of the pulse train SF. The pulse width or pulse duration of the signal SF is equal to half a clock period of the clock signal SA. The data rate or frequency and the duty cycle of the data signal SC determine the pulse repetition rate of the pulse train SF.

Referring to Fig. 2, the data signal SC is retimed and reshaped after the first D-flip-flop 101 which is triggered by rising edges of the clock signal SA. In other words, the first D-flip-flop 101 is arranged such that data from the data input terminal D are transferred to the output terminal Q on a positive edge of the clock signal SA applied to the clock input terminal CLK. After the D-flip-flop 101 the relationship between a transferred data signal SD and the clock signal SA is fixed. Then the retimed signal SD is delayed half a clock period of the clock signal SA by the successive or second D-flip-flop 103 which is triggered by the rising edge of the inverted clock signal SB, i.e. the falling edge of the clock signal SA. There- fore the output pulse signal or pulse train SF is generated by combining the retimed signal SD and the delayed signal SE, output by the second D-flip-flop 103, with a simple combinatory logic circuitry in form of the XOR-gate 104. The pulse duration of the signal SF is equal to half a clock period of the clock signal SA.

Fig. 3 shows a principle block diagram of a pulse generator 200 for generating pulses with tuneable pulse width and tuneable pulse repetition rate according to a further embodiment of the invention. The pulse generator 100 of Fig. 1 generates so called mono pulses, i.e. pulses with only one polarity, whereas the pulse generator 200 of Fig. 3 generates so called doublet pulses, i.e. pulses with a positive and a negative polarity. A doublet can be viewed as a monocycle (i.e. the derivative of a pulse) where the positive and negative-going halves have been separated in time. This separation is the basis for one of the key benefits of using doublets as a basis waveform. Doublets are much more tolerant of jitter in a transmitter clocking and the clocking of correlators in a coherent receiver.

In order to get the doublet pulses with separate mono pulses, the XOR- gate 104 of Fig. 1 is replaced with the subtracter 105. The remaining elements are identical those of Fig. 1.

Fig. 4 shows signal waveforms of the pulse generator of Fig. 3. The pulse train SF in Fig. 4 is generated as doublet pulses. The remaining signals are identical those of Fig. 2.

Fig. 5 shows a schematic of a summing amplifier acting as the subtracter 105 of the pulse generator 200 of Fig. 3. The signal SD of Fig. 3 is formed as a differential signal and comprises an inverted part SD_I and a noninverted part SD_NI, i.e. the signal pair SD_I and SD_NI forms the differential signal SD. Accordingly the signal SE of Fig. 3 comprises an inverted part SE_I and a noninverted part SE_NI, i.e. the signal pair SE_I and SE_NI forms the differential signal SE. The input signals of the summing amplifier 105 are added in the current domain.

The summing amplifier or subtracter 105 comprises resistors R1 and R2 and transistors T1 to T6 which are coupled between a positive voltage supply Vdd and a negative voltage supply Vss in the topology shown in Fig. 5.

Fig. 6 shows a block diagram of an embodiment of the pulse generator 200 of Fig. 3. The pulse generator 200' of Fig. 6 operates as a differential pulse generator, i.e. uses differential signals as input and output signals. Each differential signal comprises an inverted part and a nonin- verted part.

The clock input terminals of the first and the second D-flip-flops 101 and 103 each comprise a noninverted clock input terminal CLK_NI and an inverted clock input terminal CLK_I. The noninverted clock input terminal CLK_NI of the first D-flip-flop 101 receives a noninverted part SA_NI of the differential clock signal SA and the inverted clock input terminal CLK_I of the first D-flip-flop 101 receives the inverted part SA_I of the differential clock signal SA. The noninverted clock input terminal CLK_NI of the second D-flip-flop 103 receives the inverted part SA_I of the differential clock signal SA and the inverted clock input terminal CLK_I of the second D-flip-flop 103 receives the noninverted part SA_NI of the differential clock signal SA. Because the inverted part SA_I and the non- inverted part SA_NI of the differential clock signal SA are swapped between the D-flip-flops 101 and 103, the dedicated inverter 102 of figures 1 and 3 can be omitted.

The pulse generators 100, 200 and 200' can for example be used in impulse-based Ultra-Wide-Bandwidth (UWB) wireless transceivers. The low cost, compact pulse generators 100, 200 and 200' are able to generate symmetrical pulses with tuneable pulse duration and sufficient swing for UWB applications. The pulse duration variations are achieved by electrically controlling the frequency of the input clock signal SA₁ which leads to more accurate and technology independent solutions compared to the conventional pulse generators. The wide bandwidth master-slave D-flip-flop structure is used to get the tuneable time delay. An XOR-block is utilized to generate the narrow pulse.

This pulse generator according the invention can be designed and realized using commercially available discrete components and can operate at a pulse repetition frequency or pulse repetition rate up to 500 MHz with an ultra short pulse. Good symmetry and low distortion have been achieved for these pulses. The pulse generators are suitable for the IEEE 802.15.4a standard.

Claims

1. Pulse generator (100, 200, 200') for generating pulses (SF) with tuneable pulse width and tuneable pulse repetition rate, comprising: a first flip-flop (101 ) with a clock input terminal (CLK), a data input terminal (D) and an output terminal (Q), wherein the first flip-flop (101 ) is arranged to receive a clock signal (SA) with variable frequency at the clock input terminal (CLK) for tuning the pulse width, and is arranged to receive a data signal (SC) with variable frequency at the data input terminal (D) for tuning the pulse repetition rate, a second flip-flop (103) with a clock input terminal (CLK), a data input terminal (D) and an output terminal (Q), wherein the output terminal (Q) of the first flip-flop (101 ) is connected to the data input terminal (D) of the second flip flop (103) and the second flip-flop (103) is arranged to receive an inverted clock signal (SB) at the clock input terminal (CLK), and a signal processing means (104, 105) with a first input terminal connected to the output terminal (Q) of the first flip-flop (101 ), a second input terminal connected to the output terminal (Q) of the second flip-flop (103) and an output terminal for outputting the pulses (SF).

2. Pulse generator of claim 1 , characterized in that the signal processing means is an XOR-gate (104) or a subtracter (105).

3. Pulse generator of claim 1 or 2, characterized in that the first flip- flop (101 ) and/or the second flip-flop (103) are D-flip-flops.

4. Pulse generator of anyone of claims 1 to 3, characterized in that the first flip-flop (101 ) and/or the second flip-flop (103) are ar- ranged such that data from the data input terminal (D) are transferred to the output terminal (Q) on a positive edge of the clock signal (SA, SB) applied to the clock input terminal (CLK).

5. Pulse generator of anyone of claims 1 to 4, characterized in that the clock input terminals (CLK) of the first and the second flip-flops (101 , 103) each comprise a noninverted clock input terminal (CLK_NI) and an inverted clock input terminal (CLKJ) and the clock signal (SA) is a differential clock signal comprising an inverted part (SAJ) and a noninverted part (SAJsII), wherein the noninverted clock input terminal (CLKJMI) of the first flip-flop (101 ) is adapted to receive the noninverted part (SAJMI) of the differential clock signal (SA) and the inverted clock input terminal (CLKJ) of the first flip-flop (101 ) is adapted to receive the inverted part (SAJ) of the differential clock signal (SA), and the noninverted clock input terminal (CLKJsII) of the second flip-flop (103) is adapted to receive the inverted part (SAJ) of the differential clock signal (SA) and the inverted clock input terminal (CLKJ) of the second flip-flop (103) is adapted to receive the noninverted part (SAJsJI) of the differential clock signal (SA).