CN114629468B - Pulse width adjustable pulse voltage generating device - Google Patents
Pulse width adjustable pulse voltage generating device Download PDFInfo
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- CN114629468B CN114629468B CN202210532086.7A CN202210532086A CN114629468B CN 114629468 B CN114629468 B CN 114629468B CN 202210532086 A CN202210532086 A CN 202210532086A CN 114629468 B CN114629468 B CN 114629468B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/017—Adjustment of width or dutycycle of pulses
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
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- Pulse Circuits (AREA)
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Abstract
The invention discloses a pulse voltage generating device with adjustable pulse width, comprising: a switch control circuit for generating a control signal; a clock generation circuit for generating a 50MHZ clock signal; the adjustable pulse width generation integrated circuit comprises a PLL phase-locked loop, a first trigger, a second trigger, a row trigger array, a selector and an exclusive-OR gate, wherein the PLL phase-locked loop is used for processing a 50MHZ clock signal and then outputting a 400MHZ high-speed clock signal and a 50MHZ clock signal; the first trigger is used for carrying out rising edge synchronous processing on the control signal and outputting a synchronous signal; the second trigger is used for carrying out 20ns delay processing on the synchronous signal; each trigger in the row trigger array is used for outputting a plurality of pulse signals with adjustable pulse width and the step precision of 2.5ns under the control of a 400MHZ high-speed clock signal, and then a pulse voltage signal with the required pulse width is selected to the phase change memory through the selector. The pulse voltage generator can generate 20-100 ns pulse voltage signals with high precision of rising edges and falling edges, and is adjustable in pulse width and high in flexibility.
Description
Technical Field
The invention belongs to the technical field of pulse voltage generators, and particularly relates to a pulse voltage generator with adjustable pulse width.
Background
Phase change memory has become the most potential next generation mainstream nonvolatile memory technology because of its advantages of fast read/write speed, high storage density, compatibility with the traditional CMOS process, etc. Unlike traditional semiconductor memory, phase change memory belongs to resistive memory, and features that it can store data stably in crystalline or amorphous state for long period at proper temperature and change from one phase state to another rapidly under certain conditions.
The process of implementing phase change generally is to apply an electric pulse signal to the memory cell, for example, apply an electric pulse with narrow pulse width, high amplitude and fast falling edge to perform a RESET operation, so that the ordered crystalline phase change material is melted and rapidly cooled to be converted into an unordered amorphous state, and the phase change from the low resistance state "0" to the high resistance state "1" is implemented; on the contrary, an electric pulse with wide pulse width and low amplitude is applied to carry out SET operation on the phase change unit, and the amorphous phase change material is crystallized after the annealing process and becomes crystalline state, so that the phase change from 1 to 0 is realized; the specific process of performing the read operation on the phase change memory cell is as follows: an electric pulse with low amplitude which does not affect the state of the phase-change material is applied, or an electric pulse scanning signal with low amplitude is applied, and the state of the phase-change material is read by measuring the resistance value of the device.
At present, an ns-level pulse voltage signal is needed to be used for carrying out read-write-erase operation on a phase change memory unit, the rising edge time and the falling edge time of the pulse signal are required to be less than 10ns, the pulse width is adjustable within 20-100 ns, the precision is high, the speed is high, and the signal stability is good.
The pulse signal generating device on the market is mainly realized in a digital mode and an analog mode, the digital mode is mainly realized in a time delay mode and is realized by connecting different chips, the digital method is high in price, the system with different pulse requirements can not be adapted, the precision of a general digital pulse generator is insufficient, the time of a rising edge and a falling edge is too long, usually more than 10ns, and the general digital pulse generator cannot be used for testing equipment such as a phase change memory and the like which need high-precision signal pulses. The analog mode is realized mainly by building a transistor through an analog circuit to generate a pulse signal or by filtering, so that the defects of inflexibility, inconvenience in modifying pulse parameters, great limitation, incapability of flexibly modifying different test systems and the like exist.
Therefore, it is an urgent need to solve the problem of the art to develop a pulse voltage generator with high precision and adjustable pulse width for implementing read/write operation of a phase change memory cell.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a pulse voltage generating device with adjustable pulse width, which can generate a pulse voltage signal with high precision of 20-100 ns rising edge and falling edge, and has adjustable pulse width and high flexibility.
In order to achieve the above object, the present invention provides a pulse voltage generating device with adjustable pulse width, which is used for performing read-write operation on a phase change memory, and comprises:
the switch control circuit is used for receiving an operation instruction input by a user to generate a control signal;
a clock generation circuit for generating a 50MHZ clock signal;
the adjustable pulse width generation integrated circuit comprises a PLL phase-locked loop, a first trigger, a second trigger, a row trigger array, a selector and an exclusive-OR gate, wherein each trigger in the first trigger, the second trigger and the row trigger array is a trigger prepared by adopting a 28nm transistor process;
the PLL is used for outputting a 400MHZ high-speed clock signal and a 50MHZ clock signal after frequency multiplication and frequency division processing are carried out on the 50MHZ clock signal; the first trigger is used for carrying out rising edge synchronous processing on the control signal under the control of the 50MHZ clock signal and outputting a synchronous signal; the second trigger is used for carrying out 20ns time delay processing on the synchronous signal under the control of the 50MHZ clock signal and outputting a 20ns pulse width pulse signal; each trigger in the row trigger array is used for sequentially carrying out 2.5ns time delay processing on the 20ns pulse width pulse signals under the control of the 400MHZ high-speed clock signal and outputting a plurality of adjustable pulse width pulse signals with the stepping precision of 2.5 ns; the selector is used for receiving a pulse width selection signal input by a user and selecting a pulse signal with a required pulse width from a plurality of adjustable pulse width pulse signals; and the exclusive-OR gate receives and carries out exclusive-OR processing on the synchronous signal and the pulse signal with the required pulse width, and outputs a pulse voltage signal with the required pulse width to the phase change memory.
The pulse voltage generating device with adjustable pulse width provided by the invention has the advantages that the main body pulse width generating integrated circuit is manufactured on one chip, compared with the traditional digital mode that a discrete device is adopted to connect circuits, the speed and the precision of signals can be improved, and compared with an analog mode, a PLL (phase locked loop), a plurality of triggers triggered by different clocks and an exclusive-OR gate are adopted, the pulse width can be modified and adjusted, so that the device is more flexible; in addition, the first trigger, the second trigger and each trigger in the row trigger array can be prepared by a 28nm transistor process, so that the time of the rising edge and the falling edge of an output pulse signal can be ensured to be within 10ns, and the precision requirement of the phase change memory for reading, writing and erasing operations can be met.
In one embodiment, the row flip-flop array comprises a plurality of cascaded flip-flops, and the input end of the first cascaded flip-flop in the row flip-flop array and the output ends of all the cascaded flip-flops are connected with the signal input end of the selector.
In one embodiment, an upper computer is used to input the pulse width selection signal to the selector.
In one embodiment, the upper computer is a Labview upper computer.
In one embodiment, the clock generation circuit employs an active crystal oscillator.
In one embodiment, the exclusive-or gate adopts a high-speed 2-way input exclusive-or gate.
In one embodiment, the electronic device further comprises an indicator light circuit, and when the switch control circuit receives an operation instruction input by a user, an indicator light in the indicator light circuit is turned on.
Drawings
Fig. 1 is a schematic block diagram of a pulse voltage generator with adjustable pulse width according to an embodiment of the present invention;
FIG. 2 is a waveform diagram of an adjustable pulse width pulse signal with a step precision of 2.5ns from 20ns to 100ns output by a row flip-flop array according to an embodiment of the present invention;
FIG. 3 is a waveform diagram of a pulse voltage signal with a pulse width of 20ns outputted from a pulse voltage generator with adjustable pulse width according to an embodiment of the present invention;
FIG. 4 is a waveform diagram of a 40ns pulse width pulse voltage signal outputted by the pulse voltage generator with adjustable pulse width according to an embodiment of the present invention;
fig. 5 is a waveform diagram of an 80ns pulse width pulse voltage signal output by a pulse voltage generator with adjustable pulse width according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
It should be noted that the technical indexes of the phase change memory for performing the read-write operation are as follows: under the condition that the voltage amplitude is 0-5V, the pulse width of a pulse required by the phase change memory for reading operation is about 20ns, the pulse width of a pulse required by the phase change memory for writing operation is 20-50 ns, and the pulse width of a pulse required by the phase change memory for erasing operation is 60-100 ns.
Fig. 1 is a schematic block diagram of a pulse voltage generating apparatus with adjustable pulse width according to the present invention, as shown in fig. 1, the pulse voltage generating apparatus includes a switch control circuit 10, a clock generating circuit 20, and an adjustable pulse width generating integrated circuit 30, where the adjustable pulse width generating integrated circuit 30 includes a PLL phase-locked loop, a first flip-flop, a second flip-flop, a row flip-flop array, a selector, and an xor gate.
The clock output end of the clock generating circuit 20 is connected with the input end of a PLL (phase locked loop), the first output end of the PLL is respectively connected with the clock input end of a first trigger and the clock input end of a second trigger, and the second output end of the PLL is connected with the clock input end of each trigger cascaded in the row trigger array; the output end of the switch control circuit 10 is connected with the signal input end of the first trigger, and the output end of the first trigger is respectively connected with the signal input end of the second trigger and one input end of the exclusive-or gate; the output end of the second trigger is connected with the signal input end of the first trigger in the row trigger array, and the signal input ends of all the triggers except the first trigger in the row trigger array are connected with the output end of the previous stage trigger; the output ends of all cascaded triggers in the row trigger array are connected with the signal input end of a selector, the signal selection end of the selector is used for receiving a pulse width selection signal input by a user, the output end of the selector is connected with the other input end of the exclusive-OR gate, and the output end of the exclusive-OR gate is connected with the phase change memory through a high-speed interface.
In the present embodiment, the switch control circuit 10 is configured to receive an operation instruction input by a user to generate a control signal, i.e. a step signal from 0 to 1 or from 1 to 0, where the control signal is generated by pressing a control switch. Specifically, the switch control circuit 10 includes a control switch, one end of the control switch is connected to a power supply terminal, the other end of the control switch is grounded, the power supply terminal can use a 3.3V or 5V power supply voltage, and specifically, the power supply voltage value can be set correspondingly according to the requirement of the phase change memory on the amplitude of the pulse voltage signal.
The clock generating circuit 20 may use an active crystal oscillator commonly used in the art to generate a clock signal with a frequency of 50MHZ, where the frequency may enable the triggering interval of the first flip-flop and the second flip-flop at the back end to be 20ns, and the time interval of 20ns is used as the initial output of the adjustable pulse width generating integrated circuit, that is, the pulse width pulse voltage outputted may be adjusted from 20 ns.
In the adjustable pulse width generating integrated circuit 30, the PLL phase-locked loop is configured to perform frequency multiplication and frequency division processing on a 50MHZ clock signal generated by the clock generating circuit 20 and then output the frequency-multiplied and frequency-divided clock signal, so that the PLL phase-locked loop can output two different clock signals, one is a 400MHZ high-speed clock signal, and the other is a 50MHZ clock signal having the same frequency as the active crystal oscillator, and the PLL phase-locked loop can output a plurality of clock signals and can effectively ensure that the phases of the output clock signals are the same without time delay, thereby ensuring that the output clock is more accurate, i.e., outputting a plurality of output clocks with high synchronization.
After the control signal is input from the switch control circuit 10, the control signal first passes through a first flip-flop, which is used to synchronize the control signal that is not input at the rising edge of the clock with the clock 50MKZ, and convert the asynchronous control signal into a synchronous signal. After passing through the second flip-flop, because the trigger clock of the flip-flop is also 50MHZ, 20ns delay can be performed on the synchronous signal through the flip-flop, after 20ns delay, the synchronous signal passes through the row flip-flop array, the trigger clock of the row flip-flop array is generated by a PLL phase-locked loop, and the frequency is 400MHZ, so that the clock triggered by each flip-flop in the row flip-flop array is 2.5ns, that is, 2.5ns delay can be performed on the synchronous signal through each flip-flop, and 2.5ns, 5ns, 10ns, 12.5ns delay and the like can be realized by continuously cascading the flip-flops in the row flip-flop array, that is, an adjustable pulse width pulse signal with the step precision of 2.5ns from 22.5 to 100ns can be output through the row flip-flop array.
The selector is used for receiving a pulse width selection signal input by a user, specifically, the pulse width selection signal can be input to the selector by an upper computer, and the selector selects a pulse signal with a required pulse width from pulse signals with adjustable pulse widths of 22.5-100 ns according to the pulse width selection signal. It should be noted that the selector provided in this embodiment can identify the pulse width selection signal sent by the upper computer, and if the upper computer sends all 0 signals, the selector does not select pulses to output, and does not operate, and meanwhile, when the pulse width selection signal received by the selector exceeds the number of the current pulses, the selector also does not select pulses to output, and does not operate, and only within the normal input range, after the selector identifies, the selector selects the required pulse width to output. Specifically, the upper computer provided by this embodiment may adopt a Labview upper computer, and may implement waveform display of an output pulse width pulse signal, thereby improving operability.
And the XOR gate receives and outputs the synchronous signal output by the first trigger and the pulse signal with the required pulse width to the phase change memory after XOR processing, and then outputs the pulse voltage signal with the required pulse width to the phase change memory, thereby realizing the corresponding operation of the phase change memory. Specifically, the exclusive-or gate can adopt a high-speed 2-way input exclusive-or gate, so that the time delay caused by the output of the exclusive-or gate can be reduced, the rising edge and the falling edge of the output pulse width pulse signal are further ensured to be about 3ns, and the precision is effectively improved.
Because the pulse width required by the phase change memory for reading operation is about 20ns, in order to accurately control the initial pulse width output by the phase change memory, the signal input end of the selector is connected with the output end of each trigger cascaded in the row trigger array and also connected with the input end of the first trigger cascaded in the row trigger array, so that the selector can select the pulse signal with the pulse width of 20ns, and the adjustable pulse signal with the step precision of 2.5ns from 20ns to 100ns can be output through the row trigger array, as shown in fig. 2. Specifically, in order to output a pulse signal with a pulse width of 20ns, the selector selects a pulse signal with a pulse width of 20ns input by the first flip-flop in the row flip-flop array, as shown in fig. 3; in order to output a pulse signal with a pulse width of 40ns, the selector selects the delayed signal output by the 8 th flip-flop in the row flip-flop array, i.e. n = (40-20)/2.5, as shown in fig. 4; to output a pulse signal with a pulse width of 80ns, the selector selects the delayed signal output by the 24 th flip-flop in the row flip-flop array, i.e., n = (80-20)/2.5, as shown in fig. 5. Similarly, the selection manner of each pulse width pulse signal can be known, and the details of this embodiment are not repeated.
In addition, each of the first flip-flop, the second flip-flop and the row flip-flop array provided in this embodiment is a flip-flop prepared by a 28nm transistor process, the length of a channel is small, the charging and discharging speed of a transistor is high, delay required by triggering of the flip-flop is almost negligible when the process is small, and due to the small delay, after the flip-flop is triggered, the time for converting and turning signals is very small, so that the time for a rising edge and a falling edge of a pulse signal is guaranteed to be within 10ns, and the precision requirement for performing read-write-erase operation on the phase change memory is met.
The pulse voltage generating device with adjustable pulse width provided by the embodiment has the advantages that the main body pulse width generating integrated circuit is manufactured on one chip, compared with the traditional digital mode that a discrete device is adopted to connect circuits, the speed and the precision of signals can be improved, and compared with an analog mode, a PLL (phase locked loop), a plurality of triggers triggered by different clocks and an exclusive-or gate are adopted, the pulse width can be modified and adjusted, so that the device is more flexible; in addition, each of the first flip-flop, the second flip-flop and the flip-flop in the row flip-flop array provided by this embodiment may be a flip-flop prepared by a 28nm transistor process, so that the time of a rising edge and a falling edge of an output pulse signal can be guaranteed to be within 10ns, and the precision requirement of the phase change memory for performing read-write erasing operation can be met.
In one embodiment, in order to output a pulse signal with a higher pulse width, a plurality of configurable flip-flops can be reserved in the row flip-flop array, and the number of flip-flops used in the row flip-flop array can be increased or decreased according to the actual pulse width requirement, so as to change the range of the pulse width which can be output, for example, the number of flip-flops in the row flip-flop array is increased, and a pulse with a pulse width of more than 100ns can be output. Furthermore, the row trigger array can also expand the pulse width of the output pulse signal to 20 ns-200 ns through the cycle operation.
In one embodiment, the pulse voltage generating apparatus with adjustable pulse width provided by the present invention may further include an indicator light circuit, and when the switch control circuit 10 receives an operation instruction input by a user, that is, when the control switch is pressed by the user, an indicator light in the indicator light circuit lights up to output indicating that the pulse width is performed, so as to perform an indicating function.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (6)
1. A pulse voltage generating device with adjustable pulse width is used for carrying out read-write erasing operation on a phase change memory, and is characterized by comprising:
the switch control circuit is used for receiving an operation instruction input by a user to generate a control signal;
a clock generating circuit for generating a 50MHZ clock signal;
the adjustable pulse width generation integrated circuit comprises a PLL phase-locked loop, a first trigger, a second trigger, a row trigger array, a selector and an exclusive-OR gate, wherein each of the first trigger, the second trigger and the row trigger array adopts a trigger prepared by a 28nm transistor process, the row trigger array comprises a plurality of cascaded triggers, and the input end of the first cascaded trigger in the row trigger array and the output ends of all cascaded triggers are connected with the signal input end of the selector;
the PLL is used for outputting a 400MHZ high-speed clock signal and a 50MHZ clock signal after frequency multiplication and frequency division processing are carried out on the 50MHZ clock signal; the first trigger is used for carrying out rising edge synchronous processing on the control signal under the control of the 50MHZ clock signal and outputting a synchronous signal; the second trigger is used for carrying out 20ns time delay processing on the synchronous signal under the control of the 50MHZ clock signal and outputting a 20ns pulse width pulse signal; each trigger in the row trigger array is used for sequentially carrying out 2.5ns time delay processing on the 20ns pulse width pulse signals under the control of the 400MHZ high-speed clock signal and outputting a plurality of adjustable pulse width pulse signals with the stepping precision of 2.5 ns; the selector is used for receiving a pulse width selection signal input by a user and selecting a pulse signal with a required pulse width from a plurality of adjustable pulse width pulse signals; and the exclusive-OR gate receives and carries out exclusive-OR processing on the synchronous signal and the pulse signal with the required pulse width, and outputs a pulse voltage signal with the required pulse width to the phase change memory.
2. The pulse voltage generator according to claim 1, wherein the pulse width selection signal is input to the selector by using an upper computer.
3. The pulse voltage generator with adjustable pulse width according to claim 2, wherein the upper computer is a Labview upper computer.
4. The pulse width adjustable pulse voltage generator according to claim 1, wherein the clock generation circuit employs an active crystal oscillator.
5. The pulse voltage generator according to claim 1, wherein the xor gate is a high-speed 2-way input xor gate.
6. The apparatus according to claim 1, further comprising an indicator light circuit, wherein when the switch control circuit receives an operation command from a user, an indicator light in the indicator light circuit is turned on.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210532086.7A CN114629468B (en) | 2022-05-17 | 2022-05-17 | Pulse width adjustable pulse voltage generating device |
| PCT/CN2022/102736 WO2023221252A1 (en) | 2022-05-17 | 2022-06-30 | Pulse voltage generation apparatus having adjustable pulse width |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210532086.7A CN114629468B (en) | 2022-05-17 | 2022-05-17 | Pulse width adjustable pulse voltage generating device |
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| CN114629468A CN114629468A (en) | 2022-06-14 |
| CN114629468B true CN114629468B (en) | 2022-08-05 |
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| WO (1) | WO2023221252A1 (en) |
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| CN114629468B (en) * | 2022-05-17 | 2022-08-05 | 华中科技大学 | Pulse width adjustable pulse voltage generating device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP3457557B2 (en) * | 1998-12-28 | 2003-10-20 | Ｎｅｃマイクロシステム株式会社 | Pulse generating apparatus and method |
| US6390579B1 (en) * | 1999-04-15 | 2002-05-21 | Hewlett-Packard Company | Pulse width modulator using delay-line technology with automatic calibration of delays to desired operating frequency |
| US6670837B2 (en) * | 2001-09-26 | 2003-12-30 | Tempo Research Corporation | Time domain reflectometer with digitally generated variable width pulse output |
| US7250800B2 (en) * | 2005-07-12 | 2007-07-31 | Hewlett-Packard Development Company, L.P. | Clock pulse width control circuit |
| JP2007235908A (en) * | 2006-02-02 | 2007-09-13 | Sharp Corp | Ring oscillating circuit, delayed time measuring circuit, test circuit, clock signal generating circuit, image sensor, pulse generating circuit, semiconductor integrated circuit and its testing method |
| JP4106383B2 (en) * | 2006-06-08 | 2008-06-25 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Delay ratio adjustment circuit, delay pulse generation circuit, and pulse width modulation pulse signal generator. |
| WO2008095508A1 (en) * | 2007-02-05 | 2008-08-14 | Tes Electronic Solutions Gmbh | Pulse generator |
| CN109302166B (en) * | 2018-09-07 | 2022-08-23 | 南方科技大学 | Pulse width modulation circuit and device |
| CN110661513B (en) * | 2019-08-15 | 2022-09-13 | 合肥工业大学 | Digital pulse width modulation circuit and working method |
| CN110429927A (en) * | 2019-08-22 | 2019-11-08 | 电子科技大学 | A kind of pulse position is any and the pulse generating unit of adjustable pulse width |
| KR20210034219A (en) * | 2019-09-20 | 2021-03-30 | 에스케이하이닉스 주식회사 | Signal generation circuit and semiconductor apparatus using the signal generation circuit |
| CN111654267B (en) * | 2020-05-28 | 2024-02-13 | 广东浪潮大数据研究有限公司 | Adjustable pulse generator |
| CN114629468B (en) * | 2022-05-17 | 2022-08-05 | 华中科技大学 | Pulse width adjustable pulse voltage generating device |
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| CN114629468A (en) | 2022-06-14 |
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