CN108123687A - Pierce circuit with spread spectrum function - Google Patents
Pierce circuit with spread spectrum function Download PDFInfo
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- CN108123687A CN108123687A CN201611087424.1A CN201611087424A CN108123687A CN 108123687 A CN108123687 A CN 108123687A CN 201611087424 A CN201611087424 A CN 201611087424A CN 108123687 A CN108123687 A CN 108123687A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/26—Modifications of amplifiers to reduce influence of noise generated by amplifying elements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/181—Low frequency amplifiers, e.g. audio preamplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
Abstract
The present invention provides a kind of pierce circuit with spread spectrum function, including oscillator module and modulation circuit.Oscillator module includes the first current source, the second current source, first switch, second switch, capacitance and logic circuit.Modulation circuit includes periodic modulation module and Stochastic Modulation module, periodic modulation module exports periodically variable first modulated charge current, and/or the first modulation discharge current changed from node ISN decimation periods, to modulate the periodic distribution of the spread spectrum of pierce circuit point, the second modulated charge current that Stochastic Modulation module output changes at random is to node ISP, and/or the second modulation discharge current changed at random is extracted from node ISN, to modulate trembling frequently for each spread spectrum point of the pierce circuit.Compared with prior art, the modulation system that the present invention is combined using periodic modulation and Stochastic Modulation, so as to reduce carrier frequency because static noise caused by Stochastic Modulation.
Description
【Technical field】
The present invention relates to circuit design field, more particularly to a kind of pierce circuit of the low static noise with spread spectrum function.
【Background technology】
D class power amplifiers have the advantages that high efficiency, low-power consumption, are widely used in the electrical equipments such as TV, mobile phone.But
That unique switching characteristic can generate high di/dt and dv/dt signals, and with wider jamming bandwidth, these voltages and
Current impulse can introduce larger alternating current in physics and parasitic circuit element respectively, generate conduction and radiated noise.
Existing oscillator circuit structure of the technology generally use with spread spectrum function, the circuit structure can cycle " random " changes one by one
The frequency of sawtooth waveforms so that the sawtooth wave frequency rate that oscillator generates changes near centre frequency, and fixed frequency is concentrated on by original
Energy spread at rate is to more side frequency points, so as to achieve the effect that reduce EMI (electromagnetic interference).But " random "
The carrier frequency of modulation would generally bring the static noise in audiorange, and D class power amplifiers quiescent noise is caused to be promoted.
Therefore, it is necessary to a kind of improved technical solution is provided to solve the problems, such as above-mentioned static noise.
【The content of the invention】
It is an object of the invention to provide a kind of pierce circuit with spread spectrum function, carrier frequency can be reduced because
Static noise caused by Stochastic Modulation.
To solve the above-mentioned problems, the present invention provides a kind of pierce circuit with spread spectrum function, including oscillator mould
Block and modulation circuit.The oscillator module include the first current source, the second current source, first switch, second switch, capacitance and
Logic circuit, wherein, first current source is connected between power end and node ISP, the electricity of the first current source output
Charging current on the basis of stream, the benchmark charging current flow to node ISP from power end；First switch be connected to node ISP and
Between node O, second switch is connected between node O and node ISN；Second current source is connected to node ISN and ground saves
Between point, and discharge current on the basis of the electric current of second current source output, the reference discharge electric current are flowed to from node ISN
Ground node；Capacitance connection is between node O and ground node.The logic circuit by the voltage of node O and the first reference voltage and
Second reference voltage is compared, and when the voltage of node O is less than or equal to the second reference voltage, the first logic level of output is opened
It closes control signal and locks, first switch to be controlled to turn on, second switch cut-off is equal to or more than first in the voltage of node O
The switch controlling signal of the second logic level and locking are exported during reference voltage, second switch to be controlled to turn on, first switch is cut
Only, the voltage of the node O forms sawtooth oscillation signal.The modulation circuit includes periodic modulation module and Stochastic Modulation mould
Block, the periodic modulation module export periodically variable first modulated charge current and are taken out to node ISP and/or from node ISN
Periodically variable first modulation discharge current is taken, it is described to modulate the periodic distribution of the spread spectrum of pierce circuit point
The second modulated charge current that the output of Stochastic Modulation module changes at random extracts random become to node ISP and/or from node ISN
Second modulation discharge current of change, to modulate trembling frequently for each spread spectrum point of the pierce circuit.
Further, the periodic modulation module includes cyclic counter and multiple first modulation units, based on described
Sawtooth oscillation signal or the switch controlling signal form the clock signal of the cyclic counter, the cycle rate counter
Periodically variable the first binary number of multidigit is exported, the first modulation that each first modulation unit can generate predefined weight is filled
Electric tributary and the first modulation electric discharge tributary of predefined weight.The control terminal of each first modulation unit and the multidigit the one or two into
Corresponding one-bit digital signal is connected in number processed, the one-bit digital signal that each first modulation unit is terminated to based on its control,
Control whether it exports node ISP described in the first modulation charging Zhi Liuzhi；It is controlled whether to extract first from the node ISN to adjust
System electric discharge tributary, the first modulation charging tributary of each first modulation unit output accumulate corresponding with the first binary number the
One modulated charge current；The first modulation electric discharge tributary that each first modulation unit extracts accumulates corresponding with the first binary number
The first modulation discharge current, due to the first binary number cyclically-varying, the first modulated charge current and the first modulation electric discharge
Electric current also can cyclically-varying therewith.
Further, each first modulation unit generates predefined weight with benchmark charging current described in estimated rate mirror image
The first modulation charging tributary, the first modulation electric discharge of predefined weight is generated with reference discharge electric current described in estimated rate mirror image
Tributary.
Further, first modulation unit includes metal-oxide-semiconductor M14, metal-oxide-semiconductor M15, switchs K1, switchs K2.Wherein, MOS
The source electrode of pipe M14 is connected with power end, and drain electrode is connected through switching K1 with node ISP, and grid is connected with node VISP, switch
The control terminal of K1 is connected with the control terminal of the first modulation unit；The drain electrode of metal-oxide-semiconductor M15 is connected through switching K2 with node ISN, grid
Pole is connected with node VISN, and source electrode is connected with ground node, switchs the control terminal of K2 and the control terminal of first modulation unit
It is connected.
Further, the Stochastic Modulation module includes random counter and multiple second modulation units, the random meter
Number devices export the second binary number of multidigit changed at random each clock cycle, based on the sawtooth oscillation signal or described open
The clock signal that control signal forms the random counter is closed, each second modulation unit can generate the second of predefined weight
Modulate the second modulation electric discharge tributary of charging tributary and predefined weight, the control terminal of each second modulation unit and the multidigit the
Corresponding one-bit digital signal is connected in two binary numbers, the one-bit digital that each second modulation unit is terminated to based on its control
Signal, controls whether it exports the second modulation charging tributary to the node ISP；Control its whether from node ISN extract second
Modulation electric discharge tributary, the second modulation charging tributary of each second modulation unit output accumulate the of corresponding second binary number
Two modulated charge currents, the second modulation electric discharge tributary that each second modulation unit extracts accumulate corresponding second binary number
Second modulation discharge current, since the second binary number changes at random, the second modulated charge current and the second modulation discharge current
Also can change at random therewith.
Further, each second modulation unit generates predefined weight with benchmark charging current described in estimated rate mirror image
The second modulation charging tributary, the second modulation electric discharge of predefined weight is generated with reference discharge electric current described in estimated rate mirror image
Tributary.
Further, second modulation unit includes metal-oxide-semiconductor M16, metal-oxide-semiconductor M17, switchs K3, switchs K4, wherein, MOS
The source electrode of pipe M16 is connected with power end, and drain electrode is connected through switching K3 with node ISP, and grid is connected with node VISP, switch
The control terminal of K3 is connected with the control terminal of the second modulation unit；The drain electrode of metal-oxide-semiconductor M17 is connected through switching K4 with node ISN, grid
Pole is connected with node VISN, and source electrode is connected with ground node, switchs the control terminal of K4 and the control terminal of second modulation unit
It is connected.
Further, the first modulated charge current and the transformable minimum value of the first modulation discharge current are more than second and adjust
The transformable minimum value of charging current processed and the second modulation discharge current, alternatively, the first modulated charge current and the first modulation
The transformable minimum value of discharge current is more than the second modulated charge current and the transformable maximum of the second modulation discharge current
Value.
Further, first current source and the second current source include reference current source, metal-oxide-semiconductor M4, metal-oxide-semiconductor M7, MOS
Pipe M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11.Wherein, the source electrode of metal-oxide-semiconductor M4, metal-oxide-semiconductor M7 and metal-oxide-semiconductor M9 are connected with power end, MOS
The grid of pipe M4 is connected with the drain electrode of metal-oxide-semiconductor M4；Reference current source is connected between the drain electrode of metal-oxide-semiconductor M4 and ground node, and base
The electric current of quasi- current source output is known as reference current, and the reference current flows to ground node from the drain electrode of the metal-oxide-semiconductor M4；MOS
Pipe M4, metal-oxide-semiconductor M7, the grid of metal-oxide-semiconductor M9 are connected with node VISP, and the drain electrode of metal-oxide-semiconductor M7 is connected with the drain electrode of metal-oxide-semiconductor M10；
The grid of metal-oxide-semiconductor M10 and drain electrode are connected with node VISN, and source electrode is connected with ground node；The drain electrode of metal-oxide-semiconductor M9 and node
ISP is connected；The drain electrode of metal-oxide-semiconductor M11 is connected with node ISN, and source electrode is connected with ground node, and grid is connected with node VISN.
Further, the oscillator module further includes reference voltage generating circuit, the reference voltage generating circuit bag
Include metal-oxide-semiconductor M5, resistance R5 and R6.Wherein, the source electrode of metal-oxide-semiconductor M5 is connected with power end, and grid is connected with node VISP, leakage
Pole is connected with node A；One end of resistance R5 is connected with node A, and the other end is connected with node B；One end of resistance R6 and node B
It is connected, the other end is connected with ground node.The voltage of the node A is first reference voltage, and the voltage of node B is described
Second reference voltage.
Further, the reference current source includes metal-oxide-semiconductor M3, resistance R1, R2, R3 and R4 and operational amplifier
OPA.Wherein, resistance R1, R2 and R3 is sequentially connected in series between power end and ground node；The positive input of the operational amplifier
Connecting node between resistance R2 and R3 is connected, and negative input is connected through resistance R4 with ground node；The metal-oxide-semiconductor M3's
Drain electrode is connected with the drain electrode of metal-oxide-semiconductor M4, and the grid of the metal-oxide-semiconductor M3 is connected with the output terminal of operational amplifier OPA, the MOS
The source electrode of pipe M3 is connected with the negative input of operational amplifier OPA.
Further, the logic circuit include first comparator, the second comparator, the first NAND gate and second with it is non-
Door, the positive input of first comparator are connected with the first reference voltage, and the forward direction of negative input and the second comparator is defeated
Enter end and node O is connected, the negative input of the second comparator is connected with the second reference voltage；The first of first NAND gate is defeated
Enter end with the output terminal of first comparator to be connected, the second input terminal is connected with the output terminal of the second NAND gate；First NAND gate
Output terminal be connected with the output terminal of logic circuit；The first input end of second NAND gate and the output terminal phase of the first NAND gate
Even, the second input terminal is connected with the output terminal of the second comparator, wherein, the voltage value of the first reference voltage is more than the second benchmark
The voltage value of voltage.
Compared with prior art, the pierce circuit with spread spectrum function in the present invention uses periodic modulation and random
The modulation system being combined is modulated, so as to reduce carrier frequency because static noise caused by Stochastic Modulation.
【Description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Attached drawing be briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present invention, for this
For the those of ordinary skill of field, without having to pay creative labor, it can also be obtained according to these attached drawings other
Attached drawing.Wherein：
Fig. 1 is the circuit diagram of pierce circuit in one embodiment in the present invention；
Fig. 2 is the circuit diagram of pierce circuit shown in FIG. 1 in a specific embodiment；
Fig. 3 is the circuit diagram of first modulation unit in one embodiment in Fig. 2；With
Fig. 4 is the circuit diagram of second modulation unit in one embodiment in Fig. 2.
【Specific embodiment】
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is described in further detail.
" one embodiment " or " embodiment " referred to herein refers to may be included at least one realization method of the present invention
A particular feature, structure, or characteristic." in one embodiment " that different places occur in the present specification not refers both to same
A embodiment, nor the individual or selective embodiment mutually exclusive with other embodiment.Unless stated otherwise, herein
In connect, be connected, connecting expression be electrically connected word represent directly or indirectly to be electrical connected.
Shown in please referring to Fig.1, for the circuit diagram of the pierce circuit in the present invention in one embodiment.Fig. 1
Shown pierce circuit includes oscillator module 100 and modulation circuit 200.
The oscillator module 100 includes the first current source 110, the second current source 120, first switch M12, second switch
M13, capacitance C1 and logic circuit 130.Wherein, the first current source I1 is connected between power end VDDA and node ISP, institute
The electric current for stating the first current source I1 outputs is known as benchmark charging current I1, the benchmark charging current I1 from power end VDDA flow directions
Node ISP；First switch M12 is connected between node ISP and node O, second switch M13 be connected to node O and node ISN it
Between；Second current source 120 is connected between node ISN and ground node GNDA, and the electricity of second current source 120 output
Stream is known as reference discharge electric current I2, the reference discharge electric current I2 and flows to ground node GNDA from node ISN；Capacitance C1 is connected to section
Between point O and ground node GNDA.
The first input end of the logic circuit 130 is connected with the first reference voltage V REFH, the second input terminal and second
Reference voltage V REFL is connected, and the 3rd input terminal is connected with node O, and output terminal is connected with switching the control terminal of M12 and M13.
Voltage and the comparison knot of first reference voltage V REFH and second reference voltage V REFL of the logic circuit 130 based on node O
Fruit exports a switch controlling signal VOSC0 by its output terminal, and switch controlling signal VOSC0 is used to control first switch M12
With second switch M13 alternate conductions.
In the embodiment shown in fig. 1, the logic circuit 130 includes first comparator COMP1, the second comparator
COMP2, the first NAND gate NAND1 and the second NAND gate NAND2, wherein, the positive input of first comparator COMP1 and first
Reference voltage V REFH is connected, and negative input is connected with the positive input of the second comparator COMP2 and the node O,
The negative input of second comparator COMP2 is connected with the second reference voltage V REFL；The first input of first NAND gate NAND1
End is connected with the output terminal of first comparator COMP1, and the second input terminal is connected with the output terminal of the second NAND gate NAND2；The
The output terminal of one NAND gate NAND1 is connected with the output terminal VOSC0 of logic circuit 130；The first input of second NAND gate NAND2
End is connected with the output terminal of the first NAND gate NAND1, and the second input terminal is connected with the output terminal of the second comparator COMP2,
In, the voltage value of the first reference voltage V REFH is more than the voltage value of the second reference voltage V REFL.
In Fig. 1, the voltage (i.e. the voltage of node O) of capacitance C1 is raised and lowered under the influence of charging and discharging currents, with shape
Into sawtooth oscillation signal VSAW.Sawtooth oscillation signal VSAW becomes switch control letter after being handled by logic circuit 130
Number VOSC0, the switch controlling signal VOSC0 control switch M12 and M13 alternate conductions or shut-off, so as to change filling for capacitance C1
Discharge condition.Specifically, when the voltage of node O is less than the second reference voltage V REFL, the output terminal output of logic circuit 130
The switch controlling signal VOSC0 of first logic level (such as low level) is simultaneously locked, and first switch M12 conductings at this time, second open
M13 shut-offs are closed, so that capacitance C1 enters charged state, the benchmark charging current I1 is by the first switch M12 to institute
Capacitance C1 chargings are stated, the voltage of the node O can gradually rise；When the voltage of node O is more than the first reference voltage V REFH,
The output terminal of the logic circuit 130 exports the switch controlling signal VOSC0 of the second logic level (such as high level) and locks,
At this point, first switch M12 shut-offs, the 2nd M13 conductings, so that capacitance C1 enters discharge condition, the reference discharge electric current I2
It is discharged by the second switch M13 to the capacitance C1, the voltage of the node O can continuously decrease.
In the embodiment shown in fig. 1, the first switch is metal-oxide-semiconductor M12, and the second switch is metal-oxide-semiconductor M13,
In, the source electrode of the metal-oxide-semiconductor M12 is connected with node ISP, and drain electrode is connected with node O, grid and the logic circuit 130
Output terminal be connected；The drain electrode of the metal-oxide-semiconductor M13 is connected with node O, and source electrode is connected with node ISN, and grid is patrolled with described
The output terminal for collecting circuit 130 is connected.
Please continue to refer to shown in Fig. 1, the modulation circuit 200 includes periodic modulation module 210 and Stochastic Modulation module
220。
The periodic modulation module can be generated based on the sawtooth oscillation signal VSAW or switch controlling signal VOSC0
The 210 and clock signal VOSC of Stochastic Modulation module 220.Based on the clock signal VOSC, the periodic modulation module 210 is defeated
Go out periodically variable first modulated charge current IP1 nodes ISP and/or the first tune changed from node ISN decimation periods
Discharge current IN1 processed, with the periodic distribution of the spread spectrum point of modulating oscillator circuit.It is described based on the clock signal VOSC
Stochastic Modulation module 220 exports the second modulated charge current IP2 changed at random and is extracted to node ISP and/or from node ISN
The the second modulation discharge current IN2 changed at random trembles frequency with each spread spectrum point of modulating oscillator circuit.
It should be noted that the switch that the output terminal that the clock signal VOSC can be the logic circuit 130 exports
Control signal VOSC0, or the first input end received signal of the first NAND gate NAND1 of logic circuit 130
VOSC1 can also be the second input terminal received signal VOSC2 of the second NAND gate NAND2 of logic circuit 130.
It is the circuit diagram of pierce circuit shown in FIG. 1 in a specific embodiment shown in please referring to Fig.2.
Pierce circuit shown in Fig. 2 includes oscillator module 300 and modulation circuit 400.
Compared with the logic circuit 130 in Fig. 1, the logic circuit 330 in Fig. 2 further includes phase inverter INV1, INV2, INV3
And INV4.Wherein, the input terminal of phase inverter INV1 is connected with the output terminal of first comparator COMP1, phase inverter INV1 output terminals
It is connected with the input terminal of phase inverter INV2, the output terminal of phase inverter INV2 is connected with the first input end of the first NAND gate NAND1；
The input terminal of phase inverter INV3 is connected with the output terminal of the second comparator COMP2, the output terminal and phase inverter of phase inverter INV3
The input terminal of INV4 is connected, and the output terminal of phase inverter INV4 is connected with the second input terminal of the second NAND gate NAND2.
Compared with the oscillator module 100 in Fig. 1, the first current source and the second electricity in oscillator module 300 in Fig. 2
Stream source includes reference current source 312, metal-oxide-semiconductor M4, M7, M8, M9, M10 and M11.Wherein, the source electrode of metal-oxide-semiconductor M4, M7 and M9 with
Power end VDDA is connected, and the grid of metal-oxide-semiconductor M4 is connected with the drain electrode of metal-oxide-semiconductor M4；Reference current source 312 is connected to metal-oxide-semiconductor M4's
Between drain electrode and ground node GNDA, and the electric current that reference current source 312 exports is known as reference current I0, the reference current I0 certainly
The drain electrode flow direction ground node GNDA of the metal-oxide-semiconductor M4；The grid of metal-oxide-semiconductor M4, M7 and M9 are connected with node VISP, metal-oxide-semiconductor M7
Drain electrode be connected with the source electrode of metal-oxide-semiconductor M8, the grid of metal-oxide-semiconductor M8 is connected with enable signal EN, the drain electrode of metal-oxide-semiconductor M8 and metal-oxide-semiconductor
The drain electrode of M10 is connected；The grid of metal-oxide-semiconductor M10 and drain electrode are connected with node VISN, and source electrode is connected with ground node GNDA；MOS
The drain electrode of pipe M9 is connected with node ISP；The drain electrode of metal-oxide-semiconductor M11 is connected with node ISN, and source electrode is connected with ground node GNDA,
Grid is connected with node VISN.Metal-oxide-semiconductor M4, M5, M7 and M9 form current mirror, and metal-oxide-semiconductor M10 and M11 also form current mirror.Its
In, the electric current of metal-oxide-semiconductor M9 mirror image metal-oxide-semiconductors M4, to obtain the benchmark charging current I1；The electricity of metal-oxide-semiconductor M11 mirror image metal-oxide-semiconductors M10
Stream, to obtain the reference discharge electric current I2.
In the embodiment shown in Figure 2, the reference current source 312 includes metal-oxide-semiconductor M1, M2 and M3, resistance R1, R2, R3
And R4 and operational amplifier OPA.Wherein, the source electrode of metal-oxide-semiconductor M1 is connected with power end VDDA, grid and enable signal EN
It is connected, resistance R1, R2 and R3 are sequentially connected in series between the drain electrode of metal-oxide-semiconductor M1 and ground node GNDA；The grid and resistance of metal-oxide-semiconductor M2
Connecting node between R1 and R2 is connected, and the source electrode of metal-oxide-semiconductor and drain electrode are connected with ground node GNDA；The operational amplifier
Connecting node between the positive input of OPA and resistance R2 and R3 is connected, and negative input is through resistance R4 and ground node
GNDA is connected；The drain electrode of the metal-oxide-semiconductor M3 is connected with the drain electrode of metal-oxide-semiconductor M4, the grid and operational amplifier of the metal-oxide-semiconductor M3
The output terminal of OPA is connected, and the source electrode of the metal-oxide-semiconductor M3 is connected with the negative input of operational amplifier OPA.
Compared with the oscillator module 100 in Fig. 1, device module 300 shown in Fig. 2 of swinging further includes reference voltage generating circuit
340, the reference voltage generating circuit 340 includes metal-oxide-semiconductor M5, M6, resistance R5 and R6.Wherein, the source electrode and power supply of metal-oxide-semiconductor M5
End VDDA is connected, and grid is connected with node VISP, and drain electrode is connected with the source electrode of metal-oxide-semiconductor M6；The grid of metal-oxide-semiconductor M6 is with enabling
Signal EN is connected, and drain electrode is connected with node A；One end of resistance R5 is connected with node A, and the other end is connected with node B；Resistance
One end of R6 is connected with node B, and the other end is connected with ground node GNDA.The voltage of the node A is first benchmark electricity
VREFH is pressed, the voltage of node B is the second reference voltage V REFL.
In the embodiment shown in Figure 2, metal-oxide-semiconductor M1, M4, M5, M6, M7, M8, M9 and M12 is PMOS transistor；Metal-oxide-semiconductor
M2, M3, M10 and M11 are NMOS transistor.
In the embodiment shown in Figure 2, metal-oxide-semiconductor M1, M6 and M8 is enabled switch, by enable signal EN control metal-oxide-semiconductors M1,
M6 and M8 on or off, so as to which oscillator module 300 be controlled to work or do not worked.In other embodiments, M1, M6 and M8 can
To be omitted.
Please continue to refer to shown in Fig. 2, the periodic modulation module 410 includes cyclic counter 412 and multiple first and adjusts
Unit processed.
Based on the clock signal VOSC, the cycle rate counter 412 exports periodically variable the first binary system of multidigit
Number.Each first modulation unit can generate the first modulation charging tributary of predefined weight and the first tributary modulation of predefined weight
Electric discharge tributary.The control terminal CON of each first modulation unit one-bit digital letters corresponding with first binary number of multidigit
Number be connected, the one-bit digital signal that each first modulation unit is connected to based on its control terminal CON controls whether it exports the first tune
Node ISP described in charging Zhi Liuzhi processed；It is controlled whether to extract first from the node ISN and modulates electric discharge tributary.Each first
First modulation charging tributary of modulation unit output accumulates first modulated charge current IP1 corresponding with the first binary number；
The first modulation electric discharge tributary that each first modulation unit extracts accumulates the first modulation electric discharge corresponding with the first binary number
Electric current IN1.Due to the first binary number cyclically-varying, the first modulated charge current and the first modulation discharge current also can be therewith
Cyclically-varying.Each first modulation unit generates the first of predefined weight with benchmark charging current described in estimated rate mirror image
Charging tributary is modulated, the first modulation electric discharge tributary of predefined weight is generated with reference discharge electric current described in estimated rate mirror image.
In the embodiment shown in Figure 2, the cycle rate counter 412 includes several d type flip flops being sequentially connected in series, except last
Outside one d type flip flop, in adjacent two d type flip flops, the output terminal Q of previous d type flip flop and the input of the latter d type flip flop
End D is connected, and the clock end VOSC of the clock end CLK of each d type flip flop with the periodic modulation module 410 is connected；Last
The output terminal Q of a d type flip flop is connected with the input terminal D of first d type flip flop.In this way, it is selected from the cycle rate counter 412
Multidigit output terminal of the output terminal of multiple d type flip flops as the cycle rate counter 412 is periodically variable described more to export
The first binary number of position.
Please continue to refer to shown in Fig. 2, the Stochastic Modulation module 420 includes random counter 422 and multiple second modulation
Unit.
Based on the clock signal VOSC, the random counter 422 exports the second binary number of multidigit changed at random.
Each second modulation unit can generate the second modulation charging tributary of predefined weight and the second tributary modulation of predefined weight is put
Electric tributary.
The control terminal CON of each second modulation unit and corresponding one-bit digital signal in second binary number of multidigit
It is connected.The one-bit digital signal that each second modulation unit is connected to based on its control terminal CON, controls whether it exports the second modulation
The node ISP is given in charging tributary；It is controlled whether to extract second from node ISN and modulates electric discharge tributary.Each second modulation is single
Second modulation charging tributary of member output accumulates the second modulated charge current IP2 of corresponding second binary number；Each second
The second modulation electric discharge tributary that modulation unit extracts accumulates the second modulation discharge current IN2 of corresponding second binary number.By
Change at random in the second binary number, the second modulated charge current and the second modulation discharge current can also change at random therewith.Often
A second modulation unit generates the second modulation charging tributary of predefined weight with benchmark charging current described in estimated rate mirror image,
The second modulation electric discharge tributary of predefined weight is generated with reference discharge electric current described in estimated rate mirror image.
In the embodiment shown in Figure 2, the random counter 422 includes feedback unit 4222 and is sequentially connected in series several
In two adjacent d type flip flops of d type flip flop, the output terminal Q of previous d type flip flop and the input terminal D phases of the latter d type flip flop
Even, clock end VOSCs of the clock end CLK of each d type flip flop with the Stochastic Modulation module 420 is connected, the first d type flip flop
Input terminal D be connected with a feedback unit 500, the feedback unit 500 exports the level signal that changes at random and gives the first D triggerings
The input terminal D of device.In this way, the output terminal of multiple d type flip flops is selected from the random counter 422 as the random counter
The multidigit output terminal of device 422, to export second binary number of multidigit.
In one embodiment, the first modulated charge current and the transformable minimum value of the first modulation discharge current are more than
The transformable minimum value of second modulated charge current and the second modulation discharge current.Preferably, the first modulated charge current and
The transformable minimum value of first modulation discharge current is more than the second modulated charge current and second and modulates the variable of discharge current
The maximum of change.In this way, it can utilize described in the first modulated charge current and the first modulation discharge current modulation of large change
The periodic distribution of the spread spectrum point of pierce circuit utilizes the second modulated charge current of small change and the second modulation electric discharge electricity
Each spread spectrum point of the stream modulation pierce circuit trembles frequency.
It is the circuit diagram of first modulation unit in one embodiment in Fig. 2 shown in please referring to Fig.3.
First modulation unit shown in Fig. 3 includes metal-oxide-semiconductor M14, M15, and the 3rd switch K1, the 4th switchs K2.Wherein, MOS
The source electrode of pipe M14 is connected with power end VDDA, and drain electrode is connected through switching K1 with node ISP, and grid is connected with node VISP,
The control terminal of switch K1 is connected with the control terminal CON of the first modulation unit.The drain electrode of metal-oxide-semiconductor M15 is through switching K2 and node ISN phases
Even, grid is connected with node VISN, and source electrode is connected with ground node, switchs the control terminal of K2 and first modulation unit
Control terminal CON is connected.
It is the circuit diagram of second modulation unit in one embodiment in Fig. 2 shown in please referring to Fig.4.
Second modulation unit shown in Fig. 4 includes metal-oxide-semiconductor M16, M17, and the 5th switch K3, the 6th switchs K4.Wherein, MOS
The source electrode of pipe M16 is connected with power end VDDA, and drain electrode is connected through switching K3 with node ISP, and grid is connected with node VISP,
The control terminal of switch K3 is connected with the control terminal CON of the second modulation unit.The drain electrode of metal-oxide-semiconductor M17 is through switching K4 and node ISN phases
Even, grid is connected with node VISN, and source electrode is connected with ground node, switchs the control terminal of K4 and second modulation unit
Control terminal CON is connected.
In conclusion the pierce circuit in the present invention, the modulation being combined using a kind of periodic modulation and Stochastic Modulation
Mode reduces carrier frequency because static noise caused by Stochastic Modulation.The key point of the present invention is using periodic modulation
The point distribution of setting spread spectrum is modulated at each spread spectrum point using randomness and carries out trembling frequency.By periodic modulation band spectrum modulation pair
The frequency component answered is set in outside the audible audiorange of human ear.
In the present invention, the word that the expressions such as " connection ", connected, " company ", " connecing " are electrical connected, unless otherwise instructed, then
Represent direct or indirect electric connection.
It is pointed out that any change that one skilled in the art does the specific embodiment of the present invention
All without departing from the scope of claims of the present invention.Correspondingly, the scope of claim of the invention is also not merely limited to
In previous embodiment.
Claims (12)
1. a kind of pierce circuit with spread spectrum function, which is characterized in that it includes oscillator module and modulation circuit,
The oscillator module includes the first current source, the second current source, first switch, second switch, capacitance and logic circuit,
Wherein, first current source is connected between power end and node ISP, is filled on the basis of the electric current of the first current source output
Electric current, the benchmark charging current flow to node ISP from power end；First switch is connected between node ISP and node O,
Second switch is connected between node O and node ISN；Second current source is connected between node ISN and ground node, and institute
State the second current source output electric current on the basis of discharge current, the reference discharge electric current from node ISN flow to ground node；Capacitance
It is connected between node O and ground node,
The logic circuit by the voltage of node O compared with the first reference voltage and the second reference voltage, in the electricity of node O
When pressure is less than or equal to the second reference voltage, switch controlling signal and the locking of the first logic level are exported, to control first switch
Conducting, second switch end, and the switch of the second logic level is exported when the voltage of node O is equal to or more than the first reference voltage
Control signal simultaneously locks, and second switch to be controlled to turn on, first switch cut-off, the voltage of the node O forms sawtooth oscillation
Signal,
The modulation circuit includes periodic modulation module and Stochastic Modulation module, and the periodic modulation module exports cyclically-varying
The first modulated charge current to node ISP and/or from node ISN decimation periods change first modulation discharge current, with
Modulate the periodic distribution of the spread spectrum point of the pierce circuit, the second modulation that the Stochastic Modulation module output changes at random
Charging current is to node ISP and/or from the second modulation discharge current that node ISN extractions change at random, to modulate the vibration
Each spread spectrum point of device circuit trembles frequency.
2. pierce circuit according to claim 1, which is characterized in that
The periodic modulation module includes cyclic counter and multiple first modulation units,
The clock signal of the cyclic counter, institute are formed based on the sawtooth oscillation signal or the switch controlling signal
It states cycle rate counter and exports periodically variable the first binary number of multidigit, each first modulation unit can generate predefined weight
First modulation charging tributary and predefined weight first modulation electric discharge tributary,
The control terminal of each first modulation unit is connected with corresponding one-bit digital signal in first binary number of multidigit, often
The one-bit digital signal that a first modulation unit is terminated to based on its control, controls whether it exports the first modulation charging Zhi Liuzhi
The node ISP；It is controlled whether to extract first from the node ISN and modulates electric discharge tributary, each first modulation unit output
The first modulation charging tributary accumulate the first modulated charge current corresponding with the first binary number；Each first modulation unit
Extract first modulation electric discharge tributary accumulate it is corresponding with the first binary number first modulation discharge current, due to the one or two into
Property one number time variation processed, the first modulated charge current and the first modulation discharge current also can cyclically-varyings therewith.
3. pierce circuit according to claim 2, which is characterized in that
The first modulation that each first modulation unit generates predefined weight with benchmark charging current described in estimated rate mirror image is filled
Electric tributary generates the first modulation electric discharge tributary of predefined weight with reference discharge electric current described in estimated rate mirror image.
4. pierce circuit according to claim 2, which is characterized in that
First modulation unit includes metal-oxide-semiconductor M14, metal-oxide-semiconductor M15, switchs K1, switchs K2,
Wherein, the source electrode of metal-oxide-semiconductor M14 is connected with power end, and drain electrode is connected through switching K1 with node ISP, grid and node
VISP is connected, and the control terminal for switching K1 is connected with the control terminal of the first modulation unit；The drain electrode of metal-oxide-semiconductor M15 is through switching K2 and section
Point ISN is connected, and grid is connected with node VISN, and source electrode is connected with ground node, and the control terminal and described first for switching K2 are adjusted
The control terminal of unit processed is connected.
5. pierce circuit according to claim 1, which is characterized in that
The Stochastic Modulation module includes random counter and multiple second modulation units,
The random counter exports the second binary number of multidigit changed at random each clock cycle,
The clock signal of the random counter is formed based on the sawtooth oscillation signal or the switch controlling signal, each
Second modulation unit can generate the second modulation charging tributary of predefined weight and the second modulation electric discharge tributary of predefined weight, often
The control terminal of a second modulation unit is connected with corresponding one-bit digital signal in second binary number of multidigit, and each second
The one-bit digital signal that modulation unit is terminated to based on its control, controls whether it exports the second modulation charging tributary to the section
Point ISP；It is controlled whether to extract second from node ISN and modulates electric discharge tributary, the second modulation of each second modulation unit output
Charging tributary accumulates the second modulated charge current of corresponding second binary number, the second tune that each second modulation unit extracts
System electric discharge tributary accumulates the second modulation discharge current of corresponding second binary number, since the second binary number changes at random,
Second modulated charge current and the second modulation discharge current can also change at random therewith.
6. pierce circuit according to claim 5, which is characterized in that
The second modulation that each second modulation unit generates predefined weight with benchmark charging current described in estimated rate mirror image is filled
Electric tributary generates the second modulation electric discharge tributary of predefined weight with reference discharge electric current described in estimated rate mirror image.
7. pierce circuit according to claim 5, which is characterized in that second modulation unit include metal-oxide-semiconductor M16,
Metal-oxide-semiconductor M17 switchs K3, switchs K4,
Wherein, the source electrode of metal-oxide-semiconductor M16 is connected with power end, and drain electrode is connected through switching K3 with node ISP, grid and node
VISP is connected, and the control terminal for switching K3 is connected with the control terminal of the second modulation unit；The drain electrode of metal-oxide-semiconductor M17 is through switching K4 and section
Point ISN is connected, and grid is connected with node VISN, and source electrode is connected with ground node, and the control terminal and described second for switching K4 are adjusted
The control terminal of unit processed is connected.
8. pierce circuit according to claim 1, which is characterized in that
First modulated charge current and first modulation discharge current transformable minimum value be more than the second modulated charge current and
The transformable minimum value of second modulation discharge current, alternatively,
First modulated charge current and first modulation discharge current transformable minimum value be more than the second modulated charge current and
The transformable maximum of second modulation discharge current.
9. pierce circuit according to claim 1, which is characterized in that first current source and the second current source include
Reference current source, metal-oxide-semiconductor M4, metal-oxide-semiconductor M7, metal-oxide-semiconductor M9, metal-oxide-semiconductor M10, metal-oxide-semiconductor M11,
Wherein, the source electrode of metal-oxide-semiconductor M4, metal-oxide-semiconductor M7 and metal-oxide-semiconductor M9 are connected with power end, grid and the metal-oxide-semiconductor M4 of metal-oxide-semiconductor M4
Drain electrode be connected；Reference current source is connected between the drain electrode of metal-oxide-semiconductor M4 and ground node, and the electric current of reference current source output claims
On the basis of electric current, the reference current is from the drain electrode of metal-oxide-semiconductor M4 flow direction ground node；Metal-oxide-semiconductor M4, metal-oxide-semiconductor M7, metal-oxide-semiconductor M9
Grid be connected with node VISP, the drain electrode of metal-oxide-semiconductor M7 is connected with the drain electrode of metal-oxide-semiconductor M10；The grid of metal-oxide-semiconductor M10 and drain electrode
It is connected with node VISN, source electrode is connected with ground node；The drain electrode of metal-oxide-semiconductor M9 is connected with node ISP；The drain electrode of metal-oxide-semiconductor M11
It is connected with node ISN, source electrode is connected with ground node, and grid is connected with node VISN.
10. pierce circuit according to claim 9, which is characterized in that the oscillator module further includes reference voltage
Generation circuit, the reference voltage generating circuit include metal-oxide-semiconductor M5, resistance R5 and R6,
Wherein, the source electrode of metal-oxide-semiconductor M5 is connected with power end, and grid is connected with node VISP, and drain electrode is connected with node A；Electricity
One end of resistance R5 is connected with node A, and the other end is connected with node B；One end of resistance R6 is connected with node B, the other end with
Ground node is connected.The voltage of the node A is first reference voltage, and the voltage of node B is second reference voltage.
11. pierce circuit according to claim 9, which is characterized in that
The reference current source includes metal-oxide-semiconductor M3, resistance R1, resistance R2, resistance R3 and resistance R4 and operational amplifier OPA,
Wherein, resistance R1, resistance R2 and resistance R3 are sequentially connected in series between power end and ground node；The operational amplifier is just
Connecting node between input terminal and resistance R2 and resistance R3 is connected, and negative input is connected through resistance R4 with ground node；
The drain electrode of the metal-oxide-semiconductor M3 is connected with the drain electrode of metal-oxide-semiconductor M4, the grid of the metal-oxide-semiconductor M3 and the output terminal of operational amplifier OPA
It is connected, the source electrode of the metal-oxide-semiconductor M3 is connected with the negative input of operational amplifier OPA.
12. pierce circuit according to claim 1, which is characterized in that the logic circuit includes first comparator, the
Two comparators, the first NAND gate and the second NAND gate,
The positive input of first comparator is connected with the first reference voltage, and the forward direction of negative input and the second comparator is defeated
Enter end and node O is connected, the negative input of the second comparator is connected with the second reference voltage；The first of first NAND gate is defeated
Enter end with the output terminal of first comparator to be connected, the second input terminal is connected with the output terminal of the second NAND gate；First NAND gate
Output terminal be connected with the output terminal of logic circuit；The first input end of second NAND gate and the output terminal phase of the first NAND gate
Even, the second input terminal is connected with the output terminal of the second comparator, wherein, the voltage value of the first reference voltage is more than the second benchmark
The voltage value of voltage.
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