JPH0758912B2 - High-speed settling D / A converter - Google Patents

Description

The present invention relates to a high-speed settling D / A converter with improved output characteristics of a voltage output type D / A converter.

"Prior Art" FIG. 8 is a diagram showing a configuration example of a conventional voltage output type D / A converter. An n-bit digital signal to be converted into an analog signal is given to the first to n-th switches S1 to Sn. For example, when the given bit signal is "1", the switches S1 to Sn corresponding to the respective bit signals are closed. Is made. Switches S1 to Sn
The signal current I / 2 ¹ , I / 2 ² ...... corresponding to the weighting of the bit signal (2 ¹ , 2 ² … 2 ⁿ ) given to each one terminal of
I / 2 ⁿ are respectively supplied from constant current sources C1 to Cn, and their signal currents I / 2 ¹ , I / 2 ² ...... I
/ 2 ⁿ is added to the current I from the reference current source 11 to add the operational amplifier 1
Supplied to 2. This added current i is converted into a voltage signal v by the operational amplifier 12 and output. For example, when digital data in which only the second bit is “1” is given, the second data
The signal current I / 2 ² = I / 4 from the constant current source C2 is given to the negative input terminal A of the operational amplifier 12 after being subtracted from the signal current I of the reference current source 11 considering the direction of the current in this example. .

The operational amplifier 12 constitutes a current-voltage conversion circuit 13 whose output signal is fed back to the negative input terminal A via the feedback resistor Rf and the feedback capacitor Cf, and the signal current i supplied to the negative input terminal A is a signal. The voltage v is converted and output. In the above example, the maximum converted output voltage V _MAX is output as a step voltage (V _MAX / 4) of a quarter.

[Problems to be Solved by the Invention] Even if the signal current i supplied to the current-voltage conversion circuit 13 changes in an ideal step waveform, the feedback resistor Rf and the feedback resistor constituting the current-voltage conversion circuit 13 are fed back. Due to the band limitation by the capacitor Cf, the output characteristic of the operational amplifier 12, and the like, it takes time for the output voltage v of the current-voltage conversion circuit 13 to settle to the voltage value corresponding to the signal current i. There is a problem that the operating characteristics of is poor and the D / A conversion speed is slow.

"Means for Solving Problems" In the present invention, digital data to be converted into an analog signal is stored in a temporary storage register, and the digital data is multiplied by a predetermined value by a multiplier. Further, the data multiplied by the predetermined value and the digital data already stored in the temporary storage register and previously converted into the analog signal are added by the adder and supplied to one input end of the multiplexer. Then, this addition signal is supplied from the multiplexer to the current-voltage conversion circuit only for a predetermined time at the beginning of the digital-analog conversion operation, instead of the digital data to be converted into the analog signal supplied to the other input terminal. .

[Operation of the Invention] According to the configuration of the present invention, instead of the predetermined signal current corresponding to the digital data to be converted into the analog signal, the excessive signal current or the excessive signal current is changed to the predetermined time at the start of the D / A conversion operation. By giving only the current-voltage conversion circuit, the initial rate of change of the voltage output is largely changed, so that the output voltage value corresponding to the digital data to be converted is rapidly changed.

[Embodiment] FIG. 1 is a diagram showing a main part of an embodiment of a high-speed settling D / A converter of the present invention. In this embodiment, a current output type D / A converter is used as the constant current source. In the present invention, the digital data D to be converted into an analog signal is supplied to the data processing circuit 21, and the digital data D is subjected to the data conversion processing by the data processing circuit 21 and then supplied to the current output type D / A converter 22. Supplied. That is, the data processing circuit 21 performs data conversion processing on the digital data so that the rate of change of the output voltage change of the current-voltage conversion circuit 23 becomes large, and the signal current i corresponding to the converted data is the current output type D. / A converter 22 to current-voltage conversion circuit 23
Is supplied to.

2 and 3 are a circuit diagram and a waveform diagram for explaining the principle of the present invention. For example, as described above, in the conventional voltage output type D / A converter, the switch 24 is turned on and the signal current i is supplied from the first constant current source 25 to the operational amplifier 26. Thus, when the value of the signal current i changes from the state of i = 0 to i = Io as shown in the waveform A of FIG. 3A, the output waveform diagram of the operational amplifier 26 is the waveform of FIG. 3B. A
As shown in, the voltage rises with a time constant To toward a voltage (Vo) corresponding to the magnitude of the signal current i = Io.

On the other hand, in the present invention, the signal current Io is supplied from the first constant current source 25 to the operational amplifier 26, and, for example, the current Io is supplied from the second constant current source 27 through the switch 28 for a predetermined period of time in the initial stage of the conversion operation. Only added and supplied. The waveform B of FIG. 3A shows how the signal current i of the present invention supplied to the operational amplifier 26 changes, and the waveform B of FIG. 3B shows the output of the operational amplifier 26 according to the signal current i. The waveform is shown. That is, when the signal current i = 2Io is supplied, the output of the operational amplifier 26 rapidly rises toward the voltage (2Vo). In the present invention, at the beginning of D / A conversion, a predetermined change amount of, for example, 2
When the doubled signal current i is supplied and the output of the operational amplifier 26 is changing toward the corresponding voltage (2Vo), when the predetermined voltage Vo corresponding to the digital data D _t is reached, or Immediately before, the switch 28 is turned off and the signal current i supplied to the operational amplifier 26 has a predetermined value i = Io.
Control to become. Therefore, compared to the case where the signal current i is set to the predetermined value i = Io from the beginning as shown by the waveform A in FIG. 3A, the predetermined converted voltage Vo can be reached more quickly, and after reaching the predetermined value. Since the signal current i is set and changed to a predetermined signal current i = Io corresponding to the reached output, the output voltage v of the operational amplifier 26 does not change further as shown by the waveform C.

The transfer function of this circuit when the signal current is controlled in this way is v (t) = 2 (1-ε- ^{(1 / T)} t)-{1-ε- ^{(1 / T) (t-t0 )} } U (t−t ₀ ), where t ₀ is the period in which the input current is doubled, and T is the time constant of the 1st delay. Here, the condition for v (t) = 1, in other words, the condition for the output voltage of the operational amplifier 26 to settle is t ₀ = Tln 2. That is, regardless of the magnitude of the signal current i supplied to the operational amplifier 26, the time t ₀ during which a double input signal has to be supplied is constant.

Now, if the settling time is defined as the time when the voltage output v of the operational amplifier 26 is within the voltage range of G when the difference from the target value is within the voltage range of G, the settling time t ₁ due to the normal first-order lag response is defined.
Is t ₁ = Tln (1 / G). On the other hand, the settling time t ₂ according to the present invention is t ₂ = Tln (2 / (1 + G)). Now, for example, the time constant T of the response output of the operational amplifier 26 is T = 5.31 ns, the number of bits of the digital data D supplied to the current output type D / A converter 22 is 12 bits, and the output v of the operational amplifier 26 is , And the time until the voltage value corresponding to the digital data D and the voltage value within (1/2) LSB are reached, t ₁ = 5.31 × 10 ^-9 × ln (1 / (1 / (2 ^{12 + 1} ))) = 47.8 ns t ₂ = 5.31 × 10 ^-9 × ln (2 / (1 + 1 / (2 ^{12 + 1} ))) = 3.68 ns. That is, it is shown that the settling time of the output voltage of the high speed D / A converter of the present invention is shortened to about 1/10 of the settling time of the conventional voltage output type D / A converter.

That, D _t-1 digital data already converted in the previous and the current digital data to be converted in the D _t, the data change amount is D _t -D _t-1. In the present invention, a change current corresponding to, for example, twice the data change amount is supplied to the current-voltage conversion circuit 23 as an initial current. That is, as shown in FIG. 4, this data change amount is added to the previous digital data D _t-1.
The initial data Dx is obtained by superimposing the data that is doubled from D _t −D _t-1.
Is output. That is, the data processing circuit 21 performs a conversion process of Dx = D _t-1 +2 (D _t −D _t-1 ) = D _t-1 + 2D _t −2D _t-1 = 2D _t −D _t-1 Converted data Dx to digital data
Output for a predetermined time instead of D _t .

In the embodiment shown in FIG. 1, in order to perform such a signal conversion operation, digital data D _t to be converted into an analog signal and a control signal described later are supplied.

The digital data D _t supplied to the data processing circuit 21 is supplied to one data input terminal A of the multiplexer 31 and is also supplied to the temporary storage register 32 and the multiplier 33. The temporary storage register 32 stores the digital data D _t-1 that was D / A converted last time.

The multiplier 33 uses the supplied digital data D _t as 2 in this example.
The arithmetic processing to obtain a doubled digital value is performed and the result is supplied to the data input terminal A of the adder 34. Further, in this embodiment, the previous data D _t-1 held in the temporary storage register 32 is the complement unit 35.
And is supplied to the other data input terminal B of the adder 34 via.

That is, the digital data D _t-1 of the temporary storage register 32 is subjected to the operation of converting it into a two's complement number by the complementer 35, and the two's complement value (−D _t-1 ) of this digital data is multiplied by the multiplier 33. Two
The data value (2D _t ) that has undergone the doubling operation is the adder 3
Added by 4 and output. This operation data is supplied to the data input terminal B of the multiplexer 31, and either the operation data or the digital data D _t to be converted into an analog signal supplied to the other input terminal A is output terminal Y thereof. Is selected and output.

On the other hand, the strobe signal s is given to the timing signal generation circuit 36, and its output is used as a control signal in the temporary storage register.
32, the multiplexer 31, and the current output type D / A converter 22.

FIG. 5 is a diagram showing a configuration example of the timing signal generation circuit 36, and FIG. 6 is a waveform diagram of each part of the timing signal generation circuit 36. Although not shown in the drawing, digital data D _t (waveform A) is supplied from the control circuit to the data processing circuit 21 shown in FIG.
The arithmetic data Dx obtained by performing the arithmetic processing as described above on the previous digital data D _t-1 held in the output section 34 is output from the adder 34. The signal is applied to the signal input terminal B of the multiplexer (waveform B). The strobe signal s (waveform C) is applied to the inverter 41 of the timing signal generation circuit 36 in accordance with this operation output. The output of the inverter 41 receives the signal delay d1 by the first delay element 42 and is given to the clock terminal of the flip-flop 43, and the flip-flop 43 outputs the signal at the rising timing of the supplied signal (a signal substantially inverted from the waveform D). The multiplexer control signal (waveform E) is output from the inverted signal output terminal Q / as logic "0". The multiplexer 31 shown in FIG. 1 selects the signal supplied to its signal input terminal B when this control signal (waveform F) given to its selection input terminal S is logic "0", and outputs it. Y
Output from. Therefore, the operation data Dx from the adder 34 is output from the output terminal Y (waveform F).

On the other hand, the output signal of the first delay element 42 is supplied to the one input terminal A of the gate circuit 45 and the second delay element 46 as an inverted signal (waveform D) thereof via the inverter 44. When the output signal (waveform D) of the inverter 44 is output from the gate circuit 45,
The third delay element 47 receives the signal delay d3 and outputs it as a signal of the negative pulse P1 of the waveform G via the inverter 48. This signal (negative pulse P1 of waveform G) is a current output type D / A converter 22.
To the control signal.

Further, the output signal (waveform D) of the inverter 44 receives the signal delay d2 at the second delay element 46, and the delayed signal (waveform H) is supplied to the reset terminal R of the flip-flop 43, and by this signal (waveform H). The flip-flop 43 is reset and the signal at its inverted signal output terminal Q / returns to the logic "1" as shown by the waveform E. The multiplexer 31 receives the signal of this logic "1" at the data selection terminal S, and replaces the data Dx of the input terminal B which has been selected and output until now with the digital data D _t given to the input terminal A thereof. Y output.
Therefore, the multiplexer 31 outputs the data Dx calculated by the data processing circuit 21 for the signal delay time d2 of the second delay element 46.

The delay signal (waveform H) of the second delay element 46 is supplied to the other input terminal B of the gate circuit 45. The output signal receives the signal delay d3 by the third delay element 47, and is supplied to the current output type D / A converter 22 as a control signal (negative pulse P2 of the waveform G) via the inverter 48.

Further, the delay signal (waveform H) of the second delay element 46 is supplied to the fourth delay element 52 via two inverters 49 and 51 in this example, and its output signal which has received the signal delay d4 is an inverter.
A temporary storage register as a control signal (waveform I) via 53
Supplied to 32. This control signal (waveform I) means the end of the D / A conversion operation, and the temporary storage register 32 uses this control signal (waveform I) as a clock signal to input digital data D _t to its input terminal. Read and memorize. This read data D _t is used when performing D / A conversion on the next data D _{t + 1} .

FIG. 7 is a constitutional view showing another embodiment of the present invention, which is an example constituted by using two current output type D / A converters 61 and 62.
That is, in this example, instead of changing the digital data supplied to one current output type A / D converter 61, the control unit 63
The output current of the current output type D / A converter 61 is made constant based on the control signal supplied from, and the initial current is added by using another current output type D / A converter 62. It is configured as follows.

In the above description, the initial change amount of the signal current is explained as being twice as large as the signal change amount, but it is not limited to twice, and may be three times or any other magnification. In that case, the set time t ₀ of the initial change amount is changed according to the speed of the output response of the current-voltage conversion circuit 21 at that magnification.

[Advantages of the Invention] As described above, according to the present invention, the output of the D / A converter, that is, the D / A conversion output can be obtained without using an expensive operational amplifier having good frequency characteristics. A high-performance, high-performance voltage output type D / A converter can be constructed at low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a high-speed settling D / A converter according to the present invention, FIG. 2 is a circuit diagram for explaining the principle of the present invention, and FIGS. 3A and 3B are shown in FIG. Fast settling D / A
An input / output waveform diagram showing an operation example of the converter, FIG. 4 is a diagram for explaining the data conversion process of the data processing circuit, FIG. 5 is a diagram showing a configuration example of the timing signal generating circuit, and FIG. 6 is a timing diagram. FIG. 7 is a waveform diagram of each part of the signal generating circuit, FIG. 7 is a configuration diagram showing another embodiment of the present invention, and FIG. 8 is a circuit diagram showing an example of a conventional voltage output type D / A converter. 11: reference current source, 12: operational amplifier, 13: current-voltage conversion circuit, 21: data processing circuit, 22: current output type D / A converter, 23:
Current-voltage conversion circuit, 24: switch, 25: first constant current source,
26: operational amplifier, 27: second constant current source, 28: switch, 31: multiplexer, 32: temporary storage register, 33: multiplier, 34:
Adder, 35: Complement, 36: Timing signal generation circuit, 41:
Inverter, 42: first delay element, 43: flip-flop,
44: Inverter, 45: Gate circuit, 46: Second delay element, 47:
Third delay element, 48: Inverter, 49, 51: Inverter, 52:
Fourth delay element, 53: inverter, Rf: feedback resistor, Cf: feedback capacitor, S1 to Sn: switch, C1 to Cn: constant current source.

Claims (1)

[Claims] 1. A voltage output type D / A converter which is composed of a current output type D / A converter and an integrating circuit which integrates its output, and which converts sequentially inputted digital data into an analog voltage, The temporary storage register for storing the digital data to be stored and outputting the previous storage data, the multiplier for supplying the input digital data and multiplying the value of the digital data by a predetermined value, and the output of the temporary storage register. An adder that adds a signal corresponding to the data and the output signal of the multiplier, a multiplexer that is supplied with the input digital data and the addition output of the adder, and selects and outputs one of them, D And a control circuit for controlling the multiplexer so that the output of the adder is selected for a certain time when a strobe signal for performing the A / A conversion operation is provided. Fast Settling D / A converter.