JPS63190913U - - Google Patents
Info
- Publication number
- JPS63190913U JPS63190913U JP8385687U JP8385687U JPS63190913U JP S63190913 U JPS63190913 U JP S63190913U JP 8385687 U JP8385687 U JP 8385687U JP 8385687 U JP8385687 U JP 8385687U JP S63190913 U JPS63190913 U JP S63190913U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- value
- sampling period
- input signal
- recorder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005070 sampling Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Measurement Of Current Or Voltage (AREA)
- Recording Measured Values (AREA)
Description
第１図は、この考案の一実施例の示す記録計の
ブロツク図、第２図は同記録計の動作を説明する
ためのサンプリング時刻からサンプリング時刻ま
での波形の変化例を示す図、第３図は、同記録計
における各サンプリング周期毎の記録例を示す図
である。
Ｓ：切替回路、１，２：ピークホールドアンプ
、４：Ａ／Ｄ変換器、５：ＣＰＵ、６：メモリ、
７：表示装置、８：記録装置。
FIG. 1 is a block diagram of a recorder according to an embodiment of this invention, FIG. 2 is a diagram showing an example of waveform change from sampling time to sampling time to explain the operation of the recorder, and FIG. The figure is a diagram showing an example of recording for each sampling period in the same recorder. S: switching circuit, 1, 2: peak hold amplifier, 4: A/D converter, 5: CPU, 6: memory,
7: Display device, 8: Recording device.
Claims (1)
デジタル値に変換してメモリに記憶するとともに
、そのメモリ値を出力して表示及び若しくは記録
する記録計において、 入力信号のピーク値を前記サンプリング周期の
間保持するピークホールド回路と、前記アナログ
入力信号をサンプリング周期毎にデジタル変換し
て取込むか、前記ピークホールド回路に入力し、
ピーク値をデジタル値に変換して、前記メモリに
記憶するかを選択する切替回路とを備えたことを
特徴とする記録計。[Scope of Claim for Utility Model Registration] A recorder that converts an analog input signal into a digital value at a predetermined sampling period and stores it in a memory, and outputs the memory value to display and/or record the peak value of the input signal. a peak hold circuit that holds the signal during the sampling period, and the analog input signal is digitally converted and taken in every sampling period, or is input to the peak hold circuit;
A recorder comprising: a switching circuit that selects whether to convert a peak value into a digital value and store it in the memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8385687U JPS63190913U (en) | 1987-05-29 | 1987-05-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8385687U JPS63190913U (en) | 1987-05-29 | 1987-05-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63190913U true JPS63190913U (en) | 1988-12-08 |
Family
ID=30937825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8385687U Pending JPS63190913U (en) | 1987-05-29 | 1987-05-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63190913U (en) |
-
1987
- 1987-05-29 JP JP8385687U patent/JPS63190913U/ja active Pending
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