JPH0237596U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram of the first embodiment of the present invention;
FIG. 2 is a waveform diagram of sampling pulses and control timing pulses for explaining the operation of the first embodiment of FIG. 1, FIG. 3 is a block diagram of the second embodiment of the present invention, and FIG. 1 is a block diagram of an example of a conventional motor control device. 1...Anti-aliasing filter circuit, 2
... Sampling pulse generation circuit, 3 ... Sample hold and A-D conversion circuit, 4 ... Frequency division circuit, 5, 5a ... Control calculation circuit, 6 ... Current detection signal, 7 ... Sampling pulse, 8 ... ... Control timing pulse, 9, 9a... Inverter command signal, 10... Noise processing circuit, 11... Low-pass filter.

Claims (1)

[Scope of utility model registration request] a sampling pulse generation circuit that generates a sampling pulse; a filter circuit that removes a frequency component of one-half or more of the sampling pulse from an input analog current detection signal; and a filter circuit that samples the output of the filter circuit with the sampling pulse. a sample hold and A-D converter circuit that holds and converts the digital signal into a digital signal; a frequency divider circuit that divides the sampling pulse at a predetermined frequency division ratio and outputs a control timing pulse; A motor control device comprising: a control calculation circuit that performs predetermined calculation processing at a pulse cycle and outputs an inverter command signal.