JPH0165529U

JPH0165529U -

Info

Publication number: JPH0165529U
Application number: JP1987160910U
Authority: JP
Priority date: 1987-10-21
Filing date: 1987-10-21
Publication date: 1989-04-26

Description

[Brief explanation of the drawing]

第１図は、この考案の一実施例を示す回路の構
成図、第２図は従来の回路を示す構成図である。図において、１はバツフア回路、２は電圧比較
型コンパレータ、３は逐次比較レジスタ、４は基
準電圧発生回路、５はＡ／Ｄ変換器、６はタイミ
ング信号発生回路、７はレジスタ、８はサンプル
ホールド回路、９は差動増幅器、１０はスイツチ
回路、１１は放電制御回路である。なお、図中同
一符号は同一または相当部分を示す。 FIG. 1 is a block diagram of a circuit showing an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional circuit. In the figure, 1 is a buffer circuit, 2 is a voltage comparison type comparator, 3 is a successive approximation register, 4 is a reference voltage generation circuit, 5 is an A/D converter, 6 is a timing signal generation circuit, 7 is a register, and 8 is a sample A hold circuit, 9 a differential amplifier, 10 a switch circuit, and 11 a discharge control circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A timing signal generation circuit that outputs a timing signal that controls the output of each component constituting the A/D conversion device, a buffer circuit that converts the impedance of an externally applied analog signal, and a D/A converter that converts the output of the buffer circuit. A voltage comparison type comparator that compares the voltage with the output voltage of the converter, a successive approximation register whose input is the output of the voltage comparison type comparator and whose operating speed is controlled by the output of the timing signal generation circuit, and a successive approximation register whose operation speed is controlled by the output of the timing signal generation circuit. An A/D comprising a D/A converter that converts the output into an analog voltage, a reference voltage generation circuit that supplies a reference voltage to the D/A converter, and a register that accumulates the output of the successive approximation register. In the conversion device, a sample and hold circuit samples and holds the output voltage of the D/A converter using the output of the timing signal generation circuit, and a difference that amplifies the difference between the output voltage of the sample and hold circuit and the output voltage of the buffer circuit. The present invention is characterized by comprising a dynamic amplifier, a switch circuit that switches between the output of the buffer circuit and the output of the differential amplifier using the output of the timing signal generation circuit, and a discharge control circuit that discharges the output of the sample and hold circuit. A/D conversion device.