JPS63530U

JPS63530U -

Info

Publication number: JPS63530U
Application number: JP9424786U
Authority: JP
Priority date: 1986-06-20
Filing date: 1986-06-20
Publication date: 1988-01-05

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例として示したデジタ
ル電圧出力回路の概略図、第２図は該回路の動作
の説明を補足する為に使用したグラフ、第３図は
比色検出器を備えた分析装置の検出系、第４図は
従来のデジタル電圧出力回路の概略図、第５図は
タイムチヤートである。１０：マルチプレクサ、１２：ＡＤ変換器、１
１：サンプルホールド回路、１４：タイミング発
生回路、１５：スイツチング機構、１６：ホール
ドコンデンサ、１７：バツフアアンプ、１９：演
算回路。 Fig. 1 is a schematic diagram of a digital voltage output circuit shown as an embodiment of the present invention, Fig. 2 is a graph used to supplement the explanation of the operation of the circuit, and Fig. 3 is equipped with a colorimetric detector. FIG. 4 is a schematic diagram of a conventional digital voltage output circuit, and FIG. 5 is a time chart. 10: multiplexer, 12: AD converter, 1
1: Sample and hold circuit, 14: Timing generation circuit, 15: Switching mechanism, 16: Hold capacitor, 17: Buffer amplifier, 19: Arithmetic circuit.

Claims

[Scope of utility model registration request]

In a digital voltage output circuit comprising a sample and hold circuit for holding an unknown analog input voltage signal and an AD converter for converting the analog input voltage signal held by the hold circuit into a digital voltage signal, the hold circuit includes: a mechanism for inputting two mutually different known analog reference voltage signals, and a known digital reference voltage signal corresponding to the two analog reference voltage signals;
an arithmetic circuit that outputs the output of the AD converter in response to an unknown analog input voltage signal as a digital voltage signal with an offset voltage corrected based on a digital voltage signal obtained by converting two analog reference voltage signals by the AD converter; Equipped with digital voltage output circuit.