JPH0339930U

JPH0339930U -

Info

Publication number: JPH0339930U
Application number: JP10084789U
Authority: JP
Priority date: 1989-08-29
Filing date: 1989-08-29
Publication date: 1991-04-17

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示す構成図、第
２図は従来回路を示す構成図である。図において、１は電圧比較型コンパレータ、２
は逐次比較レジスタ、３は基準電圧発生回路、４
はＤ／Ａ変換回路、５はタイミング回路、６はス
イツチ回路、７はラツチ回路、８は加算回路であ
る。なお、図中同一符号は同一または相当部分を
示す。 FIG. 1 is a block diagram showing an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional circuit. In the figure, 1 is a voltage comparison type comparator, 2
is a successive approximation register, 3 is a reference voltage generation circuit, and 4 is a successive approximation register.
5 is a D/A conversion circuit, 5 is a timing circuit, 6 is a switch circuit, 7 is a latch circuit, and 8 is an adder circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A voltage comparison type comparator that compares the externally applied measured signal and the output voltage of the A/D conversion circuit, and a successive approximation device that inputs the comparison results of the voltage comparison type comparator and whose operating speed is controlled by a timing circuit. register and D that converts the output value of the successive approximation register to an analog voltage.
/A conversion circuit and a reference voltage generation circuit that supplies a reference voltage to the D/A conversion circuit.
/D converter, an addition circuit that adds the output voltage of the D/A conversion circuit, which is an input signal of the voltage comparison type comparator, and the output voltage of the reference voltage generation circuit, and the comparison result of the voltage comparison type comparator. An A/D conversion device comprising: a latch circuit that latches the output voltage; and a switch circuit that controls whether or not the reference voltage generation circuit output voltage is supplied to the addition circuit based on the result of the latch circuit.