JPS6438030U - - Google Patents
Info
- Publication number
- JPS6438030U JPS6438030U JP12913887U JP12913887U JPS6438030U JP S6438030 U JPS6438030 U JP S6438030U JP 12913887 U JP12913887 U JP 12913887U JP 12913887 U JP12913887 U JP 12913887U JP S6438030 U JPS6438030 U JP S6438030U
- Authority
- JP
- Japan
- Prior art keywords
- digital signal
- offset voltage
- digital
- generating
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Analogue/Digital Conversion (AREA)
Description
図はこの考案によるＡ／Ｄ変換装置の一実施例
を示すブロツク図である。
１……サンプル・ホールド回路、２……アナロ
グアンプ、３１，３２，３３……比較器、４……
エンコーダ、５……アナログオフセツト電圧発生
器、６……デジタルオフセツト値発生器、７……
アナログ演算器、８……アナログ／デジタル変換
器、９……デジタル加算器。
The figure is a block diagram showing one embodiment of an A/D conversion device according to this invention. 1... Sample/hold circuit, 2... Analog amplifier, 31, 32, 33... Comparator, 4...
Encoder, 5... Analog offset voltage generator, 6... Digital offset value generator, 7...
Analog computing unit, 8...Analog/digital converter, 9...Digital adder.
Claims (1)
階の基準電圧と夫々比較する比較手段と、 この比較手段の出力に基づき前記入力アナログ
信号に対応する１つの前記基準電圧に対応するア
ナログのオフセツト電圧を発生するオフセツト電
圧発生手段と、 前記入力アナログ信号と前記オフセツト電圧発
生手段からのオフセツト電圧との差を求める第１
の演算手段と、 前記第１の演算手段で求められた前記電圧差を
第１のデジタル信号に変換するアナログ／デジタ
ル変換手段と、 前記比較手段の出力に基づき前記オフセツト電
圧に対応する第２のデジタル信号を発生するオフ
セツト値発生手段と、 前記第１のデジタル信号と第２のデジタル信号
とを加算若しくは減算し、前記入力アナログ信号
に対応するデジタル信号を得る第２の演算手段と を具えるアナログ／デジタル変換装置。[Claims for Utility Model Registration] Comparison means for comparing an input analog signal with reference voltages at multiple different levels, and one reference voltage corresponding to the input analog signal based on the output of the comparison means. an offset voltage generating means for generating an analog offset voltage to be inputted; and a first step for determining the difference between the input analog signal and the offset voltage from the offset voltage generating means.
calculating means, analog/digital converting means for converting the voltage difference obtained by the first calculating means into a first digital signal, and a second digital signal corresponding to the offset voltage based on the output of the comparing means. an offset value generating means for generating a digital signal; and a second calculating means for adding or subtracting the first digital signal and the second digital signal to obtain a digital signal corresponding to the input analog signal. Analog/digital converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12913887U JPS6438030U (en) | 1987-08-27 | 1987-08-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12913887U JPS6438030U (en) | 1987-08-27 | 1987-08-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6438030U true JPS6438030U (en) | 1989-03-07 |
Family
ID=31383133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12913887U Pending JPS6438030U (en) | 1987-08-27 | 1987-08-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6438030U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133331B2 (en) * | 1972-02-18 | 1976-09-18 | ||
| JPS5624825A (en) * | 1979-08-08 | 1981-03-10 | Sanyo Electric Co Ltd | Analog-digital converting circuit |
-
1987
- 1987-08-27 JP JP12913887U patent/JPS6438030U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5133331B2 (en) * | 1972-02-18 | 1976-09-18 | ||
| JPS5624825A (en) * | 1979-08-08 | 1981-03-10 | Sanyo Electric Co Ltd | Analog-digital converting circuit |
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