JPS61152143U - - Google Patents
Info
- Publication number
- JPS61152143U JPS61152143U JP3558685U JP3558685U JPS61152143U JP S61152143 U JPS61152143 U JP S61152143U JP 3558685 U JP3558685 U JP 3558685U JP 3558685 U JP3558685 U JP 3558685U JP S61152143 U JPS61152143 U JP S61152143U
- Authority
- JP
- Japan
- Prior art keywords
- output signal
- converter
- fourier transform
- signal
- sample
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003321 amplification Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Complex Calculations (AREA)
Description
第１図は本考案の一実施例を示すブロツク図、
第２図は従来の離散フーリエ変換装置を示すブロ
ツク図である。図において、
１，２，１３……Ａ／Ｄ変換器、３，７，１４
……メモリ回路、４……Ｄ／Ａ変換器、５……差
動増幅器、６，１２……サンプルホールド回路、
８，１５……フーリエ変換演算器、９……ラツチ
回路、１０……加算器、１１，１６……制御信号
発生器、である。
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional discrete Fourier transform device. In the figure, 1, 2, 13...A/D converter, 3, 7, 14
...Memory circuit, 4...D/A converter, 5...Differential amplifier, 6, 12...Sample and hold circuit,
8, 15... Fourier transform computing unit, 9... latch circuit, 10... adder, 11, 16... control signal generator.
Claims (1)
ホールド回路と、このサンプルホールド回路の出
力信号をデイジタル信号に変換する第１のＡ／Ｄ
変換器と、この第１のＡ／Ｄ変換器の出力信号を
アナログ信号に変換するＤ／Ａ変換器と、前記サ
ンプルホールド回路の出力信号と前記Ｄ／Ａ変換
器の出力信号との差を増幅する差動増幅器と、こ
の差動増幅器の出力信号をデイジタル信号に変換
する第２のＡ／Ｄ変換器と、これら第１および第
２のＡ／Ｄ変換器の各出力信号を時系列データと
して格納するメモリ回路と、前記各時系列データ
を別々にフーリエ変換するフーリエ変換演算器と
、前記各時系列データの各フーリエ変換結果のビ
ツト位置をずらして加算を行なう加算器とを備え
、前記アナログ入力信号に離散フーリエ変換処理
を行なうことを特徴とする離散フーリエ変換装置
。 A sample and hold circuit that sequentially samples an analog input signal, and a first A/D that converts the output signal of this sample and hold circuit into a digital signal.
a converter, a D/A converter that converts the output signal of the first A/D converter into an analog signal, and a difference between the output signal of the sample and hold circuit and the output signal of the D/A converter. A differential amplifier for amplification, a second A/D converter for converting the output signal of this differential amplifier into a digital signal, and a time series data of each output signal of these first and second A/D converters. a Fourier transform calculator that separately performs Fourier transform on each of the time series data; and an adder that performs addition by shifting the bit positions of each Fourier transform result of each of the time series data; A discrete Fourier transform device characterized by performing discrete Fourier transform processing on an analog input signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3558685U JPS61152143U (en) | 1985-03-14 | 1985-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3558685U JPS61152143U (en) | 1985-03-14 | 1985-03-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61152143U true JPS61152143U (en) | 1986-09-20 |
Family
ID=30539998
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3558685U Pending JPS61152143U (en) | 1985-03-14 | 1985-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61152143U (en) |
-
1985
- 1985-03-14 JP JP3558685U patent/JPS61152143U/ja active Pending
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