JPH0181580U - - Google Patents
Info
- Publication number
- JPH0181580U JPH0181580U JP1987177320U JP17732087U JPH0181580U JP H0181580 U JPH0181580 U JP H0181580U JP 1987177320 U JP1987177320 U JP 1987177320U JP 17732087 U JP17732087 U JP 17732087U JP H0181580 U JPH0181580 U JP H0181580U
- Authority
- JP
- Japan
- Prior art keywords
- output
- converters
- subtracting
- converter
- average
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000001228 spectrum Methods 0.000 description 1
Landscapes
- Complex Calculations (AREA)
Description
第1図は本考案に係るFFTアナライザの一実
施例を示す構成ブロツク図、第2図は第1図装置
の平均値回路11,12の具体例を示す構成ブロ
ツク図、第3図は第1図装置の加減算回路15の
具体例を示す構成ブロツク図、第4図は従来のF
FTアナライザを示す構成ブロツク図、第5図お
よび第6図は第4図装置で生じる誤差モードを示
す説明図、第7図は信号処理演算部6のパワース
ペクトムラム出力を示す説明図である。
3,4……A/D変換器、11,12……平均
値演算手段、13……引算手段、15……加減算
手段。
FIG. 1 is a block diagram showing an embodiment of the FFT analyzer according to the present invention, FIG. 2 is a block diagram showing a specific example of the average value circuits 11 and 12 of the device shown in FIG. 4 is a block diagram showing a specific example of the adder/subtractor circuit 15 of the device;
5 and 6 are explanatory diagrams showing the error modes occurring in the apparatus shown in FIG. 4, and FIG. 7 is an explanatory diagram showing the power spectrum output of the signal processing calculation unit 6. 3, 4... A/D converter, 11, 12... Average value calculation means, 13... Subtraction means, 15... Addition/subtraction means.
Claims (1)
値に変換する2つのA/D変換器と、この2つの
A/D変換器のそれぞれ複数の出力値を平均演算
する2つの平均値演算手段と、この2つの平均値
演算手段の出力の差を演算する引算手段と、この
引算手段の出力に関連する出力値を一方の前記A
/D変換器の出力値に加算し他方の前記A/D変
換器の出力値から減算する加減算手段とを備え、
2つのA/D変換器が交互に出力するデータ系列
に含まれるナイキストモードの誤差成分を除去す
るように構成したことを特徴とするFFTアナラ
イザ。 two A/D converters that alternately sample input signals and convert them into digital values; two average value calculation means that average a plurality of output values of each of these two A/D converters; a subtracting means for calculating the difference between the outputs of the two average value calculating means; and an output value related to the output of the subtracting means.
addition/subtraction means for adding to the output value of the A/D converter and subtracting from the output value of the other A/D converter;
An FFT analyzer characterized in that it is configured to remove Nyquist mode error components contained in data series alternately output by two A/D converters.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17732087U JPH0725716Y2 (en) | 1987-11-20 | 1987-11-20 | FFT analyzer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17732087U JPH0725716Y2 (en) | 1987-11-20 | 1987-11-20 | FFT analyzer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0181580U true JPH0181580U (en) | 1989-05-31 |
JPH0725716Y2 JPH0725716Y2 (en) | 1995-06-07 |
Family
ID=31468988
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17732087U Expired - Lifetime JPH0725716Y2 (en) | 1987-11-20 | 1987-11-20 | FFT analyzer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0725716Y2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019132806A (en) * | 2018-02-02 | 2019-08-08 | アンリツ株式会社 | Signal measuring device and signal measuring method |
-
1987
- 1987-11-20 JP JP17732087U patent/JPH0725716Y2/en not_active Expired - Lifetime
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019132806A (en) * | 2018-02-02 | 2019-08-08 | アンリツ株式会社 | Signal measuring device and signal measuring method |
Also Published As
Publication number | Publication date |
---|---|
JPH0725716Y2 (en) | 1995-06-07 |
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