JPH0725716Y2 - FFT analyzer - Google Patents

Description

[Detailed Description of the Invention] << Industrial Application Field >> The present invention relates to correction of data when two A / D converters are operated in a signal input section of an FFT analyzer or the like to improve the sampling speed. Is.

<< Prior Art >> FIG. 4 is a block diagram showing an outline of prior art by the applicant of the present application. In the data input section, this is
By operating the A / D converters in parallel, the speed of the FFT analyzer (FFT: Fast Fourier Transform) is improved, and 2 is an attenuator to which an input signal is applied via the input terminal 1 and an anti-aliasing filter. Including, 3 and 4 are two A / D for A / D converting this attenuator 2.
A converter that includes a sample and hold function, 8 is this A /
A data bus 5 from which data is output from the D converters 3 and 4 is a memory for storing data on the data bus 8, and 6 is an FRT operation for the data read from the memory 5 and the output is a CRT display. A signal processing operation unit (abbreviated as DSP hereinafter) 7 is an inverter (NOT circuit) for applying a reverse phase clock to the A / D converters 3 and 4. After the signal input to terminal 1 passes through the attenuator 2, the A / D converters 3 and 4 perform A / D conversion with half-cycle offsets by the clocks of opposite phases, and the converted digital data is transferred to the data bus. 8 is output alternately. This output data is the waveform memory 5
Is written into the memory 5 and the DSP 6 performs an operation on the data read from the memory 5 and displays the output by CRT.

<< Problems to be solved by the device >> However, in the device having the above configuration, the attenuator 2, the A / D converters 3, 4 have offsets, drifts, non-uniformity of characteristics, etc. In the acquired data, the error in the DC mode as shown in FIG. 5 and the error in the Nyquist mode as shown in FIG.
Error that occurs at the Nyquist frequency corresponding to double). Here, Δt is the sampling interval of the A / D converters 3 and 4. When FFT calculation such as block floating is performed in DSP6 without removing these errors, the power spectrum has large amplitudes of the DC component error component 72 and the Nyquist mode error component 73 as shown in FIG. In addition, the dynamic range of the component of the signal 71 to be originally analyzed may be reduced. In FIG. 7, fs represents a sampling frequency and fs / 2 represents a Nyquist frequency.
In the figure, the dotted line 74 represents the area displayed on the CRT. Regarding the DC mode error component, due to the nature of the FFT analyzer, A
The method of performing correction based only on the acquired data after / D conversion cannot be used because it also removes the DC component of the signal input from terminal 1, and the conventional method of using calibration data etc. Apply the correction method in the FFT analyzer that uses the A / D converter. However, in the case of Nyquist mode error, even if this correction method is applied, offset, drift, misalignment of A / D converters 3, 4 etc. change slowly from moment to moment, so it is possible to correct the acquired data. There is no guarantee.

The present invention has been made to solve the above-mentioned problems, and in an FFT analyzer having an input unit that performs double sampling rate conversion by using two A / D converters, two FFT analyzers are provided. The purpose is to realize elimination of Nyquist mode error caused by non-uniformity of characteristics of A / D converter based only on acquired data.

<< Means for Solving the Problems >> In order to solve the above problems, the present invention comprises first and second A / D converters for alternately sampling an input signal and converting it into a digital value, and these two A / D converters. First and second average value calculating means for calculating an average value of respective output values of the / D converter, and subtracting the output value of the second average value calculating means from the output value of the first average value calculating means Subtraction means for multiplying, a multiplication means for multiplying an output value obtained from the subtraction means by 1/2, and a memory for alternately storing the digital values obtained from the first and second A / D converters, If the data is obtained from the first A / D converter, the output value of the multiplication means is subtracted from the output data of the memory, and if it is the data obtained from the second A / D converter, Adding and subtracting means for adding the output data of the memory to the output value obtained from the multiplying means; A signal processing operation unit for performing signal processing on the output of the calculation means, and removing the Nyquist mode erroneous calculation component included in the data series alternately output by the first and second A / D converters. And

<Example> Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of an FFT analyzer according to the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals and the description thereof will be omitted. The clock-related circuit of FIG. 4 is omitted here. 11, 12 is an average value circuit for inputting the digital outputs of the A / D converters 3, 4, respectively, 13 is a subtraction circuit for calculating the difference between the outputs of the average value circuits 11, 12, 14
Is a multiplication circuit for inputting the output of the subtraction circuit 13, and 15 is an addition / subtraction circuit for inputting the output of the multiplication circuit 14 and the output of the memory 5 and outputting them to the DSP circuit 6.

Next, the operation of the apparatus having the above configuration will be described. Since the Nyquist mode error generally exists at the frequency fs / 2 that is not displayed on the CRT as shown in FIG. 7, it is safe to remove the Nyquist component of the signal input from the terminal 1 at the same time. Therefore, in the present invention, as shown below, the Nyquist mode error is removed from the digital data after the data bus 8. The signal input to the terminal 1 is A / D converted and stored in the memory 5 as in the case of FIG. 4, but the even-numbered data among the stored data is 1 → 2 → 3 →
It goes through the path of 8 → 5 and the odd number data is 1 → 2 → 4 →
It is assumed that A / D conversion is performed through the path of 8 → 5. The average value circuit 11 calculates the average value of the even-numbered data at the same time as the conversion in the A / D converter 3. After the A / D conversion is completed for all data, the average value output is the subtraction circuit 13
One of the inputs. For odd-numbered data,
At the same time as the exchange in the A / D converter 4, the average value is calculated by the average value circuit 12, and after the A / D conversion is completed for all data, the average value becomes the other input of the subtraction circuit 13. The subtraction circuit 13 calculates the difference between the two average values, and the output is the multiplier 14
Is multiplied by 1/2. When the DSP 6 starts calculation processing such as FFT, each time the DSP 6 fetches data from the memory 5, if the data is an even-numbered data, the addition / subtraction circuit 15 causes the memory 5
The data obtained by subtracting the output data of the multiplier 14 from the read data of is passed to the DSP 6. On the contrary, if the data is odd-numbered, the adder / subtractor circuit 15 passes the read data of the memory 5 and the output data of the multiplier 14 to the DSP 6.

FIG. 2 is a configuration block diagram showing a concrete example of the average value circuit 11 (12) in FIG. Reference numeral 31 is an adder having the output of the A / D converter 3 (4) as one input, 32 is a latch circuit which latches the output of the adder 31 and uses its output as the other input of the adder 31, 33 Is a shifter which constitutes a divider and receives the output of the latch circuit 32 and outputs it to the subtraction circuit 13. FF
Since the number of data points N handled by T is represented by N = 2n, a divider can be constructed using a shifter. The latch circuit 32 latches the output data of the adder 31 each time the output of the A / D converter 3 (4) changes. Finally, the contents of the adder 31 is A /
The integrated value of each output data from the D converter 3 (4) is shown. This integrated value is input to the shifter 33 via the latch circuit 32 and divided by the number of data points N to produce an average value output. If the number of data points N is fixed, the divider can also be configured by wired logic (fixed wiring of a logic circuit).

FIG. 3 is a block diagram showing the configuration of the addition / subtraction circuit 15 shown in FIG. 41 is a sign inversion circuit that inputs the output of the multiplier 14, 42 is a buffer that inputs the output of this sign inversion circuit 41, 43 is a buffer that inputs the output of the multiplier 14, 44 is the output of the buffer 42 or 43 One input, memory 5
It is an adder that outputs the output of to the other input and outputs it to DSP6.
When the even-numbered data is input from the memory 5, the buffer 42 is enabled, the output data of the multiplier 14 is sign-inverted by the sign inverting circuit 41, and then the adder 44 adds the memory 5 to the memory 5.
Add with the data from. As a result, the data obtained by subtracting the output data of the multiplier 14 from the output data of the memory 5 is output to the DSP 6. When the odd-numbered data is input from the memory 5, the buffer 43 is enabled, and the output data of the multiplier 14 is added to the data from the memory 5 by the adder 44. As a result, the data obtained by adding the output data of the memory 5 and the output data of the multiplier 14 is output to the DSP 6.

Next, the operation of the above device will be described using mathematical expressions. The number of data points processed by the DSP6 is N points, the signal input from the terminal 1 is x (t), the Nyquist mode error due to uneven characteristics of the A / D converters 3 and 4 is m, and A / D conversion is performed. In container 3 +
It is assumed that the m, A / D converter 4 has an error of -m.

The reason why the errors of + m and -m are generated in this way is that the Nyquist mode error is generated by the DC offset (difference) between the two A / D converters.

This will be described with reference to FIG. DC of A / D converters 3, 4
Let each offset be E ₁ E ₂ . Corresponds to this central value
An error (here, m) of the same value occurs around the DC error (= (E ₁ + E ₂ ) / 2). FIG. 5 shows the error only in this DC offset, and FIG. 6 shows the error (+ m, −m) in the Nyquist mode. When the data stored in the memory 5 in the circuit of FIG. 1 is expressed using such conditions, {x (0) + m, x (1) −m, x (2) + m, x (3) −m , ...,
x (N-1) -m} (1) In the conventional method, since the data in the memory 5 is directly processed by the DSP 6, the Fourier transform X (N / 2) corresponding to the Nyquist frequency (fs / 2) is However, e ^{−j2 π nN / 2} is 1 when n = 2k and −1 when n = 2k + 1. The purpose of the present invention is to remove the component of equation (2).

Since the average value circuit 11 averages the even-numbered data,
The output data D ₁₁ is Similarly, the output data D ₁₂ of the average value circuit ₁₂ is Therefore, the output data D ₁₃ of the multiplier 14 is Becomes Next, in the adder / subtractor circuit 15, the output data of the memory 5 expressed by the equation (1) is added to the output data D ₁₃ expressed by the equation (3).
Subtraction, addition, subtraction, addition, ... Addition and subtraction circuit 15 outputs data. Becomes Next, the DSP6 performs signal processing. The Fourier transform X (N / 2) corresponding to the Nyquist frequency (fs / 2) of the data in equation (4) is Therefore, the Fourier transform X (N / 2) corresponding to the Nyquist frequency (fs / 2) is removed. Further, as is clear from the equation (4), since the above apparatus does not perform corrections other than the Nyquist mode, the Fourier transform {X (0), X (1), ..., X ( N / 2-1)} and {X (N
/2+1),...,X(N-1)} is not affected at all.

According to the FFT analyzer having such a configuration, the Nyquist mode error can be removed, so that the dynamic range can be secured in the signal processing of the DSP 6.

Further, not only the Nyquist mode error caused by the irregularity of the A / D converter but also all the Nyquist mode errors can be removed, and the frequency components other than the Nyquist mode are not affected at all.

Further, since it is a complete post-processing by digital operation, it is possible to cope with an error variation and the like, and the removal of the Nyquist mode is sure as compared with the method in which the correction is made in the analog section.

If the shifter 33 in the average value circuit 11 (12) of FIG. 2 shifts it to 1/2, the multiplier 14 can be omitted in FIG.

Further, the average value circuit 11, 12, the subtraction circuit 13, in the above embodiment,
The multiplier 14, the addition / subtraction circuit 15 and the like can be realized by software.

<< Advantages of the Invention >> As described above, according to the present invention, in the FFT analyzer having the input section for performing the conversion of the double sampling rate by using the two A / D converters, the two A / D converters are provided. Nyquist mode error generated due to non-uniformity of converter characteristics can be removed with a simple configuration.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural block diagram showing an embodiment of an FFT analyzer according to the present invention, and FIG. 2 is an average value circuit 11 of the apparatus shown in FIG.
FIG. 3 is a block diagram showing a concrete example of (12), FIG. 3 is a block diagram showing a concrete example of the addition / subtraction circuit 15 of the apparatus shown in FIG. 1, and FIG. 4 is a block diagram showing a conventional FFT analyzer. And FIG. 6 is an explanatory diagram showing an error mode generated in the apparatus of FIG. 4, FIG. 7 is an explanatory diagram showing a power spectrum output of the signal processing operation unit 6, and FIG. 8 is a diagram showing two A / D converters. It is explanatory drawing which shows the error which occurs. 3, 4 ... A / D converter, 11, 12 ... Average value computing means, 13 ... Subtraction means, 15 ... Addition / subtraction means.

Claims (1)

[Scope of utility model registration request] 1. A first and a second A / D converter for alternately sampling an input signal and converting it into a digital value, and a first for calculating an average value of output values of these two A / D converters. And second subtraction means for subtracting the output value of the second average value calculation means from the output value of the first average value calculation means, and the output value obtained from this subtraction means. Multiplication means for multiplying by 1/2, a memory for alternately storing digital values obtained from the first and second A / D converters, and data obtained by the first A / D converters For example, the output value of the multiplication means is subtracted from the output data of the memory, and if the data is obtained from the second A / D converter, the output data of the memory is added to the output value obtained from the multiplication means. An adder / subtractor, and a signal processing operation unit for processing the output of the adder / subtractor. The FFT analyzer is characterized in that a Nyquist mode erroneous calculation component included in a data sequence alternately output by the first and second A / D converters is removed.