JP5203440B2 - Harmonic component measuring device - Google Patents

Description

  The present invention relates to a harmonic component measuring apparatus, and more particularly to improvement of an apparatus that measures a voltage effective value, a current effective value, an active power, and the like by digital calculation and also measures a harmonic component of a voltage and a current.

  In recent years, power converters typified by inverters have been widely used in various household electric appliances and industrial electric appliances in order to perform detailed operation control and improve power utilization efficiency. Along with this, harmonic components generated during the switching operation of these power converters may affect other devices, causing unnecessary operation or damage.

  Therefore, in order to prevent these problems from occurring, when measuring AC power, voltage harmonic components, current harmonic components, active power harmonic components, etc. are measured in addition to the effective voltage value, effective current value, and active power. It is required to be able to analyze.

  FIG. 10 is a block diagram illustrating the configuration of the harmonic component measuring apparatus disclosed in Patent Document 1. In FIG. The voltage input circuit 1 normalizes the input voltage to a level suitable for the processing of the subsequent circuit. The A / D converter 2 converts the voltage input by the voltage input circuit 1 into a digital signal. The zero cross detector 3 detects that the voltage input from the voltage input circuit 1 crosses the zero level, and the detection output is inverted by detecting that the input voltage changes from LOW to HIGH or HIGH to LOW. To do. The detection output frequency of the zero cross detector 3 is the fundamental frequency of the input voltage signal.

  The current input circuit 4 normalizes the input current to a level suitable for the processing of the subsequent circuit. The A / D converter 5 converts the current input from the current input circuit 4 into a digital signal. The zero-cross detector 6 detects that the current input from the current input circuit 4 crosses the zero level, and the detection output is inverted by detecting that the input current changes from LOW to HIGH or HIGH to LOW. To do. The detection output frequency of the zero cross detector 6 becomes the fundamental frequency of the input current signal.

  The conversion data of the instantaneous voltage value output from the A / D converter 2 and the conversion data of the instantaneous current value output from the A / D converter 5 are input to the DSP 7 and the DSP 17. The output signals of the zero cross detectors 3 and 6 are input to the switch 9.

  The switch 9 selects one of the outputs of the zero-cross detectors 3 and 6 according to the setting of the CPU 10 and inputs it to the PLL sampling clock generator 13. Note that which output of the zero-cross detectors 3 and 6 is used depends on the measurement object. For example, the output of the voltage zero-cross detector 3 is used in the case of a device in which the current waveform is distorted, and the output of the current zero-cross detector 6 is used in the case where the voltage waveform is distorted as in an inverter-controlled device. .

  The fixed sampling clock generator 12 generates an arbitrarily set fixed sampling clock. The fixed sampling clock is input to the A / D converters 2 and 5, and the A / D converters 2 and 5 perform A / D conversion based on this. The fixed sampling clock is also input to the flag circuit 23.

  The PLL sampling clock generator 13 generates a PLL sampling clock that is an integral multiple of the output signal of the zero-cross detector 3 or the zero-cross detector 6 that is selectively input via the switch 9 and outputs the PLL sampling clock to the flag circuit 23.

  The counter clock generator 22 generates a counter clock for increasing the count values of the counter A19 and the counter B21 by one count. The frequency of the counter clock is assumed to be sufficiently higher than the frequency of the fixed sampling clock.

  The counter A19 counts up for each counter clock only from one fixed sampling clock to the next fixed sampling clock. When the next fixed sampling clock comes, the count value of the counter A19 is read and held in the latch A18, and the counter A19 initializes the count value to zero.

  The counter B21 counts up for each counter clock during a period from a certain fixed sampling clock to the next PLL sampling clock. When the PLL sampling clock comes, the counter B21 initializes the count value to zero. However, if there is no PLL sampling clock between a certain fixed sampling clock and the next fixed sampling clock, the count value is initialized to 0 at the timing when the next fixed sampling clock is present. The count value of the counter B21 is read and held in the latch B20 at the timing when the fixed sampling clock arrives.

  When there is a PLL sampling clock between the fixed sampling clock and the next fixed sampling clock, the flag circuit 23 holds the output at 1 at the timing of the next fixed sampling clock. If there is no PLL sampling clock in the meantime, the output is held at 0.

  The DSP 7 (Digital Signal Processor) includes an instantaneous voltage value v (n) converted into a digital value by the A / D converter 2 and an instantaneous current value a (n) converted into a digital value by the A / D converter 5. Based on the above, the effective voltage value, effective current value, and active power are calculated.

  The DSP 17 reads the output values of the A / D converter 2 and the A / D converter 5 that have been A / D converted at the timing of the fixed sampling clock. At this time, one A / D value is read and the previous A / D value is also stored in the DSP 17. Further, the outputs of the latch A18, the latch B20 and the flag circuit 23 are read at the timing of the fixed sampling clock.

  The DSP 17 performs the following interpolation operation when the output of the flag circuit 23 is 1. An example of the nth fixed sampling clock whose flag is 1 will be described with reference to FIG. FIG. 11 is a diagram for explaining the linear interpolation disclosed in Patent Document 1. In FIG.

  It is assumed that the A / D value read at the timing of the nth fixed sampling clock is X (n), the value of the latch A18 is Cfix (n), and the value of the latch B20 is Cpll (n). The A / D value read at the timing of the (n−1) -th clock pulse of the fixed sampling clock generator 12 is assumed to be X (n−1). Then, the following calculation is performed to obtain the linearly interpolated A / D value X_HRM (m). An arithmetic expression of X_HRM (m) is shown in FIG.

  The A / D value X_HRM (m) obtained by the linear interpolation in this way is set as the target data for the FFT calculation performed by the DSP 17. When performing a 1024-point FFT operation, X_HRM (m) between m = 1 and 1024 is obtained, and the FFT operation is performed on this X_HRM (m).

  The DSP 17 calculates the fundamental wave component and the harmonic component of the voltage by performing such an FFT operation on the instantaneous voltage value, and calculates the fundamental wave component and the harmonic component of the current by performing the FFT operation on the instantaneous current value. The fundamental power component and the harmonic component of the active power are calculated based on the FFT result of the voltage and the FFT result of the current.

  The effective voltage value V, the effective current value A, the active power P calculated by the DSP 7, and the fundamental wave component and the harmonic component of the voltage, current, and active power calculated by the DSP 17 are sent to the display 11 via the CPU 10. Is displayed. The CPU 10 displays each measured value calculated by the DSPs 7 and 17 on the display 11 and controls the switch 9 by an operation input from the operation unit 14.

  When the FFT calculation is performed with the number of points that is an integral multiple of zero cross in this way, each frequency component of the FFT calculation result matches the frequency of the fundamental and harmonic components of the voltage / current, and the input signal is lost. The FFT calculation can be performed in real time, and the fundamental wave component and the harmonic component can be calculated with high accuracy. In particular, by performing linear interpolation, components that are not originally included in the input waveform when the FFT operation is performed can be reduced, and the amplitude of the components that are originally included can be obtained more accurately.

  In place of the PLL sampling clock generator 13, the sampling clock generator proposed in Patent Document 2 can be used to generate a sampling clock N times the basic frequency with high accuracy. In Patent Document 2, the basic frequency based on zero crossing is counted by a high-speed reference clock, and this is divided by a constant N to obtain the clock pulse interval (number of clocks) for performing the FFT operation. The number of clocks is down-counted by the integer part when divided by the constant N, and the interpolation timing is output as a signal pulse.

JP 2009-264753 A JP 2007-198763 A

  FIG. 12 is a diagram for explaining the problem. In the apparatus described with reference to FIG. 10, assuming that voltage input = 1 kHz sine wave, current input = composite wave of 1 kHz sine wave with amplitude 10A and 200 kHz sine wave with amplitude 1A, the current input waveform is as shown in FIG. become. The switch 9 is set as the output of the zero cross detector 3 on the voltage side (because the current side is disturbed) and input to the PLL sampling clock generator 13. At this time, if the fixed sampling clock is 2 MHz and the output magnification with respect to the input of the PLL sampling clock is 512 times, the PLL sampling clock is 1 kHz × 512 = 512 kHz.

The FFT result of the current input at this time (the number of FFT points is 512) is as shown in FIG. In this figure, the horizontal axis is the harmonic order, and the vertical axis is the dB display with the amplitude of each order component being 20 log ₁₀ (I). 1A = 0 dB. Since the current waveform is a combined waveform of only the first-order 10A component and the 200th-order 1A component, the FFT result should ideally be as shown in FIG. However, in FIG. 12B, components also exist in other orders, and the larger ones exceed −40 dB.

  Next, the cause of this will be described. FIG. 13 is a diagram for explaining the cause of the problem. FIG. 13A shows the input waveform of 110 μs to 120 μs in FIG. 12A and the sampling points when this is AD-converted. ● is an AD value when AD conversion is performed at a timing of a fixed sampling clock (here, 2 MHz). Δ is an AD value that is linearly interpolated from the AD values at the two points before and after at the interpolation timing (here, 512 kHz).

  When the frequency included in the input waveform is close to the frequency of the fixed sampling clock (in this example, the maximum frequency included in the input waveform: fixed sampling frequency = 200 kHz: 2 MHz = 1: 10), linear interpolation cannot be accurately performed. Interpolated at a position deviated from the input waveform. When the FFT calculation is performed on the interpolation data deviated from the input waveform, that is, the distorted waveform data, harmonic components that are not included in the original input waveform are included.

  In order for the conventional technique to bring the FFT result closer to the ideal value, the fixed sampling clock may be set sufficiently high. For example, if the fixed sampling clock is set to 12 MHz (maximum frequency included in the input waveform: fixed sampling frequency = 200 kHz: 12 MHz = 1: 60), the result is as shown in FIG. 70 dB or less. However, in order to do so, it is necessary to use a high-speed AMS / D converter 2 and 5 in FIG. 10 at a speed of 10 MS / s (megasample / second) or more, which increases costs. There's a problem. Even with linear interpolation, harmonic components not included in the original input waveform can be reduced to some extent, but further reduction is desired.

  By the way, the resolution of the time axis when performing linear interpolation is determined by the frequency of the counter clock generator 22 in FIG. 10 and the frequency of the fixed sampling clock as shown in FIG. For example, when the counter clock is 132 MHz and the fixed sampling clock is 2 MHz, the resolution is Cfix (n) = 132 MHz / 2 MHz = 66 counts, and it cannot be said that the resolution is sufficient, and it is difficult to increase the interpolation accuracy. There is a problem.

  Further, when the fixed sampling clock is set to 12 MHz, the resolution is Cfix (n) = 132 MHz / 12 MHz = 11 counts. In other words, even if a high-speed A / D converter is used, the interpolation accuracy is deteriorated, so that there is a problem that the accuracy of the final measurement result is lowered.

  Further, when generating a sampling clock N times the fundamental frequency as in Patent Document 2, the timing for performing the FFT operation is output as a signal pulse counted by the reference clock. Therefore, the time resolution of the output clock is only one clock of the reference clock. For example, if the reference clock is 132 MHz, the time resolution is 1/132 MHz = 7.576 ns. In this case, it is difficult to say that the interpolation resolution is sufficient.

  Therefore, the present invention aims to reduce the harmonic components that are not originally included in the input waveform when the FFT operation is performed, and to obtain a measurement result with high accuracy, particularly when the maximum frequency included in the input waveform approaches the sampling frequency. It aims to improve the accuracy.

In order to solve the above problems, a representative configuration of a harmonic component measuring apparatus according to the present invention includes an A / D converter that converts an analog input signal into digital data based on a sampling clock, and a zero cross of the analog input signal. A zero-cross detector that detects the basic frequency of the analog input signal based on the detection signal of the zero-cross detector, an interpolation timing generator that generates an interpolation timing of an integral multiple of the frequency, and a value at the interpolation timing of the digital data and interpolator determined by spline interpolation, and FFT computing the interpolated values of the digital data and an FFT processor for calculating a fundamental wave component and harmonic wave components of the analog input signal, interpolating the timing generator, the zero-crossing A pulse counter that counts the signal interval with the reference clock and the frequency of the reference clock A coefficient deriving unit for deriving a coefficient obtained by dividing the frequency by the sampling clock, a first subtractor that repeatedly subtracts the coefficient at the timing of the sampling clock from the number of clocks counted by the pulse counter, and the output of the first subtractor from the coefficient An interpolation timing determination unit that outputs an interpolation timing flag when the value is smaller, and a second subtracter that outputs an interpolation coefficient by subtracting the output of the first subtracter from the coefficient when the interpolation timing flag is output. An interpolation timing is configured by a flag and an interpolation coefficient, and the interpolation calculator performs spline interpolation using digital data of sampling clocks of 4 points or more and 8 points or less centering on the interpolation timing.

According to the above configuration, it is possible to perform interpolation with higher accuracy by obtaining the value of digital data at the interpolation timing (timing of input data of FFT operation) by spline interpolation. Accordingly, it is possible to reduce the harmonic components that are not originally included in the input waveform when the FFT operation is performed, and to obtain a measurement result with high accuracy, even when the maximum frequency included in the input waveform approaches the sampling frequency. Accuracy can be improved.
Further, according to the above configuration, the interpolation timing is output as a difference from the sampling clock. This difference is expressed numerically as the number of clocks based on the reference clock, and includes even decimal numbers. Therefore, the resolution of the interpolation timing can be remarkably increased and the interpolation accuracy can be improved as compared with the conventional case where the interpolation timing is output as a signal pulse that matches the reference clock.

In addition, the interpolation calculator can perform interpolation calculation for each timing of input data of FFT calculation by performing spline interpolation using digital data of sampling clock of 4 points or more and 8 points or less centering on the interpolation timing. Therefore, the FFT operation can be started as soon as the last point is interpolated.

  According to the present invention, it is possible to accurately obtain a measurement result by reducing harmonic components that are not originally included in the input waveform when FFT calculation is performed. In particular, the accuracy when the maximum frequency included in the input waveform approaches the sampling frequency can be improved.

It is a block diagram which shows an example of the harmonic component measuring apparatus concerning this embodiment. It is a block diagram which shows the internal structure of 2nd FPGA. It is a block diagram explaining the internal structure of an interpolation timing generator. It is a block diagram explaining the internal structure of an interpolation processor. It is a block diagram explaining the internal structure of an interpolation calculator. It is a timing chart which shows each output example inside an interpolation timing generator. It is a figure explaining the interpolation method. It is the figure which plotted the input waveform, the sampling point, and the interpolation data. It is a figure which shows the example of the result of having carried out FFT calculation using interpolation data. It is a block diagram explaining the structure of the harmonic component measuring apparatus disclosed by patent document 1. FIG. It is a figure explaining the linear interpolation disclosed by patent document 1. FIG. It is a figure explaining a subject. It is a figure explaining the cause of a subject.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The dimensions, materials, and other specific numerical values shown in the embodiments are merely examples for facilitating understanding of the invention, and do not limit the present invention unless otherwise specified. In the present specification and drawings, elements having substantially the same function and configuration are denoted by the same reference numerals, and redundant description is omitted, and elements not directly related to the present invention are not illustrated. To do.

  FIG. 1 is a block diagram showing an example of a harmonic component measuring apparatus according to the present embodiment, and the same reference numerals are given to portions common to FIG. 10 and description thereof is omitted. 1, the voltage input circuit 1, the A / D converter 2, the zero cross detector 3, the current input circuit 4, the A / D converter 5, the zero cross detector 6, the switch 9, the CPU 10, the display 11, and the fixed sampling clock. The functions and operations of the generator 12 and the operation unit 14 are the same as those shown in FIG. Further, the first FPGA 8 calculates the effective voltage value, the effective current value, and the active power from the total average of the instantaneous values in the same manner as the DSP 7 in FIG.

  In addition, when the harmonic component measuring apparatus of FIG. 1 and FIG. 10 is compared, 2nd FPGA15 is added. On the other hand, the DSP 17, the PLL sampling clock generator 13, the latch A18, the counter A19, the latch B20, the counter B21, the counter clock generator 22, and the flag circuit 23 are eliminated. The second FPGA 15 provides an alternative function.

  FIG. 2 is a block diagram showing an internal configuration of the second FPGA 15. The second FPGA 15 includes an interpolation timing generator 40, an interpolation processor 41, a memory 42, and an FFT calculator 43.

  The interpolation timing generator 40 receives a zero cross signal from the switch 9 and a fixed sampling clock from the fixed sampling clock generator 12. The interpolation timing generator 40 includes an interpolation timing flag indicating whether or not an interpolation timing is included between a certain fixed sampling clock and the next fixed sampling clock, and an α value that is a difference from the fixed sampling clock to the interpolation timing. (Interpolation coefficient) is output to the interpolation processor 41.

  FIG. 3 is a block diagram illustrating the internal configuration of the interpolation timing generator 40. In FIG. 3, the rising edge detector 24 generates one pulse by detecting the rising edge of the input zero-cross signal, and outputs the pulse to the pulse counter 25.

  In addition to the zero-cross signal input from the switch 9, the pulse counter 25 is also input with a reference clock composed of a pulse train at regular intervals from a reference clock generation source (not shown). The frequency of the reference clock is sufficiently higher than the frequency of the fixed sampling clock. The pulse counter 25 counts the time from the zero cross signal pulse to the next zero cross signal pulse and the number of pulses of the reference clock. After the count is completed, the count value is output to the memory 26.

  The memory 26 has an area where M outputs of the pulse counter 25 can be stored. Every time there is an output pulse of the rising edge detector 24, the count value output of the pulse counter 25 is stored in the memory 26. The count value output of the pulse counter 25 is stored in the memory area 1 of the memory 26 by the output pulse of the first rising edge detector 24, and the pulse is output to the memory area 2 of the memory 26 by the output pulse of the second rising edge detector 24. The count value output of the counter 25 is stored, and the count value output of the pulse counter 25 is stored in the memory area M of the memory 26 by the output pulse of the Mth rising edge detector 24.

  Then, the output pulse of the (M + 1) th rising edge detector 24 returns to the beginning of the memory 26 and the count value output of the pulse counter 25 is stored in the memory area 1, and the output of the (M + 2) th rising edge detector 24 is output. In the pulse, the count value output of the pulse counter 25 is stored in the memory area 2 of the memory 26.

  The first adder 27 adds all the count values of the pulse counter 25 stored in the memory areas 1 to M of the memory 26 and outputs the addition result to the first calculator 28 in binary.

The first computing unit 28 includes a divider, a multiplier, a shifter, and the like. In the case of a divider, a numerical value N is input as a constant 1, and a numerical value obtained by dividing the addition output of the first adder 27 by N is output. In the case of a multiplier, a numerical value obtained by calculating (1 / N) as a constant 1 is input, and a numerical value obtained by multiplying the addition output of the first adder 27 by (1 / N) is output. When N is a power of 2, a shifter can be used. In the case of a shifter, a numerical value obtained by calculating (log ₂ N) as a constant 1 is input, and a numerical value obtained by shifting the addition output of the first adder 27 to the right by (log ₂ N) bits is output.

The second computing unit 29 is also composed of a divider, a multiplier, a shifter, and the like. In the case of a divider, a numerical value M is input as the constant 2, and a numerical value obtained by dividing the output of the first arithmetic unit 28 by M is output. In the case of a multiplier, a numerical value obtained by calculating (1 / M) as a constant 2 is input, and a numerical value obtained by multiplying the output of the first arithmetic unit 28 by (1 / M) is output. When M is a power of 2, a shifter can be used. In the case of a shifter, a numerical value obtained by calculating (log ₂ M) as a constant 2 is input, and a numerical value obtained by shifting the output of the first computing unit 28 to the right by (log ₂ M) bits is output.

  The output value of the second calculator 29 and the output value of the first subtracter 36 are input to the second adder 34. The second adder 34 adds these and outputs them.

  The selector 35 receives the output of the second adder 34 and the output of the first subtractor 36, and outputs one of them depending on whether the output of the interpolation timing determiner 37 is 0 or 1. When the output of the interpolation timing determination unit 37 is 0, the output of the first subtractor 36 is output, and when the output is 1, the output of the second adder 34 is output.

  The first subtracter 36 receives the output of the selector 35, the fixed sampling clock, and the coefficient h output from the coefficient derivation unit 38. The first subtracter 36 outputs an output value β obtained by subtracting the coefficient h from the output of the selector 35 at a fixed sampling timing. The output value β is a numerical value including a decimal number.

  The interpolation timing determination unit 37 outputs 1 (interpolation timing flag) when the output value β of the first subtracter 36 is equal to or smaller than the coefficient h (β ≦ h), and when the output value β is larger than h (β> h). ) Outputs 0.

  The coefficient deriving unit 38 outputs a coefficient h obtained by dividing the frequency of the reference clock by the frequency of the fixed sampling clock. The coefficient h means how many clocks of the reference clock the fixed sampling clock interval is, and is a numerical value including a decimal.

  The second subtractor 39 outputs a value obtained by subtracting the output value β of the first subtractor 36 from the coefficient h at the timing when the interpolation timing flag (ie, 1) is output from the interpolation timing determination unit 37. Since the output value β is a numerical value including a decimal, the α value is the same.

  According to the above configuration, the pulse counter 25 counts how many reference clocks the zero-cross signal interval is, and causes the memory 26 to store the number of M zero-cross signal clocks. This is added by the first adder 27 and divided by M in the second calculator 29, whereby the average number of clocks can be taken. Further, by dividing by N in the first calculator 28, the second calculator 29 outputs a numerical value 1 / N of the count number of the zero cross signal.

  The first subtracter 36 subtracts the coefficient h (the number of clocks of the fixed sampling clock) from the clock number of the zero-cross signal. As long as the output value β is larger than the coefficient h (β> h in the interpolation timing determination unit 37). Since the output value β is selected in the selector 35, subtraction is repeatedly performed. When the output value β decreases by a factor h at the timing of the fixed sampling clock, and finally β ≦ h, the coefficient h−output value β = α value is output from the second subtractor 39. Therefore, the α value is a numerical value equal to or less than the coefficient h, and means a difference from the latest fixed sampling clock to the interpolation timing. The remaining β is added to the output value of the second computing unit 29 in the second adder 34, and the subtraction is repeated again.

  FIG. 6 is a timing chart showing an example of each output in the interpolation timing generator 40. As an example, reference clock frequency = 132 MHz, fixed sampling clock frequency = 2 MHz, zero cross signal frequency = 1.02 kHz, M = 2, and N = 512.

  FIG. 4 is a block diagram illustrating the internal configuration of the interpolation processor 41. In this embodiment, spline interpolation is performed using digital data of sampling clocks of 6 points (front 3 points and rear 3 points) centering on the interpolation timing.

  In FIG. 4, the memory 44 holds the ADU data (voltage AD value) for each fixed sampling clock for the past six times from the latest one, and y0u, y1u, y2u, y3u, y4u, Output as y5u. The memory 45 holds the ADI data (AD value of current) for each fixed sampling clock for the past six times from the latest one, and outputs them as y0i, y1i, y2i, y3i, y4i, y5i in order from the oldest ADI data. To do.

  The shifter 46 is composed of a three-stage shifter, latches the interpolation timing flag in the first stage for each fixed sampling clock, and shifts it to the second and third stages for each fixed sampling clock. Output the data. Thus, after the interpolation timing flag is output from the interpolation timing generator 40, the interpolation timing flag is output when the third fixed sampling clock arrives.

  The shifter 47 is also composed of a three-stage shifter, and the α value from the interpolation timing generator 40 is latched in the first stage for each fixed sampling clock, and this is latched in the second and third stages for each fixed sampling clock. Shift and output the third-stage data as an α value.

  When the voltage data is input to the interpolation calculator 49, the switch 48 outputs y0 = y0u, y1 = y1u,..., Y5 = y5u. When data on the current side is input to the interpolation calculator 49, y0 = y0i, y1 = y1i,..., Y5 = y5i are output.

  When the output of the shifter 46 is 1, the calculation of the interpolation calculator 49 is executed. The internal arithmetic expression will be described later. When the output of the switch 48 is voltage-side data, the AD value interpolated by the interpolation calculator 49 is output as yu. When the output of the switch 48 is current-side data, the AD value interpolated by the interpolation calculator 49 is output as yi. Switching of the switch 48 is performed in a time-sharing manner in the time between two consecutive fixed sampling clocks.

  The memory 42 shown in FIG. 2 stores the outputs yu and ii of the interpolation processor 41 by the number of FFT points. The FFT computing unit 43 performs an FFT computation when yu or ii is stored in the memory 42 for the number of FFT points. Then, the fundamental wave component and harmonic component of the voltage are obtained from the data obtained by interpolating the AD value of the voltage, the fundamental wave component and harmonic component of the current are obtained from the data obtained by interpolating the AD value of the current, the FFT result of the voltage and the FFT result of the current. The fundamental component and the harmonic component of the active power are calculated from the above and transferred to the CPU 10.

Next, an interpolation method will be described.
The AD value at the interpolation timing is interpolated from the AD value at the timing of the fixed sampling clock. When calculating with a quadratic derivative in general cubic spline interpolation, the following formula (1) is obtained (Reference: Mathematics of New Series “20 Spline Functions and Their Applications” Education Publishing) p.43 to 51. Note that S (x) in equation (3) on page 44 of the literature is replaced with y (x) here.

上記の変数は今回の提案では、次に該当する。
y(x)：補間後のAD値
x：補間タイミングの時刻
xj：補間タイミングの後の一番近い固定サンプリングクロックのタイミングの時刻
xj-1：補間タイミングの前の一番近い固定サンプリングクロックのタイミングの時刻
yj：時刻xjでのAD値
yj-1：時刻xj-1でのAD値
hj:xj-xj-1
非周期スプラインなので、行列Ｍ_ｊ、Ｍ_ｊ−１は、次の式（２）のようになる。

The above variables correspond to the following in this proposal.
y (x): AD value after interpolation
x: Time of interpolation timing
xj: Time of the nearest fixed sampling clock timing after the interpolation timing
xj-1: Time of closest fixed sampling clock timing before interpolation timing
yj: AD value at time xj
yj-1: AD value at time xj-1
hj: xj-xj-1
Since it is an aperiodic spline, the matrices M _j and M _j−1 are as shown in the following equation (2).

Interpolation data can be obtained by calculating using the above equation, but the calculation amount becomes enormous. For example, if the frequency of the zero cross is 1 kHz, the FFT window width is 1/1 kHz for 1 wave of 1 kHz = 1 ms, and the fixed sampling clock is 2 MHz, N in Expression (2) is 1 ms / (1/2 MHz) = 2000. Become. All the 2000 AD values are temporarily stored in the memory 42, and all the AD values are stored. Then, the 2000-ary linear simultaneous equations of Equation (2) are solved, and the matrix M _j (j = 1, 2,..., N−1). Then, y (x) is obtained by substituting it into the equation (1). Furthermore, if the number of FFT points is 512, 512 y (x) must be obtained.

  In another example, assuming that the frequency of zero crossing = 1 Hz, the FFT window width is 1/1 Hz = 1 s for one wave of 1 Hz, and the fixed sampling clock = 2 MHz, N = 1 s / (1/2 MHz) = 2,000. Therefore, a memory for storing AD values is also required for 2,000,000 data, and a 2,000,000 yuan linear simultaneous equation must be solved.

Therefore, in this embodiment, as described above, spline interpolation is performed using digital data of sampling clocks of 6 points (front 3 points and rear 3 points) centering on the interpolation timing. FIG. 7 is a diagram for explaining an interpolation method. As shown in FIG. 7, in order to obtain one interpolation data, a total of 6 points from a time close to the AD value of the fixed sampling before that, and 3 points from a time close to the AD value of the fixed sampling after that are obtained. Matrix _Mj , _Mj-1 is calculated _| required using only a point, and y (x) is calculated using the matrix _Mj , _Mj-1 . Then, when determining the different interpolation data, another matrix M _j, the M _j-1 determined using the AD value of the fixed sampling six points before and after the time, the matrix M _j, M _j-1 To calculate y (x).

A specific calculation method is as follows. First, although the time interval between sample points in the spline interpolation in the literature is not constant, the time interval between sample points is constant because sampling is performed with a fixed sampling clock here. Therefore, when time difference h _j = h _{j + 1} between fixed samplings is established and this is a coefficient h (the same as the coefficient h calculated by the coefficient deriving unit 38), the above expression (3) is expressed by the following expression (4). It becomes like this.

Furthermore, when the number of sample points is 6 in equation (2), the following equation (5) is obtained.

The end condition can be set as follows.

これらを式（５）に代入すると、次式のようになる。

In order for Expression (6) to be satisfied by Expression (5), it is as follows.

Substituting these into equation (5) yields:

When the calculation is performed by applying an inverse matrix to both sides, it is as follows.

Since the interpolation point is between j = 2 and j = 3, it is only necessary to obtain M ₂ and M ₃ .

式（１）にｊ＝３を代入すると、次のようになる。

When the numerical value of Formula (7) is represented by a symbol and M2 and M3 are represented by y0 to y5, the following Formula (8) is obtained.

Substituting j = 3 into equation (1) yields:

Here, if x ₃ −x = α, then xx ₂ = h−α, and if substituted, the following equation (9) is obtained.

  FIG. 5 is a block diagram illustrating the internal configuration of the interpolation calculator 49. As shown in FIG. 5, the interpolation calculator 49 is provided with a multiplier, an adder, and a subtracter for implementing the above equation (9). Although the unit of h and α is time, there is no problem even if the unit is not time as long as the ratio is the same in calculating equation (9). Here, the calculation is performed by replacing it with a count value (including the fractional part) counted with a clock having the same frequency (reference clock).

  In the above formula (8), A, B, C, D, E, F, G, H, I, J, K, L, P, Q, R, S, and T are constants, I can calculate it. Therefore, when the AD values y0, y1, y2, y3, y4, y5 and α of the fixed sampling clock are determined for each interpolation timing, the equation (9) can be calculated by the interpolation calculator 49. Interpolated data yu and ii can be obtained in substantially real time.

  FIG. 8 is a diagram in which an input waveform, sampling points, and interpolation data are plotted. Interpolated data is shown in the mouth. As shown in FIG. 8, the interpolation data follows the input waveform with high accuracy. Therefore, it can be seen that even when the ratio between the maximum frequency and the fixed sampling frequency included in the input waveform is close to, for example, 200 kHz: 2 MHz = 1: 10, it is in good agreement with the original waveform.

  FIG. 9 is a diagram illustrating an example of a result of FFT calculation using interpolation data. It can be seen that the harmonic component not included in the input waveform is smaller than that of the conventional technique (see FIG. 12B). It can be seen that the component that was -40 dB or more in the prior art becomes -70 dB or less (for example, around 250th order), which is improved by 30 dB or more.

  Further, as described above, if general cubic spline interpolation is used as it is, a large amount of memory for storing AD values is required. However, according to the configuration of this embodiment, only six in total before and after the interpolation point (per channel) ) Is enough. Further, even if the FFT window width is changed, the number of memories to be used does not change and is always only 6 (per channel). Further, it is not necessary to solve a multi-dimensional linear simultaneous equation, and interpolation calculation can be performed only with an adder, a subtracter, and a multiplier. Further, since the interpolation formula is modified so as to reduce the number of calculations by using only six points, there is an advantage that the number of calculators can be reduced.

  Further, in general cubic spline interpolation, since interpolation calculation is performed after all the sample points are aligned, it takes time to start the FFT calculation. However, according to the configuration of this embodiment, interpolation is performed at each interpolation timing. Since the calculation can be performed, the FFT calculation can be started as soon as the last point is interpolated.

  The interpolation calculation accuracy is determined by constants A, B, C, D, E, F, G, H, I, J, K, L, P, Q, R, S, T, and interpolation calculation. The accuracy of the calculator. Therefore, the accuracy can be easily improved by using a floating point format for constants and arithmetic units and increasing the number of mantissa digits.

  In particular, the resolution of the α value is important for interpolation, but instead of using a signal pulse that matches the interpolation timing with the reference clock as in the prior art, an α value expressed by a numerical value including decimals is used. Yes. Therefore, in the interpolation timing generator 40 of FIG. 3, the α value can be obtained as a numerical value with a resolution (N × M) times the reference clock, so that the resolution of the interpolation timing can be remarkably increased, and the interpolation accuracy is improved. Can be achieved. In order to achieve the same accuracy as that of the present invention with the linear interpolation of the prior art, an AD converter that is five times faster and more expensive is necessary. According to the present invention, such an increase in cost is avoided. Can do.

  Note that the proposed 6-point interpolation method is not only the voltage / current waveform interpolation as described in the present embodiment, but also the data at the time of sampling frequency conversion of the audio waveform and the enlargement / reduction of still images and moving images. It can also be applied to interpolation during re-sampling.

  If attention is paid only to the proposed interpolation timing generator 40, not only the above-described interpolation method but also the resolution in the time axis direction in the conventional linear interpolation can be increased to improve the interpolation accuracy.

  In this embodiment, six points before and after the interpolation point are used. However, the interpolation accuracy may be further increased by using eight points before and after the interpolation point. Conversely, it is possible to reduce the number of arithmetic units or shorten the arithmetic time by using four points in the front and rear. Note that the interpolation accuracy decreases when the number of points is four before and after, but the accuracy can be improved as compared with the case of linear interpolation. Further, even if the number of points is more than 8, no further improvement in accuracy is observed, and the calculation load increases rapidly, so that there is little profit. Therefore, the number of interpolation points is preferably 4 points or more and 8 points or less.

  As mentioned above, although preferred embodiment of this invention was described referring an accompanying drawing, it cannot be overemphasized that this invention is not limited to the example which concerns. It will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the claims, and these are naturally within the technical scope of the present invention. Understood.

  The present invention can be used as a harmonic component measuring apparatus, specifically, an apparatus that measures a voltage effective value, a current effective value, an active power, and the like by digital calculation and also measures a harmonic component of a voltage and a current.

DESCRIPTION OF SYMBOLS 1 ... Voltage input circuit, 2 ... A / D converter, 3 ... Zero cross detector, 4 ... Current input circuit, 5 ... A / D converter, 6 ... Zero cross detector, 7 ... DSP, 8 ... 1st FPGA, 9 ... Switcher, 10 ... CPU, 11 ... Display, 12 ... Fixed sampling clock generator, 13 ... PLL sampling clock generator, 14 ... Operating section, 15 ... Second FPGA, 17 ... DSP, 18 ... Latch A, 19 ... Counter A, 20 ... Latch B, 21 ... Counter B, 22 ... Counter clock generator, 23 ... Flag circuit, 24 ... Rising edge detector, 25 ... Pulse counter, 26 ... Memory, 27 ... First adder, 28 DESCRIPTION OF SYMBOLS 1st calculator, 29 ... 2nd calculator, 34 ... 2nd adder, 35 ... Selector, 36 ... 1st subtractor, 37 ... Interpolation timing determination device, 38 ... Coefficient derivation | leading-out part, 39 ... 2nd subtractor , 0 ... interpolator timing generator, 41 ... interpolation processor, 42 ... memory, 43 ... FFT computing unit, 44 and 45 ... memory, 46 and 47 ... Shifter, 48 ... switch, 49 ... interpolation calculator

Claims (1)

An A / D converter that converts an analog input signal into digital data based on a sampling clock;
A zero cross detector for detecting a zero cross of the analog input signal;
An interpolation timing generator for obtaining a basic frequency of the analog input signal based on a detection signal of the zero cross detector and generating an interpolation timing of an integer multiple of the fundamental frequency;
An interpolation calculator for obtaining a value at the interpolation timing of the digital data by spline interpolation;
An FFT calculator for calculating a fundamental wave component and a harmonic component of the analog input signal by performing an FFT operation on the interpolated value of the digital data ,
The interpolation timing generator is
A pulse counter that counts zero-cross signal intervals with a reference clock;
A coefficient derivation unit for deriving a coefficient obtained by dividing the frequency of the reference clock by the frequency of the sampling clock;
A first subtractor that repeatedly subtracts the coefficient from the number of clocks counted by the pulse counter at the timing of a sampling clock;
An interpolation timing determiner that outputs an interpolation timing flag when the output of the first subtracter becomes smaller than the coefficient;
A second subtractor that outputs an interpolation coefficient by subtracting the output of the first subtracter from the coefficient when the interpolation timing flag is output;
The interpolation timing is configured by the interpolation timing flag and the interpolation coefficient,
The harmonic component measuring apparatus, wherein the interpolation calculator performs spline interpolation using digital data of sampling clocks of 4 points or more and 8 points or less centering on interpolation timing.

Images