JP5784986B2 - Signal shift apparatus and method - Google Patents

Description

  The present invention relates to an apparatus and method for shifting (moving) a discrete signal obtained by sampling a continuous signal.

  FIG. 7 shows a configuration of a typical power measuring apparatus. In FIG. 7, a power measurement device 700 including a voltage A / D conversion unit 701, a current A / D conversion unit 702, a signal shift device 703, a product-sum operation unit 704, and a power amount display unit 705 is illustrated. It is shown.

  The voltage A / D conversion unit 701 receives an analog voltage signal Va, samples and quantizes the input analog voltage signal Va, and outputs a digital voltage signal Vd. The current A / D converter 702 receives the analog current signal Ia, samples and quantizes the input analog current signal Ia, and outputs a digital current signal Id. The signal shift device 703 inputs the digital current signal Id and the shift amount m in order to adjust the phase shift between the digital voltage signal Vd and the digital current signal Id, and the digital current signal Id is temporally shifted by the shift amount m. And a shifted digital current signal Id ′ is output. The product-sum operation unit 704 receives the digital voltage signal Vd and the shifted digital current signal Id ′, calculates the power value P by multiplying the digital voltage signal Vd and the shifted digital current signal Id ′, and calculates the power value P. Output the power value P. The power amount display unit 705 receives the power value P output from the product-sum operation unit 704 and displays the input power value P. The product-sum operation unit 704 calculates the power value P by performing a product-sum operation on the digital voltage signal Vd and the shifted digital current signal Id ′ according to the following (Equation 1).

  Here, Vd [i] and Id ′ [i] denote the i-th digital voltage signal Vd and the i-th shifted digital current signal Id ′, respectively. As described above, in a typical power measurement apparatus, in order to accurately measure the amount of power, it is necessary to reduce a phase shift between the digital voltage signal Vd and the digital current signal Id for each sampling.

  As a conventional signal shift device, there has been a device that shifts a discrete signal by an integral multiple of a sampling period using a shift register or the like. For example, Patent Document 1 describes a configuration in which a sampled current value is shifted by an integral multiple of a sampling period (1 time in FIG. 2 of Patent Document 1). Further, according to Patent Document 2, the shift amount is a discrete value, and a configuration is described in which the shift is performed by an integral multiple of the period sampled by the A / D modulator (in Patent Document 2, the resolution is indicated by an angle). However, this resolution is obtained by converting the sampling period of the A / D converter into an angle, and the shift amount is eventually an integer multiple of the sampling period). Non-Patent Document 1 describes a configuration in which a discrete signal is shifted by an integral multiple of a sampling period using discrete Fourier transform.

Japanese Patent No. 2813508 JP 2000-206161 A

E. Oran Bringham, Miyagawa Hiroshi, Imai Hideki, "Fast Fourier Transform", Science and Technology Publishers, p. 138, 1979.

  The conventional signal shift apparatus shifts a discrete signal by an integral multiple of the sampling period, and cannot perform a shift that is a real number multiple of the sampling period. Therefore, when the actual phase difference between the digital voltage signal Vd and the digital current signal Id is not an integral multiple of the sampling period, the phase difference cannot be corrected accurately. An object of the present invention is to solve the problem of such a conventional configuration, and to shift a discrete signal by a real number multiple of a sampling period.

In order to solve the above-described problem, a one-dimensional signal shift apparatus according to claim 1 of the present invention inputs a shift amount m which is a real number output from the outside, and calculates an integer part of the shift amount m. An integer decimal separator that calculates an integer a and a real number b of the decimal part of the shift amount m, an integer a output from the integer decimal separator, and an integer by adding 1 to the input integer a an integer adder that outputs a + 1, a real number b output from the integer fraction separator, and a subtractor that outputs a real number 1-b by subtracting the input real number b from 1; A discrete signal s [i] indicating the output i-th discrete signal and an integer a + 1 output from the integer adder are input, and the input discrete signal s [i] is calculated based on the input integer a + 1. Shift by a + 1 sample The first shift unit that generates and outputs the shifted discrete signal s _{a + 1} [i], the discrete signal s [i] output from the outside, and the integer a output from the integer fraction separator And the shifted discrete signal s _a [i] is generated and output by shifting the input discrete signal s [i] by a samples based on the input integer a. enter a shift unit, and said first of said pre-shifted output from shifter discrete signal s _{a + 1} [i] a real number b of the output integer fraction separating unit or, et al., the shifted discrete signal s Weighting is performed by multiplying the signal intensity s _{a + 1} [i] at the sample position i of _{a + 1} [i] by a coefficient Cf (b) formed of a monotonically increasing function generated based on the input real number b. a first coefficient multiplication unit for outputting a discrete signal _{Cf (b) s a + 1} [i], from the second shift section Type force has been shifted discrete signal s _a [i] and the real 1-b outputted from the fractional subtraction unit, the shifted discrete signal s _a [i] of the sample position i of the signal strength s _a [i ] Is multiplied by a coefficient Cf (1-b) composed of a monotonically increasing function generated based on the input real number 1-b, thereby outputting _a weighted discrete signal Cf (1-b) s _a [i]. The second coefficient multiplier, the weighted discrete signal Cf (b) s _{a + 1} [i] output from the first coefficient multiplier, and the weighted discrete signal Cf output from the second coefficient multiplier. (1-b) s _a [i] is input, and the input weighted discrete signal Cf (b) s _{a + 1} [i] and the input weighted discrete signal Cf (1-b) s _a [i]. ] and by adding to each the same sample position i the combined signal _{Cf (1-b) s a} [i] + Cf (b) s a + 1 Bei a combining unit for outputting a [i] And wherein the Rukoto.

A one-dimensional signal shift apparatus according to a second aspect of the present invention is the one-dimensional signal shift apparatus according to the first aspect, wherein the first shift unit is a + 1 for storing the value of the discrete signal s [i]. A first shift register including at least one buffer, and the second shift unit includes a second shift register including at least a buffer for storing a value of the discrete signal s [i], said first shift register, stores the value of the discrete signal the input from the left end of the buffer b _a, successively right at the timing when the discrete signal is inputted to the buffer b _a of the left buffer b _a-1, The values of the input discrete signals are stored in descending order as b _a-2 ,..., b ₀ , and the discrete signals stored in the leftmost buffer b _a are stored from the point of time when the discrete signals are stored for the input integer a + 1. Output the value of the signal so that the discrete signal is The discrete values stored in the right buffers b _a-1 , b _a-2 ,..., B ₀ are sequentially output at the timing of input to the leftmost buffer b _a , and the second shift register values of the discrete signal stores the left edge of the buffer b _a-1, the value of the input discrete signals is sequentially right timing to be inputted to the buffer b _a-1 of the left buffer b _a-2, b _a-3, ..., and stores the value of the discrete signals described above type in descending order to b _0, from the point of storing only discrete signal integers a number fraction that the input and stored in the buffer b _a-1 of the left The discrete signal value is output, and the discrete signals are sequentially stored in the right buffers b _a-2 , b _a-3 ,..., B ₀ at the timing when the discrete signals are input to the leftmost buffer b _a-1 . A value is output.

The one-dimensional signal shift device according to a third aspect of the present invention is the one-dimensional signal shift device according to the first aspect, wherein the first shift unit and the second shift unit are configured to output a discrete signal s [i]. A memory including _N buffers b ₀ , b ₁ ,..., B _N−2 , b _N−1 , which is the number of data, is provided, and each of the buffers is assigned an address 0 to an address N−1. , Each of the buffers b ₀ ,..., B _N−1 to which the addresses 0 to N−1 are attached stores the values of the discrete signals s [0],. The memory of the first shift unit uses the input integer a + 1, and the discrete signal value s [a stored in the buffers b _a ,..., B _N−1 from the address a to the address N−1. ],..., S [N−1] are read out and sequentially output, and the memory of the second shift unit stores the input integer. With the buffer b _a-1 from the address a to address N-1, ..., the value of b _N-1 to the stored discrete signal s [a-1], ... , reads the s [N-1] Or sequentially output the discrete signals s [a], s [a + 1], ..., s [N-1], s [using the input integer a + 1. 0], s [1],..., S [a-1], and outputs discrete signals. The memory of the second shift unit uses the input integer a to output discrete signals. s [a-1], s [a], ..., s [N-1], s [0], s [1], ..., s [a-2] are read out and output in this order. It is characterized by that.

The one-dimensional signal shift apparatus according to a fourth aspect of the present invention is the one-dimensional signal shift apparatus according to the first aspect, wherein the first shift section includes a first discrete Fourier transform section and a first shift amount. A conversion unit; a first frequency multiplication unit; and a first discrete Fourier inverse transform unit, wherein the second shift unit includes a second discrete Fourier transform unit, a second shift amount conversion unit, , A second frequency-by-frequency multiplication unit and a second discrete Fourier inverse transform unit, wherein the first discrete Fourier transform unit and the second discrete Fourier transform unit receive a discrete signal s [i]. The input discrete signal s [i] is subjected to discrete Fourier transform for each frequency information f to output a discrete Fourier transform signal S [f], and the first shift amount conversion unit is based on the input integer a + 1. Shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f The second shift amount conversion unit outputs a shift conversion amount exp (−j · 2πfa / N) for each frequency information f based on the input integer a, and for each first frequency. The multiplication unit includes a discrete Fourier transform signal S [f] output from the first discrete Fourier transform unit and a shift conversion amount exp (−j · 2πf (a + 1) /) output from the first shift amount conversion unit. N) is input and the input discrete Fourier transform signal S [f] is multiplied by the input shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f, thereby shifting Output a discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N), and the second frequency multiplication unit outputs the discrete Fourier transform output from the second discrete Fourier transform unit. Output from the signal S [f] and the second shift amount conversion unit. The shift conversion amount exp (−j · 2πfa / N) is input, and the input discrete Fourier transform signal S [f] and the input shift conversion amount exp (−j · 2πfa / N) are set for each frequency information f. To output a shifted discrete Fourier transform signal S [f] exp (−j · 2πfa / N), and the first discrete Fourier inverse transform unit outputs from the first frequency-by-frequency multiplication unit. The shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) is input for each frequency information f, and all the shifted discrete Fourier transform signals S [ f] exp (−j · 2πf (a + 1) / N) is subjected to inverse discrete Fourier transform to output _a shifted discrete signal s _{a + 1} [i], and the second discrete Fourier inverse transform unit includes Shifted discrete output from second frequency multiplication unit The Fourier transform signal S [f] exp (−j · 2πfa / N) is input for each frequency information f, and all the shifted discrete Fourier transform signals S [f] exp (−j · 2πfa /) input for each frequency information f. / N) is subjected to discrete Fourier inverse transform to output _a shifted discrete signal s _a [i].

The one-dimensional signal shift device according to claim 5 of the present invention is the one-dimensional signal shift device according to any one of claims 1 to 4, wherein the coefficient Cf (b) = b and the coefficient Cf (1- b) = 1-b .

In the method according to claim 6 of the present invention, the integer fraction separator inputs the shift amount m which is a real number output from the outside, and the integer a of the integer part of the shift amount m and the decimal of the shift amount m A step of calculating a real number b of the part; an integer adding unit that inputs the integer a output from the integer decimal separator; and adding 1 to the input integer a to output an integer a + 1; The decimal subtracting unit inputs the real number b output from the integer decimal separating unit and outputs the real number 1-b by subtracting the input real number b from 1, and the first shift unit includes an external The discrete signal s [i] indicating the i-th discrete signal output from the signal and the integer a + 1 output from the integer adder are input, and the input discrete signal s [i] based on the input integer a + 1 Shift by a + 1 samples Thus, the step of generating and outputting the shifted discrete signal s _{a + 1} [i] and the second shift unit output from the discrete signal s [i] output from the outside and the integer fraction separating unit The input integer a is input, and the input discrete signal s [i] is shifted by a samples based on the input integer a to generate and output _a shifted discrete signal s _a [i]. And the first coefficient multiplier inputs the shifted discrete signal s _{a + 1} [i] output from the first shift unit and the real number b output from the integer fraction separator. , A coefficient Cf (b) composed of a monotonically increasing function generated based on the input real number b to the signal intensity s _{a + 1} [i] at the sample position i of the shifted discrete signal s _{a + 1} [i]. by multiplying and outputting the weighted discrete signal _{Cf (b) s a + 1} [i], Coefficient multipliers of 2, the second pre-shifted output from shifter discrete signal s _a [i] and enter a real 1-b outputted from the fractional subtraction unit, the shifted discrete signal s _a By multiplying the signal intensity s _a [i] at the sample position i of [i] by a coefficient Cf (1-b) formed of a monotonically increasing function generated based on the input real number 1-b, weighting discrete A step of outputting _a signal Cf (1-b) s _a [i]; and a combining unit that outputs the weighted discrete signal Cf (b) s _{a + 1} [i] output from the first coefficient multiplication unit and the first The weighted discrete signal Cf (1-b) s _a [i] output from the coefficient multiplying unit 2 is input, and the input weighted discrete signal Cf (b) s _{a + 1} [i] is input. By adding the weighted discrete signal Cf (1-b) s _a [i] for each same sample position i, the combined signal Cf (1-b) s _a [ i] + Cf (b) s _{a + 1} [i].

The method according to claim 7 of the present invention is the method according to claim 6 , wherein the first shift unit includes a + 1 or more buffers for storing the value of the discrete signal s [i]. And the second shift unit includes a second shift register including a or more buffers for storing the value of the discrete signal s [i], and the shifted discrete signal s _{a + 1} [i] step of outputting, the first shift register, stores the value of the discrete signal the input from the left end of the buffer b _a, the timing of the discrete signal is inputted to the buffer b _a of the left sequential buffer b _a-1 on the right, b _a-2, in ..., from the time of storing the values of the discrete signal the type in descending order to b _0, storing the discrete signal by an integral a + 1 pieces of that said input, leaving the values of the discrete signal stored in the buffer b _a of the left To, comprising the step of discrete signal outputs said leftmost buffer b _a buffer sequentially right timing to be inputted to the b _a-1, b _a-2, ..., discrete values stored in b _0, In the step of outputting the shifted discrete signal s _a [i], the second shift register stores the value of the inputted discrete signal from the leftmost buffer b _a-1 and the value of the inputted discrete signal. Are sequentially input to the right-side buffers b _a-2 , b _a-3 ,..., B ₀ in descending order at the timing when is input to the left end buffer b _a-1 , From the time when discrete signals are stored for the input integer a, the value of the discrete signal stored in the leftmost buffer b _a-1 is output, and the discrete signal is input to the leftmost buffer b _a-1 . that sequential right buffer at a timing _{b a-2, b a-} 3, ..., stored in b ₀ away Characterized in that it comprises a step of outputting a value.

The method according to an eighth aspect of the present invention is the method according to the sixth aspect , wherein the first shift unit is the first shift unit and the second shift unit is a discrete signal s [i]. A memory including _N buffers b ₀ , b ₁ ,..., B _N−2 , b _N−1 , which is the number of data, is provided, and each of the buffers is assigned an address 0 to an address N−1. , Each of the buffers b ₀ ,..., B _N−1 to which the addresses 0 to N−1 are attached stores the values of the discrete signals s [0],. In the step of outputting the shifted discrete signal s _{a + 1} [i], the memory of the first shift unit uses the input integer a + 1 to buffer b _a from address a to address N−1. ,..., B _N-1 stored in discrete signal values s [a],..., S [N−1] and sequentially output And the step of outputting the shifted discrete signal s _a [i] is performed by the memory of the second shift unit using the input integer a to buffer b from address a to address N−1. _a-1, ..., b values of _N-1 to the stored discrete signal s [a-1], ... , s [N-1] or read comprising the step of sequentially outputting, or the shifted discrete signals In the step of outputting s _{a + 1} [i], the memory of the first shift unit uses the input integer a + 1 to input discrete signals s [a], s [a + 1],. -1], s [0], s [1],..., S [a-1], and outputs the discrete signals s _a [i]. In the step, the memory of the second shift unit uses the input integer a to input discrete signals s [a−1], s [a],. -1], s [0], s [1], ..., characterized in that it comprises a step of reading and outputting a discrete signal in order to be s [a-2].

According to a ninth aspect of the present invention, in the method according to the sixth aspect , the first shift unit includes a first discrete Fourier transform unit, a first shift amount conversion unit, and a first frequency. And a second discrete Fourier transform unit, a second shift amount conversion unit, and a second frequency-by-frequency multiplication unit. And a second discrete Fourier inverse transform unit, and the step of outputting the shifted discrete signal s _{a + 1} [i] inputs the discrete signal s [i] to the first discrete Fourier transform unit The input discrete signal s [i] is subjected to discrete Fourier transform for each frequency information f, the discrete Fourier transform signal S [f] is output, and the first shift amount conversion unit inputs the input integer a + 1. On the basis of the shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f. And the first frequency multiplication unit, the discrete Fourier transform signal S [f] output from the first discrete Fourier transform unit, and the shift conversion amount output from the first shift amount conversion unit. exp (−j · 2πf (a + 1) / N) is inputted, and the inputted discrete Fourier transform signal S [f] and the inputted shift conversion amount exp (−j · 2πf (a + 1) / N) are frequency. A step of outputting a shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) by multiplication for each information f, and the first discrete Fourier inverse transform unit, The shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) output from one frequency multiplication unit is input for each frequency information f, and all of the input frequency information f are input. Shifted discrete Fourier transform signal S [f] exp ( -J · 2πf (a + 1) / N) by performing discrete Fourier inverse transform to output _a shifted discrete signal s _{a + 1} [i], and outputting the shifted discrete signal s _a [i] The second discrete Fourier transform unit inputs the discrete signal s [i], performs discrete Fourier transform on the input discrete signal s [i] for each frequency information f, and performs the discrete Fourier transform signal S [ f], and a step in which the second shift amount conversion unit outputs a shift conversion amount exp (−j · 2πfa / N) for each frequency information f based on the input integer a. The second frequency-by-frequency multiplying unit outputs the discrete Fourier transform signal S [f] output from the second discrete Fourier transform unit and the shift conversion amount exp (−j output from the second shift amount conversion unit.・ 2πfa / N) is input and the input discrete frame is input Multiplying the Rie transform signal S [f] and the input shift conversion amount exp (−j · 2πfa / N) for each frequency information f, the shifted discrete Fourier transform signal S [f] exp (−j · 2πfa / N), and the second discrete Fourier inverse transform unit outputs a shifted discrete Fourier transform signal S [f] exp (−j · 2πfa / N) is input for each frequency information f, and all shifted discrete Fourier transform signals S [f] exp (−j · 2πfa / N) input for each frequency information f are shifted by inverse discrete Fourier transform. Outputting _a discrete signal s _a [i].

The method according to claim 10 of the present invention is the method according to any one of claims 6 to 9 , wherein the first shift unit is the coefficient Cf (b) = b, and the coefficient Cf (1− b) = 1-b .

  By using the one-dimensional signal shift device according to the present invention, a signal obtained by shifting a discrete signal by the shift amount can be generated with high accuracy even if the shift amount is not an integral multiple of the sampling period. In the one-dimensional signal shift device according to the present invention, the higher the sampling frequency, the higher the accuracy of the predicted value of the signal shifted by the shift amount.

  By using the one-dimensional signal shift device according to the present invention as the signal shift device of the power measurement device shown in FIG. 7 and shifting by a real number multiple of the sampling cycle, the time of the sampling cycle as shown in Patent Document 1 It is possible to obtain a power measurement value with higher accuracy than the conventional configuration that shifts with accuracy.

It is a figure which shows the structure of the one-dimensional signal shift apparatus which concerns on Example 1 of this invention. It is an operation | movement flowchart of the one-dimensional signal shift apparatus which concerns on Example 1 of this invention. It is a figure which shows the structure of the shift part 301 of the one-dimensional signal shift apparatus which concerns on Example 2 of this invention. It is a figure which shows the structure 401 of the shift part of the one-dimensional signal shift apparatus which concerns on Example 3 of this invention. It is a figure which shows the structure 501 of the shift part of the one-dimensional signal shift apparatus which concerns on Example 4 of this invention. It is a graph with the horizontal axis as the shift amount and the vertical axis as the signal strength of the discrete signal. It is a figure which shows the structure of a typical electric power measurement apparatus.

Example 1
FIG. 1 shows the configuration of a one-dimensional signal shift apparatus according to Embodiment 1 of the present invention. In FIG. 1, the integer fraction separator 101, the integer adder 102, the decimal subtractor 103, the first shift unit 104, the first shift unit 105, the first coefficient multiplier 106, A one-dimensional signal shift apparatus 100 including a coefficient multiplying unit 107 of 2 and a combining unit 108 is shown. FIG. 2 is an operation flowchart of the one-dimensional signal shift device 100 according to the first embodiment of the present invention. Hereinafter, the one-dimensional signal shift device 100 according to the first embodiment of the present invention will be described with reference to FIGS. 1 and 2. The operation will be described.

As shown by s101 in FIG. 2, the integer fraction separator 101 receives a shift amount m that is a real number output from the outside, and uses the input shift amount m, the following (Equation 2) and (Equation 2). According to 3), the integer a of the integer part of the shift amount m and the real number b of the decimal part of the shift amount m are calculated and output.
a = floor (m) (Formula 2)
b = m−a (Formula 3)

  Here, in (Expression 2), if y = floor (x), floor (x) is a function that returns an integer y satisfying 0 ≦ xy <1. Therefore, in a = floor (m) in (Equation 2), an integer a satisfying 0 ≦ m−a <1 is calculated. Further, from (Expression 2) and (Expression 3), 0 ≦ b <1. Hereinafter, the shift amount m is a real number, a is the value of the integer part of the shift amount m, and b is the value of the decimal part of the shift amount m.

  As indicated by s102 in FIG. 2, the integer adder 102 receives the integer a output from the integer decimal separator 101, and outputs 1 by adding 1 to the input integer a. As indicated by s103 in FIG. 2, the decimal subtraction unit 103 receives the real number b output from the integer decimal separation unit 101, and subtracts the input real number b from 1 to output a real number 1-b.

Assuming that i is an integer and s [i] indicates the i-th discrete signal and also indicates its signal strength, the first shift unit 104 is output from the outside as indicated by s104 in FIG. The discrete signal s [i] and the integer a + 1 output from the integer adder 102 are input, and the input discrete signal s [i] is shifted by an integer a + 1 samples based on the input integer a + 1. The generated discrete signal s _{a + 1} [i] = s [i + (a + 1)] is generated and output. As indicated by s105 in FIG. 2, the second shift unit 105 inputs the discrete signal s [i] output from the outside and the integer a output from the integer fraction separator 101, and inputs the input discrete signal. The shifted discrete signal s _a [i] = s [i + a] is generated and output by shifting s [i] by an integer a samples based on the input integer a.

As indicated by s106 in FIG. 2, the first coefficient multiplier 106 outputs the shifted discrete signal s _{a + 1} [i] output from the first shift unit 104 and the integer fraction separator 101. The real number b is input, and the coefficient Cf (b generated based on the input real number b is added to the signal strength s _{a + 1} [i] at the sample position i of the input shifted discrete signal s _{a + 1} [i]. ) To generate and output a weighted discrete signal Cf (b) s _{a + 1} [i]. Here, Cf (p) is a function of p and is a monotonically increasing function. Cf (p) can be, for example, Cf (p) = p (that is, Cf (p) is a function that outputs the variable p as it is). As indicated by s 107 in FIG. 2, the second coefficient multiplication unit 107 outputs the shifted discrete signal s _a [i] output from the second shift unit 105 and the real number 1− output from the decimal subtraction unit 103. b is input, and the signal strength s _a [i] at the sample position i of the shifted discrete signal s _a [i] is multiplied by a coefficient Cf (1-b) generated based on the input real number 1-b. Thus, the weighted discrete signal Cf (1-b) s _a [i] is generated and output.

As indicated by s108 in FIG. 2, the synthesizer 108 outputs the weighted discrete signal Cf (b) s _{a + 1} [i] output from the first coefficient multiplier 106 and the second coefficient multiplier 107. The weighted discrete signal Cf (1-b) s _a [i] is input, the input weighted discrete signal Cf (b) s _{a + 1} [i] and the weighted discrete signal Cf (1-b) s _a By adding [i] to the same sample position i, a composite signal s ′ [i] = Cf (1−b) s _a [i] + Cf (b) s _{a + 1} [i] is generated. Output.

Thus synthesized signal s generated by '[i] = Cf (1 -b) s a [i] + Cf (b) s a + 1 [i] is, s _a [i according to the value of the real number b ] And s _{a + 1} [i] change in weight. For example, if the real number b is smaller than 0.5 (b <0.5), the true shift signal, it is considered to be close to s _{a + 1} [i] than _{s a [i], s a} [ It is considered that the synthesized signal becomes closer to the true shift signal when the weight of i] is increased. Since Cf (p) is a monotonically increasing function, the weight Cf (1-b) integrated with s _a [i] is larger than the weight Cf (b) integrated with s _{a + 1} [i]. Is considered to be weighted properly.

  By using such a synthesized signal s ′ [i] as a predicted value of the true shift signal, even if the shift amount m is not an integral multiple of the sampling period but a real number of the sampling period, the shift amount m that is a real number is used. It is possible to reflect not only the integer a in the integer part of the real number b but also the real number b in the decimal part of the shift amount m in the predicted value of the true shift signal. As a result, the true shift signal can be predicted more precisely, the error of the predicted value from the true shift signal can be further reduced, and a signal obtained by shifting the discrete signal by the shift amount can be accurately obtained. Can be generated. Furthermore, since the calculation is simple, it is possible to achieve effects such as that the calculation can be speeded up, the program scale can be reduced, and a low-cost one-dimensional signal shift device can be realized. In particular, if Cf (p) = p, a complicated calculation is not required to calculate Cf (p), and thus the above-described effect can be further achieved.

In addition, when the maximum frequency of the signal before sampling is smaller than the sampling frequency (for example, 1/1000 or less), the signal between samples is close to a straight line, and thus the synthesized signal Cf (1-b) s _a [i] The error from the true shift signal of + Cf (b) s _{a + 1} [i] is reduced. The reason for this will be described with reference to FIG. FIG. 6 is a graph in which the horizontal axis is the shift amount and the vertical axis is the signal strength of the discrete signal. When T is a sampling period, the original signal g (iT + t) of the discrete signal is shown in FIG. 6, and the signal intensity s _a [i] of the i + a-th and i + (a + 1) -th discrete signals is shown on the y-axis. And s _{a + 1} [i], the true value g (iT + m) of the original signal g (iT + t) when the shift amount is m, and the synthesized signal s ′ [i], which is the predicted value of the shift amount m, It is shown.

As shown in FIG. 6, the discrete signal s discrete signals [i] was shifted by a + 1 samples s _{a + 1} [i] and the discrete signal s discrete signals [i] was shifted by a samples s _a [i ] Is the value of the signal next to the discrete signal before the shift. For example, if i = 10 and m = 3.2, a = 3 and b = 0.2 from the above-described (Equation 2) and (Equation 3). At this time, discrete signals shifted by a and a + 1 are respectively The signals are adjacent to each other such as the 13th (= 10 + 3) th and 14th (= 10 + 3 + 1) th discrete signals before the shift.

In FIG. 6, the synthesized signal s ′ [i] = Cf (1−b) s _a [i] + Cfbs _{a + 1} [i] is expressed by the signal intensity s _a [i] and x The signal intensity s _{a + 1} [i] corresponding to the axis shift amount (a + 1) T is shown by a straight line “signal predicted from discrete signal” connected by a broken line. For example, as described above, if i = 10, m = 3.2, and Cf (p) = p, then a = 3 and b = 0.2, so the predicted value is 0.8 s ₁₃ [10] +0.2 s ₁₄ [10] Since the straight line indicated by the “signal predicted from the discrete signal” is different from the signal g (iT + m) before sampling, between the predicted value of the shift amount m and the true value obtained by shifting the original signal by m samples. It can be seen that a prediction error has occurred.

However, when the maximum frequency of the signal before sampling is smaller than the sampling frequency (for example, 1/1000 or less), the signal before sampling is linear between s _a [i] and s _{a + 1} [i]. Since the signal before sampling between s _a [i] and s _{a + 1} [i] becomes closer to the straight line “signal predicted from discrete signals”, the prediction error of the shift amount m Is likely to be small. That is, in the method of the present invention, the higher the sampling frequency, the higher the possibility that the error in the predicted value of the shift amount m will be smaller.

(Example 2)
The configuration of the one-dimensional signal shift device according to the second embodiment of the present invention will be described with reference to FIG. In the second embodiment, the configuration of the first shift unit 104 and the second shift unit 105 shown in FIG. 1 is changed to the configuration of the shift unit 301 shown in FIG. Therefore, operations other than the shift unit 301 of the one-dimensional signal shift device according to the second embodiment are the same as the operations of the one-dimensional signal shift device 100 according to the first embodiment.

  FIG. 3 shows a shift unit 301 having a shift register 302. The shift register 302 includes a number of buffers equal to or greater than the shift amount d that stores the value of the discrete signal s [i], and is configured to ensure a buffer amount equal to or greater than the shift amount d. Here, in the case of the shift register of the first shift unit 104, the shift amount d is an integer a + 1, and in the case of the shift register of the second shift unit 105, the shift amount d is an integer a.

The shift register 302 of the shift unit 301 inputs the discrete signal s [i] and the shift amount d, stores the value of the input discrete signal s [i] from the leftmost buffer b _d-1 of the shift register 302, each time you enter the next discrete signals, sequentially right buffer at the timing when the discrete signal is inputted to the buffer b _d-1 of the left, i.e. the buffer _{b d-2, b d-} 3, ..., to b ₀ Discrete signal values are stored so as to shift in descending order. From the time when the value of the discrete signal is stored in the buffer b ₀ , that is, when the value of d discrete signals is stored, the value of the discrete signal stored in the leftmost buffer b _d-1 is output, and the discrete signal is output at the left end. buffer b _d-2 at a timing that is input to the buffer b _d-1 of, b _d-3, ..., by sequentially outputting the value of the stored discrete signals b _0, already shifted shifted by d samples A discrete signal s _d [i] can be output.

(Example 3)
The configuration of the one-dimensional signal shift device according to the third embodiment of the present invention will be described with reference to FIG. In the third embodiment, the configuration of the first shift unit 104 and the second shift unit 105 shown in FIG. 1 is changed to the configuration of the shift unit 401 shown in FIG. Therefore, operations other than the shift unit 401 of the one-dimensional signal shift device according to the third embodiment are the same as the operations of the one-dimensional signal shift device 100 according to the first embodiment.

  The third embodiment is a method of reading the discrete signal s [i] in the order of the discrete signals s [d−1], s [d],..., S [N−1], or the discrete signal s [d−1]. ], S [d], ..., s [N-1], s [0], s [1], ..., s [d-2]. The

FIG. 4 shows a shift unit 401 having a memory 402. Buffer b _0, b ₁ of the memory 402 is N (N is the number of data of the discrete signal s [i]), ..., b d-1, ..., includes a _{b N-2, b N-} 1, each buffer b _0, ..., to the b _N-1, respectively, address N-1 from the address 0 is attached. The shift unit 401 includes a discrete signal s [i] and a shift amount d (in the case of the first shift unit 104, the shift amount d is an integer a + 1, and in the second shift unit 105, the shift amount d is an integer a. And the values of the discrete signals s [0], ..., s [N-1] are stored in the buffers b ₀ , ..., b _N-1 from address 0 to address N-1, respectively. The

FIG. 4A is a diagram for explaining a configuration for reading discrete signals s [i] in the order of discrete signals s [d−1], s [d],..., S [N−1]. . As shown in FIG. 4A, the shift unit 401 stores the received shift amount d in buffers b _d−1 ,..., B _N−1 from address d−1 to address N−1. The values s [d−1],..., S [N−1] of the obtained discrete signals are read out and sequentially output. As a result, the discrete signal s [i] can be read in the order of the discrete signals s [d-1], s [d],. A discrete signal s _d [i] can be output.

FIG. 4B shows discrete signals s [d-1], s [d], ..., s [N-1], s [0], s [1], ..., s [d-2]. It is a figure for demonstrating the structure which reads discrete signal s [i] in order. As shown in FIG. 4B, the shift unit 401 stores the received shift amount d in buffers b _d−1 ,..., B _N−1 from address d−1 to address N−1. Read out the discrete signal values, and then read out the discrete signal values stored in the buffers b ₀ ,..., B _d-2 from address 0 to address d-2, thereby obtaining the buffers b _d−1 ,. , B _N−1 , b ₀ ,..., B _d−2 are output in the order of the discrete signals stored in these buffers. Thereby, the discrete signals s [d-1], s [d],..., S [N-1], s [0], s [1],. It is possible to read out s [i] and output a shifted discrete signal s _d [i] shifted by d samples.

Example 4
The configuration of the one-dimensional signal shift device according to Embodiment 4 of the present invention will be described with reference to FIG. In the fourth embodiment, the configuration of the first shift unit 104 and the second shift unit 105 shown in FIG. 1 is changed to the configuration of the shift unit 501 shown in FIG. Therefore, operations other than the shift unit 501 of the one-dimensional signal shift device according to the fourth embodiment are the same as the operations of the one-dimensional signal shift device 100 according to the first embodiment.

  FIG. 5 shows a shift unit 501 including a discrete Fourier transform unit 502, a shift amount conversion unit 503, a frequency multiplication unit 504, and a discrete Fourier inverse transform unit 505.

  The discrete Fourier transform unit 502 inputs the discrete signal s [i], performs a discrete Fourier transform on the input discrete signal s [i] for each frequency information f according to the following (Equation 4), and produces a discrete Fourier transform signal S [ f] is output.

  Here, f is frequency information of the discrete signal, exp (x) is a function representing the Napier number e to the power x, j is an imaginary unit, and N is the number of values of the discrete signal.

  The shift amount conversion unit 503 inputs a shift amount d (in the case of the first shift unit 104, the shift amount d is an integer a + 1, and in the second shift unit 105, the shift amount d is an integer a). Then, the shift conversion amount exp (−j · 2πfd / N) is calculated and output for each frequency information f.

  The frequency multiplication unit 504 receives the discrete Fourier transform signal S [f] output from the discrete Fourier transform unit 502 and the shift conversion amount exp (−j · 2πfd / N) output from the shift amount conversion unit 503. Multiplying the input discrete Fourier transform signal S [f] and the shift conversion amount exp (−j · 2πfd / N) for each frequency information f, the shifted discrete Fourier transform signal S [f] exp (−j Calculate 2πfd / N) and output.

The discrete Fourier inverse transform unit 505 inputs the shifted discrete Fourier transform signal S [f] exp (−j · 2πfd / N) output from the frequency multiplication unit 504 for each frequency information f, and for each frequency information f. All shifted discrete Fourier transform signals S [f] exp (−j · 2πfd / N) are subjected to discrete Fourier inverse transform according to the following (Formula 5), thereby outputting shifted discrete signals s _d [i] To do.

In this way, a shifted discrete signal s _d [i] shifted by d samples can be output.

DESCRIPTION OF SYMBOLS 100 One-dimensional signal shift apparatus 101 Integer fraction separation part 102 Integer addition part 103 Decimal subtraction part 104 1st shift part 105 2nd shift part 106 1st coefficient multiplication part 107 2nd coefficient multiplication part 108 Synthesis | combination part 301, 401, 501 Shift unit 302 Shift register 402 Memory 502 Discrete Fourier transform unit 503 Shift amount conversion unit 504 Discrete Fourier inverse transform unit 700 Power measurement device 701 Voltage A / D conversion unit 702 Current A / D conversion unit 703 Shift device 704 Sum of products Calculation unit 705 Electric energy display unit

Claims (10)

An integer fraction separator that inputs a shift amount m, which is a real number output from the outside, and calculates an integer a of the integer portion of the shift amount m and a real number b of the fractional portion of the shift amount m;
An integer adder that inputs the integer a output from the integer decimal separator and outputs an integer a + 1 by adding 1 to the input integer a;
A decimal number subtracting unit that inputs a real number b output from the integer decimal separator and outputs a real number 1-b by subtracting the input real number b from 1.
A discrete signal s [i] indicating the i-th discrete signal output from the outside and an integer a + 1 output from the integer adder are input, and the input discrete signal s [i] based on the input integer a + 1 ] Is shifted by a + 1 samples to generate and output _a shifted discrete signal s _{a + 1} [i];
The discrete signal s [i] output from the outside and the integer a output from the integer decimal separator are input, and the input discrete signal s [i] is divided into a samples based on the input integer a. A second shift unit that generates and outputs _a shifted discrete signal s _a [i] by shifting only by:
The shifted discrete signal s _{a + 1} [i] output from the first shift unit and the real number b output from the integer decimal separator are input, and the shifted discrete signal s _{a + 1} [i the signal strength of the sample position i s _{a + 1} [i] in], by multiplying the coefficient Cf (b) consisting of monotonically increasing function that is generated based on the real number b was the input, weighted discrete signal Cf (b ) _{a first} coefficient multiplier that outputs s _{a + 1} [i];
The shifted discrete signal s _a [i] output from the second shift unit and the real number 1-b output from the decimal subtraction unit are input, and the sample position i of the shifted discrete signal s _a [i] is input. signal strength s _a [i], and by multiplying the coefficient Cf (1-b) comprising a monotonically increasing function that is generated based on the real 1-b that the input, the weighted discrete signal Cf (1-b) _a second coefficient multiplier for outputting s _a [i];
The weighted discrete signal Cf (b) s _{a + 1} [i] output from the first coefficient multiplier and the weighted discrete signal Cf (1-b) s _a [i] output from the second coefficient multiplier. And the inputted weighted discrete signal Cf (b) s _{a + 1} [i] and the inputted weighted discrete signal Cf (1-b) s _a [i] for each same sample position i. A one-dimensional signal shift device comprising: a combining unit that outputs a combined signal Cf (1-b) s _a [i] + Cf (b) s _{a + 1} [i] by addition. The first shift unit includes a first shift register including a + 1 or more buffers for storing values of the discrete signal s [i], and the second shift unit includes the discrete signal s [i]. A second shift register comprising a or more buffers for storing the values of
Said first shift register, stores the value of the discrete signal the input from the left end of the buffer b _a, successively right at the timing when the discrete signal is inputted to the buffer b _a of the left buffer b _a-1, The values of the input discrete signals are stored in descending order as b _a-2 ,..., b ₀ , and the discrete signals stored in the leftmost buffer b _a are stored from the point of time when the discrete signals are stored for the input integer a + 1. The signal value is output, and discrete values stored in the right buffers b _a-1 , b _a-2 ,..., B ₀ are sequentially output at the timing when the discrete signal is input to the leftmost buffer b _a . And
In the second shift register stores the value of the discrete signal the input from the left end of the buffer b _a-1, the timing at which the value of the discrete signals the input is input to the buffer b _a-1 of the left The values of the input discrete signals are sequentially stored in descending order into the right buffers b _a-2 , b _a-3 ,..., B ₀ , and the discrete signals are stored for the input integer number a. and it outputs the value of the discrete signal stored in the buffer b _a-1 leftmost buffer b sequential right at the timing when the discrete signal is inputted to the buffer b _a-1 of the leftmost _a-2, b _a-3 The one-dimensional signal shift device according to claim 1, wherein the discrete value stored in b ₀ is output. The first shift unit and the second shift unit include N buffers b ₀ , b ₁ ,..., B _N−2 , b _N−1 which are the number of data of the discrete signal s [i]. Each of the buffers is assigned an address 0 to an address _N-1 , and each of the buffers b ₀ ,..., B _N-1 assigned an address 0 to an address N-1 is respectively , S [0], ..., s [N-1] values are stored,
The memory of the first shift unit uses the input integer a + 1, and the discrete signal value s [a stored in the buffers b _a ,..., B _N−1 from the address a to the address N−1. ],..., S [N−1] are read out and sequentially output, and the memory of the second shift unit uses the input integer a to buffer b _a− from address a to address N−1. ₁ ,..., B _N-1 stored in discrete signal values s [a−1],..., S [N−1] and sequentially output, or the memory of the first shift unit is , Using the input integer a + 1, the discrete signals s [a], s [a + 1],..., S [N−1], s [0], s [1],. Discrete signals are read out and output in this order, and the memory of the second shift unit uses the input integer a to output discrete signals s [a−1], s [a],. 1], s [0], s [1], ..., s [a-2] become the order by reading and outputting a discrete signal one-dimensional signal shifting device as claimed in claim 1, wherein the. The first shift unit includes a first discrete Fourier transform unit, a first shift amount conversion unit, a first frequency multiplication unit, and a first discrete Fourier inverse transform unit, The shift unit includes a second discrete Fourier transform unit, a second shift amount conversion unit, a second frequency-by-frequency multiplication unit, and a second discrete Fourier inverse transform unit.
The first discrete Fourier transform unit and the second discrete Fourier transform unit receive a discrete signal s [i], perform discrete Fourier transform on the input discrete signal s [i] for each frequency information f, and Outputs a Fourier transform signal S [f],
The first shift amount conversion unit outputs a shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f based on the input integer a + 1,
The second shift amount conversion unit outputs a shift conversion amount exp (−j · 2πfa / N) for each frequency information f based on the input integer a.
The first frequency multiplication unit includes a discrete Fourier transform signal S [f] output from the first discrete Fourier transform unit and a shift conversion amount exp (−j output from the first shift amount conversion unit. 2πf (a + 1) / N) is input, and the input discrete Fourier transform signal S [f] and the input shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f By multiplying, a shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) is output,
The second frequency-by-frequency multiplication unit includes a discrete Fourier transform signal S [f] output from the second discrete Fourier transform unit and a shift conversion amount exp (−j output from the second shift amount conversion unit. (2πfa / N) is input and the input discrete Fourier transform signal S [f] is multiplied by the input shift conversion amount exp (−j · 2πfa / N) for each frequency information f, thereby shifting. Output a discrete Fourier transform signal S [f] exp (−j · 2πfa / N),
The first discrete Fourier inverse transform unit outputs the shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) output from the first frequency-by-frequency multiplication unit for each frequency information f. Fill in, by inverse discrete Fourier transform of already all shifts inputted discrete Fourier transform signal S [f] exp (-j · 2πf (a + 1) / N) for each frequency information f, shifted discrete signal s _{a +1} [i] is output,
The second discrete Fourier inverse transform unit inputs the shifted discrete Fourier transform signal S [f] exp (−j · 2πfa / N) output from the second frequency multiplication unit for each frequency information f. Then, the discrete discrete Fourier transform signal S [f] exp (−j · 2πfa / N) inputted for each frequency information f is inversely transformed to output the shifted discrete signal s _a [i]. The one-dimensional signal shift device according to claim 1.   5. The one-dimensional signal shift device according to claim 1, wherein the coefficient Cf (b) = b and the coefficient Cf (1-b) = 1-b. An integer fraction separator that inputs a shift amount m that is a real number output from the outside, and calculates an integer a of the integer part of the shift amount m and a real number b of the decimal part of the shift amount m;
An integer adder that inputs the integer a output from the integer decimal separator and outputs an integer a + 1 by adding 1 to the input integer a;
A decimal subtracting unit that inputs the real number b output from the integer decimal separator and outputs the real number 1-b by subtracting the input real number b from 1;
The first shift unit inputs the discrete signal s [i] indicating the i-th discrete signal output from the outside and the integer a + 1 output from the integer adder, and based on the input integer a + 1, Generating and outputting _a shifted discrete signal s _{a + 1} [i] by shifting the input discrete signal s [i] by a + 1 samples;
The second shift unit inputs the discrete signal s [i] output from the outside and the integer a output from the integer fraction separator, and the input discrete signal s based on the input integer a generating and outputting _a shifted discrete signal s _a [i] by shifting [i] by a samples;
A first coefficient multiplier inputs the shifted discrete signal s _{a + 1} [i] output from the first shift unit and the real number b output from the integer fraction separator, and the shifted Multiplying the signal strength s _{a + 1} [i] of the discrete signal s _{a + 1} [i] at the sample position i by a coefficient Cf (b) made up of a monotonically increasing function generated based on the input real number b. To output a weighted discrete signal Cf (b) s _{a + 1} [i],
A second coefficient multiplication unit inputs the shifted discrete signal s _a [i] output from the second shift unit and the real number 1-b output from the decimal subtraction unit, and the shifted discrete signal s Weighting is performed by multiplying the signal intensity s _a [i] of the sample position i of _a [i] by a coefficient Cf (1-b) formed of a monotonically increasing function generated based on the input real number 1-b. Outputting a discrete signal Cf (1-b) s _a [i];
The combining unit outputs the weighted discrete signal Cf (b) s _{a + 1} [i] output from the first coefficient multiplier and the weighted discrete signal Cf (1-b) output from the second coefficient multiplier. s _a [i] is input, and the input weighted discrete signal Cf (b) s _{a + 1} [i] and the input weighted discrete signal Cf (1-b) s _a [i] are the same sample. Outputting the combined signal Cf (1-b) s _a [i] + Cf (b) s _{a + 1} [i] by adding each position i. The first shift unit includes a first shift register including a + 1 or more buffers for storing values of the discrete signal s [i], and the second shift unit includes the discrete signal s [i]. A second shift register comprising a or more buffers for storing the values of
The step of outputting the shifted discrete signal s _{a + 1} [i] includes:
Said first shift register, stores the value of the discrete signal the input from the left end of the buffer b _a, successively right at the timing when the discrete signal is inputted to the buffer b _a of the left buffer b _a-1, The values of the input discrete signals are stored in descending order as b _a-2 ,..., b ₀ , and the discrete signals stored in the leftmost buffer b _a are stored from the point of time when the discrete signals are stored for the input integer a + 1. The signal value is output, and discrete values stored in the right buffers b _a-1 , b _a-2 ,..., B ₀ are sequentially output at the timing when the discrete signal is input to the leftmost buffer b _a . Including the steps of
The step of outputting the shifted discrete signal s _a [i] includes:
In the timing the second shift register, stores the value of the discrete signal the input from the left end of the buffer b _a-1, the value of the discrete signals the input is input to the buffer b _a-1 of the left The values of the input discrete signals are sequentially stored in descending order into the right buffers b _a-2 , b _a-3 ,..., B ₀ , and the discrete signals are stored for the input integer number a. and it outputs the value of the discrete signal stored in the buffer b _a-1 leftmost buffer b sequential right at the timing when the discrete signal is inputted to the buffer b _a-1 of the leftmost _a-2, b _a-3 , ..., a method according to claim 6, characterized in that it comprises a step of outputting a discrete value stored in b _0. The first shift unit and the second shift unit include N buffers b ₀ , b ₁ ,..., B _N−2 , b _N−1 which are the number of data of the discrete signal s [i]. Each of the buffers is assigned an address 0 to an address _N-1 , and each of the buffers b ₀ ,..., B _N-1 assigned an address 0 to an address N-1 is respectively , S [0], ..., s [N-1] values are stored,
In the step of outputting the shifted discrete signal s _{a + 1} [i], the memory of the first shift unit uses the input integer a + 1 to buffer b _a from address a to address N−1. ,..., B _N-1 including the steps of reading and sequentially outputting the discrete signal values s [a],..., S [N−1] stored in the output, and outputting the shifted discrete signal s _a [i]. In the step of performing, the memory of the second shift unit uses the input integer a to store discrete data stored in buffers b _a−1 ,..., B _N−1 from address a to address N−1. Read out signal values s [a−1],..., S [N−1] and sequentially output them, or output the shifted discrete signals s _{a + 1} [i] The memory of the shift unit of 1 uses the input integer a + 1 to generate discrete signals s [a], s [a 1],..., S [N-1], s [0], s [1],..., S [a-1]. In the step of outputting s _a [i], the memory of the second shift unit uses the input integer a to output discrete signals s [a−1], s [a],. -1], s [0], s [1], ..., s [ a method according to claim 6, characterized in that it comprises a step of reading and outputting a discrete signal at a-2] become order. The first shift unit includes a first discrete Fourier transform unit, a first shift amount conversion unit, a first frequency multiplication unit, and a first discrete Fourier inverse transform unit, The shift unit includes a second discrete Fourier transform unit, a second shift amount conversion unit, a second frequency-by-frequency multiplication unit, and a second discrete Fourier inverse transform unit.
The step of outputting the shifted discrete signal s _{a + 1} [i] includes:
The first discrete Fourier transform unit inputs a discrete signal s [i], performs a discrete Fourier transform on the input discrete signal s [i] for each frequency information f, and outputs a discrete Fourier transform signal S [f]. Steps,
The first shift amount conversion unit outputs a shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f based on the input integer a + 1;
The first frequency multiplication unit includes a discrete Fourier transform signal S [f] output from the first discrete Fourier transform unit and a shift conversion amount exp (−j output from the first shift amount conversion unit. 2πf (a + 1) / N) is input, and the input discrete Fourier transform signal S [f] and the input shift conversion amount exp (−j · 2πf (a + 1) / N) for each frequency information f Outputting a shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) by multiplication;
The first discrete Fourier inverse transform unit converts the shifted discrete Fourier transform signal S [f] exp (−j · 2πf (a + 1) / N) output from the first frequency multiplication unit for each frequency information f. Fill in, by inverse discrete Fourier transform of already all shifts inputted discrete Fourier transform signal S [f] exp (-j · 2πf (a + 1) / N) for each frequency information f, shifted discrete signal s _{a Outputting +1} [i],
The step of outputting the shifted discrete signal s _a [i] includes:
The second discrete Fourier transform unit inputs a discrete signal s [i], performs a discrete Fourier transform on the input discrete signal s [i] for each frequency information f, and outputs a discrete Fourier transform signal S [f]. And steps to
The second shift amount conversion unit outputting a shift conversion amount exp (−j · 2πfa / N) for each frequency information f based on the input integer a;
The second frequency-by-frequency multiplying unit outputs the discrete Fourier transform signal S [f] output from the second discrete Fourier transform unit and the shift conversion amount exp (−j output from the second shift amount conversion unit. (2πfa / N) is input and the input discrete Fourier transform signal S [f] is multiplied by the input shift conversion amount exp (−j · 2πfa / N) for each frequency information f, thereby shifting. Outputting a completed discrete Fourier transform signal S [f] exp (−j · 2πfa / N);
The second discrete Fourier inverse transform unit inputs the shifted discrete Fourier transform signal S [f] exp (−j · 2πfa / N) output from the second frequency-by-frequency multiplication unit for each frequency information f. Then, the discrete discrete Fourier transform signal S [f] exp (−j · 2πfa / N) inputted for each frequency information f is inversely transformed to output the shifted discrete signal s _a [i]. The method of claim 6 comprising the steps of: Wherein a coefficient Cf (b) = b, A method according to any one of claims 6 9, characterized in that the coefficients Cf (1-b) = 1 -b.

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