JP6142790B2 - AD converter - Google Patents

Description

  The present invention relates to an AD converter that converts an analog input value into a digital value.

  As the above-described AD converter, one that periodically inputs a plurality of reference voltages and corrects input / output characteristics indicating the relationship between an analog input value and a digital value is known (for example, see Patent Document 1). .

JP 2004-274157 A

However, the AD converter has a problem in that AD conversion of an analog input value cannot be performed while performing the above correction.
Accordingly, in view of such problems, an AD converter that converts an analog input value into a digital value can perform AD conversion of the analog input value even while the input / output characteristics are being corrected. It is an object of the present invention.

  In the AD converter according to the present invention, one or more first AD converters input an analog input value, output an output value obtained by converting the analog input value into a digital value, and one or more second AD converters have a reference voltage. To output a reference value obtained by converting the reference voltage into a digital value. Then, the output correction means corrects the input / output characteristics that are characteristics when the first AD converter converts the analog input value into the digital value according to the reference value.

  According to such an AD conversion apparatus, since the first AD converter that AD converts the analog input value and the second AD converter that AD converts the reference voltage, input / output correction is performed by the second AD converter. Even when the input / output characteristics of the first AD converter are being corrected, AD conversion of the analog input value can be performed.

  In addition, description of each claim can be arbitrarily combined as much as possible. At this time, a part of the configuration may be excluded within a range in which the object of the invention can be achieved.

It is a block diagram showing a schematic structure of AD converter 1 of a 1st embodiment. It is a timing chart at the time of performing AD conversion in AD converter 1 of a 1st embodiment. It is a block diagram which shows schematic structure of AD conversion apparatus 2 of 2nd Embodiment. It is a timing chart at the time of performing AD conversion in AD converter 2 of a 2nd embodiment. It is a graph which shows input / output characteristic correction | amendment of TAD26,27. It is a block diagram which shows schematic structure of AD converter 3 of 3rd Embodiment. It is a timing chart at the time of performing AD conversion in AD converter 3 of a 3rd embodiment. It is a block diagram which shows schematic structure of AD converter 4 of 4th Embodiment. It is a timing chart at the time of performing AD conversion in AD converter 4 of a 4th embodiment.

Embodiments according to the present invention will be described below with reference to the drawings.
[First Embodiment]
FIG. 1 is a block diagram illustrating a schematic configuration of an AD conversion apparatus according to the present embodiment. As shown in FIG. 1, the AD conversion apparatus 1 according to the present embodiment includes a plurality (two in the present embodiment) of AD converters (TAD) 26 and 27, a reference voltage input unit 10, a switching logic 23, and a correction. Part 8.

  The AD converter 1 linearly corrects and outputs digital data (nonlinear characteristics) as an AD conversion result for the analog signal Vin input to the TAD [A] 26. In the present embodiment, the analog signal Vin is input to the TAD [A] 26, and a reference voltage described later is input to the TAD [B] 27.

  The TADs 26 and 27 include a pulse delay circuit that has a plurality of delay units and circulates the start pulse SP as disclosed in, for example, FIG. 20 of JP-A-2004-274157. The TADs 26 and 27 are set so that the number of delay units through which the start pulse passes is changed according to the input voltage, and the digital value corresponding to the input voltage is output by counting this number. It is configured to

  Here, the clock generation unit 21 in the correction unit 8 generates a sampling clock (clock pulse) CLK having a predetermined cycle (sampling cycle), and inputs it to the TADs 26 and 27. Further, a start pulse SP (pulse signal) is input to the TADs 26 and 27 from an external control circuit (CPU or the like) (not shown), and the operations of the TADs 26 and 27 are started by this start pulse.

  The reference voltage input unit 10 is for sequentially inputting a reference voltage for obtaining data necessary for setting the linear correction formula in the correction formula setting unit 41 to the TAD [B] 27. Then, as the reference voltages, the minimum voltage Vmin from the minimum voltage generation unit 11, the center voltage Vc from the center voltage generation unit 12, and the maximum voltage Vmax from the maximum voltage generation unit 13 are respectively represented by three-state analog switches 14, 15 and 16 through TAD [B] 27.

  In the TADs 26 and 27 of the present embodiment, the specification (scale) of the input voltage range is set to the minimum voltage Vmin to the maximum voltage Vmax, and the input voltage within this range is converted into digital data and output. The center voltage Vc is an intermediate value between the minimum voltage Vmin and the maximum voltage Vmax. These three voltages are sequentially input to the TAD [B] 27 to perform AD conversion, and based on the AD conversion result, a linear correction formula is set as will be described later.

  In addition, each voltage production | generation part 11,12,13 is realizable by all the structures which can each produce | generate desired voltages (Vmin, Vc, Vmax). For example, each voltage can be obtained by configuring a voltage dividing circuit that divides a certain voltage value with a plurality of resistors. In the following description, digital data for the minimum voltage Vmin, center voltage Vc, and maximum voltage Vmax is also referred to as a “reference value”, and digital data for an actual AD conversion target voltage is also referred to as an “output value”.

  The switching logic 23 outputs a signal for enabling any one of the three-state analog switches 14, 15, 16 in accordance with an instruction from the reference voltage selection unit 22 in the correction unit 8. In this embodiment, by sequentially enabling any one of the three-state analog switches 14, 15, 16 corresponding to the minimum voltage Vmin, the center voltage Vc, and the maximum voltage Vmax, these voltages are sequentially set to TAD [B]. The corresponding reference value is obtained. Thereafter, the correction formula setting unit 41 sets a straight-line correction formula.

  The correction unit 8 is used to set a linear correction formula and to linearly correct an output value using the linear correction formula. In the present embodiment, the correction unit 8 is configured by one FPGA (Field Programmable Gate Array). The correction unit 8 includes a clock generation unit 21, a register 30, a correction logic unit 40, and a reference voltage selection unit 22.

  The clock generator 21 generates and outputs a sampling clock CLK. The register 30 temporarily stores the reference value. The correction logic unit 40 sets a straight line correction formula based on the stored contents of the register 30 and linearly corrects the output value using the straight line correction formula.

  Hereinafter, the operation of the AD conversion apparatus 1 will be described with reference to FIG. First, in the boot period shown in FIG. 2, non-linearity correction is performed using the TAD [B] 27 on the reference voltage side. At this time, the operation of the TAD [A] 26 on the AD conversion target voltage (Vin) side is stopped.

  In the boot period, the reference voltage selection unit 22 outputs an instruction (signal) for enabling only one of the three-state analog switches 14, 15, 16 to the switching logic 23 in accordance with the sampling clock CLK. For example, the reference voltage selection unit 22 first outputs a command to enable only the three-state analog switch 8 corresponding to the minimum voltage Vmin, and the reference value MIN for this Vmin is input to the minimum data storage unit 32 in the register 30. If it is confirmed that the data has been stored, a command for enabling only the three-state analog switch 9 corresponding to the center voltage Vc is output.

  When it is confirmed that the reference value C for the center voltage Vc is stored in the center data storage unit 33 in the register 30, a command for enabling only the three-state analog switch 10 corresponding to the maximum voltage Vmax is output. . That is, the reference voltage selection unit 22 outputs a command for sequentially switching the three-state analog switches 14, 15, 16, whereby the reference value for each voltage Vmin, Vc, Vmax is set to the minimum data storage unit 32 and the central data storage unit 33, respectively. , Stored in the maximum data storage unit 34.

  Here, the correction logic unit 40 includes a correction formula setting unit 41 in which a linear correction formula is set, and a correction calculation unit 42 that performs conversion (correction calculation) of an output value in accordance with the linear correction formula. The correction formula setting unit 41 sets a linear correction formula based on MIN, C, and MAX stored in each of the storage units 32 to 34 in the register 30. For the setting of the straight line correction equation, for example, a method disclosed in Japanese Patent Application Laid-Open No. 2004-274157 (described in FIG. 2 and the like and descriptions in paragraphs [0088] to [0100]) may be used.

When the straight line correction formula is set by the correction formula setting unit 41, the correction calculation unit 42 is in a state in which the output value from the TAD [A] 26 can be straight-line corrected and output in accordance with the straight line correction formula.
When such a boot period ends, AD conversion by TAD [A] 26 is started. The output value DT [A] for the input voltage (Vin) is temporarily stored in the signal output unit 31 in the register 30, and the stored output value is linearly corrected by the correction calculation unit 42. The straight line correction by the correction calculation unit 42 is performed according to the straight line correction formula set by the correction formula setting unit 41, and the output value DT [A] is corrected to the correction value DTc.

  Here, since the information on the sampling clock CLK and the current temperature is directly reflected in these three reference values (MIN, C, MAX), the above-described linear correction corresponds to the sampling clock CLK and the current temperature at that time. It is an appropriate correction.

  In the present embodiment, by adopting a configuration in which this reference value is periodically fetched, a linear correction formula that immediately responds to fluctuations in the sampling clock CLK and the ambient temperature is set, and appropriate linear correction is performed. As a specific example of the periodic capturing, for example, a method of capturing in a cycle shorter than the expected temperature fluctuation in consideration of the temperature change situation predicted in advance in the environment where the TAD [A] 26 is installed can be considered.

  When the reference value is fetched periodically, an output value by TAD [A] 26 is generated, and the same operation as the boot period is performed on the TAD [B] 27 side. That is, the “construction of correction calculation unit” shown in FIG. 2 is periodically performed.

  The output value from TAD [A] 26 is corrected with a new linear correction formula as soon as the linear correction formula in the correction formula setting unit 41 is changed. In the present embodiment, TAD [B] 27 is in a dormant state during the period in which “construction of the correction calculation unit” is not performed in the Vin signal reference period shown in FIG.

[Effects of this embodiment]
In the AD converter 1 described in detail above, one or a plurality of TAD [A] 26 that inputs an analog input value (AD conversion target voltage) and outputs an output value obtained by converting the analog input value into a digital value. One or more TAD [B] 27 that inputs a reference voltage and outputs a reference value obtained by converting the reference voltage into a digital value, and TAD [A] 26 converts an analog input value into a digital value according to the reference value. And a correction logic unit 40 that corrects input / output characteristics, which are characteristics at the time of processing.

  According to such an AD conversion apparatus 1, the TAD [A] 26 for AD-converting the analog input value and the TAD [B] 27 for AD-converting the reference voltage are provided. Even when the input / output characteristics of the TAD [A] 26 are being corrected during output correction, AD conversion of analog input values can be performed.

In the AD converter 1, each TAD 26 and 27 is configured as a time AD converter provided with a pulse delay circuit.
According to such an AD converter 1, in the time AD converter provided with the pulse delay circuit, it is necessary to correct the input / output characteristics during the AD conversion of the analog input value in order to correct the temperature characteristics. At this time, the input / output characteristics can be corrected without interrupting the AD conversion of the analog input value.

  Furthermore, in the AD converter 1, the TAD [B] 27 receives a plurality of reference voltages and outputs a reference value corresponding to each reference voltage. The correction logic unit 40 is based on the plurality of reference values. An approximate curve is generated, and the output value is corrected to match the approximate curve.

According to such an AD conversion apparatus 1, it is possible to correct non-linearity even when the input / output characteristic has non-linearity.
[Second Embodiment]
Next, another type of AD conversion apparatus 2 will be described. In the present embodiment (second embodiment), only portions different from the AD converter 1 of the first embodiment will be described in detail, and the same portions as those of the AD converter 1 of the first embodiment are denoted by the same reference numerals. Therefore, the description is omitted.

  As shown in FIG. 3, the AD conversion apparatus 2 according to the present embodiment includes a switching unit 51 and an input / output characteristic correction unit 52 in addition to the configuration of the AD conversion apparatus 1. The switching unit 51 is configured as a switch for switching whether to input an AD conversion target voltage or a reference voltage to the TAD [A] 26. The switching unit 51 is controlled by the switching logic 23 in the same manner as the three-state analog switches 14, 15, and 16.

  The input / output characteristic correction unit 52 is arranged on the path between the TAD [B] 27 and the register 30 and is set so that the output from the TAD [A] 26 is also input. The input / output characteristic correction unit 52 has a function of correcting a characteristic difference between TAD [A] 26 and TAD [B] 27 in the boot period. That is, as shown in FIG. 4, in the configuration of the first embodiment, TAD [A] 26 that has not been used in the boot period can be used effectively.

  In the boot period, TAD [A] 26 inputs a reference voltage similar to the reference voltage input to TAD [B] 27 via switching unit 51. Then, the input / output characteristic correction unit 52 compares the outputs DT [A] and DT [B] from the TADs 26 and 27. For example, as shown in FIG. 5, reference values for a plurality of reference voltages are simultaneously input from the TADs 26 and 27 to the input / output characteristic correction unit 52.

  Then, the input / output characteristic correction unit 52 sets a correction coefficient (a function corresponding to the digital value) for matching the output characteristic of the TAD [B] 27 with the output characteristic of the TAD [A] 26, and sets this correction coefficient. Based on this, as shown in FIG. 4, the reference value output from the TAD [B] 27 after the boot period (Vin signal reference period) is corrected.

  According to such an AD conversion device 2, reference values output from a plurality of AD converters can be compared with each other, so that a characteristic difference between the AD converters can be corrected. Note that the timing at which the reference voltage is input to the TAD [A] 26 is preferably limited to the timing at which it is not necessary to perform AD conversion of the analog input value as in this embodiment.

[Third Embodiment]
Next, another form of the AD conversion apparatus 3 will be described. As shown in FIG. 6, the AD conversion device 3 according to the present embodiment includes switching units 61 and 64, an addition unit 62, and multiplication units 63 and 65 in addition to the configuration of the AD conversion device 1.

  The switching units 61 and 64 are controlled by the switching logic 23 in the same manner as the three-state analog switches 14, 15 and 16. In particular, the switching unit 61 is configured as a switch that switches whether to input an AD conversion target voltage or a reference voltage to the TAD [B] 27. The switching unit 64 is configured as a switch that switches whether an input to the register 30 is an output from an adder 62 described later or an output from a multiplier 63 described later.

The adding unit 62 adds the outputs from the TADs 26 and 27 and sends them to the switching unit 64.
The multipliers 63 and 65 multiply the input value by a constant (in this embodiment, twice) and output the result. Multiplier 63 multiplies the output from TAD [A] 26 by a constant and outputs it to switching unit 64, and multiplier 65 multiplies the output from TAD [B] 27 by a constant and outputs it to register 30.

  In such AD converter 3, the switching logic 23, as shown in FIG. 7, is a time when the reference voltage does not need to be input to the correction logic unit 40 after the boot period ends (that is, the “correction calculation” shown in FIG. At the timing when the “part construction” is not performed), the AD conversion target voltage is also input to the TAD [B] 27, and the output values from the TADs 26 and 27 are added by the adder 62 and input to the register.

  According to such an AD conversion device 3, the analog input value is input to each AD converter (TAD [A] 26 and TAD [B] 27), and the output values are added, so that the accuracy can be improved. It is statistically known that when the ratio of the magnitudes of output values from the TADs 26 and 27 is 1: 1, the accuracy is doubled.

  Further, in the AD converter 3 described above, when a reference value is input to the TAD [B] 27, the outputs from the TADs 26 and 27 are multiplied by a constant by the multipliers 63 and 65, so that the adder 62 It is possible to match the output value added in step 1 and the data size (scale).

[Fourth Embodiment]
Next, another form of the AD converter 4 will be described. As shown in FIG. 8, the AD conversion apparatus 4 of the present embodiment is different from the configuration of the AD conversion apparatus 1 of the first embodiment in that the switching unit 51, the input / output characteristic correction unit 52, and the switching units 61 and 64 described above. , An adder 62 and multipliers 63 and 65 are provided.

  The input / output characteristic correction unit 52 is disposed between the TAD [B] 27 and the multiplication unit 65. In this configuration, as shown in FIG. 9, reference voltages are input to the TADs 26 and 27 in the boot period, and when the “correction operation unit construction” is not performed after the boot period ends, the ADs are input to the TADs 26 and 27. The switching units 51, 61, and 64 are operated so that the conversion target voltage is input.

  Then, when the “construction of the correction calculation unit” is performed after the boot period, the AD conversion target voltage is input to TAD [A] 26 and the reference voltage is input to TAD [B] 27. In other words, the TAD 26 and 27 are always used so that the hardware can be used efficiently.

[Other Embodiments]
The present invention is not construed as being limited by the above embodiment. Moreover, the aspect which abbreviate | omitted a part of structure of said embodiment as long as the subject could be solved is also embodiment of this invention. An aspect configured by appropriately combining the above-described plurality of embodiments is also an embodiment of the present invention. Moreover, all the aspects which can be considered in the limit which does not deviate from the essence of the invention specified only by the wording described in the claims are embodiments of the present invention. Further, the reference numerals used in the description of the above embodiments are also used in the claims as appropriate, but they are used for the purpose of facilitating the understanding of the invention according to each claim, and the invention according to each claim. It is not intended to limit the technical scope of

  For example, in the above embodiment, each unit is configured to operate in accordance with the sampling clock CLK, but may be configured to operate in response to a command from a control device having a CPU. In the above embodiment, two AD converters (TAD 26 and 27) are used, but three or more AD converters may be used.

Furthermore, in the above embodiment, TAD is adopted as the AD converter, but AD converters other than TAD may be adopted.
[Correspondence between Configuration of Embodiment and Means of Present Invention]
The TAD [A] 26 in the above embodiment corresponds to the first AD converter referred to in the present invention, and the TAD [B] 27 in the above embodiment corresponds to the second AD converter referred to in the present invention. The correction logic unit 40 in the above embodiment corresponds to the output correction unit in the present invention, and the switching logic 23 and the switching unit 51 in the above embodiment correspond to the reference voltage input control unit in the present invention.

  Further, the input / output characteristic correction unit 52 in the above embodiment corresponds to a reference correction unit in the present invention, and the switching logic 23 and the switching unit 61 in the above embodiment correspond to an input control unit in the present invention. Further, the adding unit 62 in the above embodiment corresponds to the adding means in the present invention, and the multiplying units 63 and 65 in the above embodiment correspond to the multiplying means in the present invention.

  DESCRIPTION OF SYMBOLS 1-4 ... AD converter, 8 ... Correction | amendment part, 10 ... Reference voltage input part, 11 ... Minimum voltage generation part, 12 ... Center voltage generation part, 13 ... Maximum voltage generation part, 14, 15, 16 ... 3-state analog Switch 19, signal output unit 21, clock generation unit 22, reference voltage selection unit 23, switching logic 26, TAD [A], 27 TAD [B], 30 register, 32 minimum data storage unit , 33 ... center data storage unit, 34 ... maximum data storage unit, 40 ... correction logic unit, 41 ... correction formula setting unit, 42 ... correction calculation unit, 51 ... switching unit, 52 ... input / output characteristic correction unit, 61 ... switching 62, an addition unit, 63, a multiplication unit, 64, a switching unit, and 65, a multiplication unit.

Claims (5)

An AD converter (1) for converting an analog input value into a digital value,
One or more first AD converters (26) for inputting the analog input value and outputting an output value obtained by converting the analog input value into a digital value;
One or more second AD converters (27) for inputting a reference voltage and outputting a reference value obtained by converting the reference voltage into a digital value;
According to the reference value, output correction means (40) for correcting input / output characteristics which are characteristics when the first AD converter converts the analog input value into a digital value;
Input control means (23, 23) for controlling a timing at which a reference voltage is input to the second AD converter and for inputting an analog input value input to the first AD converter when no reference voltage is input to the second AD converter. 61)
An adding means (62) for adding an output value output from each AD converter when an analog input value is input to the second AD converter;
An AD conversion apparatus comprising: The AD converter according to claim 1,
Each AD converter is comprised as a time AD converter provided with the pulse delay circuit. The AD converter characterized by the above-mentioned. In the AD conversion device according to claim 1 or 2,
The second AD converter receives a plurality of reference voltages, outputs a reference value corresponding to each reference voltage,
The output correction unit generates an approximate curve based on a plurality of reference values, and corrects the output value so as to match the approximate curve. In the AD conversion device according to any one of claims 1 to 3,
Reference voltage input control means (23, 51) for changing the reference voltage input to the second AD converter to the first AD converter instead of the analog input value;
Reference correction means (52) for correcting the input / output characteristics of another AD converter to the input / output characteristics of a certain AD converter among the AD converters by comparing the reference values output from each AD converter. )When,
An AD conversion apparatus comprising: In the AD conversion device according to any one of claims 1 to 4 ,
Multiplier means (63, 65) for multiplying the output from each AD converter means by a constant when a reference value is input to the second AD converter,
An AD conversion apparatus comprising: