JP5387465B2 - Digitally controlled DC / DC converter - Google Patents

Description

  The present invention relates to a DC / DC converter that performs voltage conversion by switching with a pulse width modulation signal (hereinafter referred to as a PWM (Pulse Width Modulation) signal), and more particularly, a low-voltage digital control DC / DC converter controlled by a digital signal. Regarding power consumption.

  FIG. 6 shows a configuration example of a conventional general digital control DC / DC converter. The digitally controlled DC / DC converter shown in FIG. 6 is an example of a voltage mode configuration in which the switching element is turned on / off by a PWM signal to convert the input voltage Vin into the output voltage Vout. Is referred to as an AD converter circuit.) 10, the digital compensation circuit 20, the PWM circuit 30, the oscillation circuit 40, and the high-frequency oscillation circuit 50, the drive circuits DP and DN, and the drive circuits DP and DN are turned on and off. An output circuit 2 including a pair of switching elements P-channel MOSFET (hereinafter referred to as PMOS) QP and N-channel MOSFET (hereinafter referred to as NMOS) QN to be controlled; a smoothing circuit 3 including an inductor L and a capacitor Co; It is composed of In addition, Vin is a power source for inputting the input voltage Vin to the DC / DC converter (the power source and its voltage are given the same reference numerals), and the load circuit 4 is a load circuit of the DC / DC converter.

  In the control circuit 1 shown in FIG. 6, the AD conversion circuit 10 converts an error voltage between the output voltage Vout fed back and the reference voltage Vref as a target value into a digital error signal e [n], and the digital compensation circuit 20 The duty command signal d [n] indicating the duty ratio of the PWM signal (the on-time ratio during the switching period) is calculated by digital calculation from the digital error signal e [n], and the PWM circuit 30 outputs the duty command signal d A PWM signal is generated based on [n]. Here, [n] indicates a signal in the nth switching period. The output circuit 2 turns on / off the switching elements PMOS • QH, NMOS • QN according to the PWM signal, smoothes the output of the output circuit 2 by the smoothing circuit 3, obtains the output voltage Vout, and drives the load circuit 4.

In FIG. 6, the AD conversion circuit 10 of the control circuit 1 is, for example, a delay line circuit type AD conversion circuit that performs AD conversion by controlling the delay time of the delay element. (See Patent Document 1)
FIG. 7 shows a configuration example of an AD conversion circuit using this delay line circuit system. The AD conversion circuit 10 shown in FIG. 7 includes two delay line circuits 5 and 6, an error output circuit 7, a start signal generation circuit 8, and an oscillation circuit 40.

  Generally, a delay line circuit is configured by connecting delay elements whose delay time is controlled by a control voltage in a required number of stages in series. A configuration example and a timing chart of this delay element are shown in FIG. The delay element shown in FIG. 8A is configured by connecting in series a pair of PMOS QP1 and NMOS QN1 to which the input signal in is connected to the gate, and NMOS QN2 to which the control voltage Vb is connected to the gate. The first inverter and the second inverter INV to which the output signal o1 of the first inverter is input, and the bias current Ib of the NMOS QN2 of the first inverter is controlled by the control voltage Vb. The desired delay time tdelay is generated by controlling. FIG. 8B shows a timing chart of the delay element shown in FIG. The delay element delays the rising edge of the input signal in by a desired delay time tdelay and generates an output signal out in which the falling edge is delayed by a normal switching delay time td.

  The two delay line circuits 5 and 6 shown in FIG. 7 are configuration examples with eight stages of delay elements. In the first delay line circuit 5, the delay times of all the delay elements a1 to a8 are controlled by the inputted reference voltage Vref, and the second delay line circuit 6 is made up of all the delay elements by the inputted output voltage Vout. The delay times b1 to b8 are controlled.

  FIG. 9 shows a timing chart of the AD converter circuit 10 of the delay line circuit system shown in FIG. The AD conversion circuit 10 performs an AD conversion operation every switching cycle of the DC / DC converter. The start signal generation circuit 8 generates a start signal start synchronized with the switching frequency generated by the oscillation circuit 40. The start signal start is input to the two delay line circuits 5 and 6, and sequentially propagates through the delay elements a1 to a8 and b1 to b8 while being delayed by the delay time of the delay elements. When the start signal start reaches the fourth delay element a4 of the first delay line circuit 5, a latch signal is output. By this latch signal, the outputs b1 to b8 of the respective delay elements of the second delay line circuit 6 (elements and their outputs have the same reference numerals) are taken into the error output circuit 7, and the fetched data b1 to b8 are taken. The digital error calculation signal e [n] is output after conversion. This digital error signal e [n] is a conversion value determined according to the error voltage between the reference voltage Vref and the output voltage Vout for controlling the delay time of the two delay line circuits 5 and 6.

  In the timing chart of FIG. 9, when the first delay line circuit 5 outputs a latch signal, if the reference voltage Vref and the output voltage Vout match, the start signal start of the second delay line circuit 6 is also the first. Similarly to the delay line circuit 1 of 1, the fourth delay element b4 is reached, and the digital error signal e [n] outputs “0”. Next, when the reference voltage Vref is lower than the output voltage Vout, the start signal start of the second delay line circuit 6 reaches only the first delay element b1, and the digital error signal e [n] is “−3”. Output. When the reference voltage Vref is higher than the output voltage Vout, the start signal start of the second delay line circuit 6 reaches the eighth delay element b8, and the digital error signal e [n] outputs “+3”. . In this way, the output signals b1 to b8 of the second delay line circuit 6 are stored as latch signals, converted into a digital value corresponding to the error voltage between the reference voltage Vref and the output voltage Vout, and then output. Conversion operation is performed.

  In FIG. 6, the digital compensation circuit 20 of the control circuit 1 is, for example, a circuit that performs digital PID (Proportional Integral and Differential) control as a digital arithmetic function. In other words, the duty command signal d [n] is controlled and calculated so that the digital error signal e [n] becomes “0”. The expression of the discretized digital PID control calculation is generally expressed as Expression (1).

  Here, d [n−1] is a duty command signal before one switching period, e [n−1] and e [n−2] are digital error signal outputs one switching period before and two switching periods, respectively, A , B and C are control coefficients.

  As shown in the above equation (1), the PID control calculation requires three multiplications and three additions, but providing three multiplication circuits and three addition circuits each leads to a significant increase in circuit area. Implements the PID control operation by executing three multiplication processes and three accumulation processes using one multiplication circuit and one accumulation circuit. However, this PID control calculation needs to indicate the duty command signal d [n] by completing the calculation process within one switching period. That is, in order to complete three multiplication processes and three accumulation processes within one switching cycle, the operation clock used for the operation process needs to have a frequency that is at least six times the switching frequency. This arithmetic clock is generated by the high frequency oscillation circuit 50.

  However, since the current consumption of the circuit is proportional to the frequency, there is a problem in that the current consumption of the DC / DC converter increases and the power conversion efficiency decreases in the circuit configuration incorporating the high-frequency oscillation circuit 50.

  As a digital control device that improves the increase in current consumption due to this high-frequency oscillation circuit, an AD converter circuit that performs an operation equivalent to a high oscillation pulse using a low oscillation pulse, and a circuit configuration of a power conversion device using this AD conversion circuit Is introduced in Patent Document 2.

  FIG. 10 shows a circuit configuration of the AD conversion circuit described in Patent Document 2. The AD conversion circuit shown in FIG. 10 includes a periodic signal generation circuit 60, a counter circuit 70, and a digital signal generation circuit 80.

  The periodic signal generation circuit 60 receives an analog signal Ain that changes over time, and replaces the analog signal Ain with N-series periodic signals P1 to PN having a frequency corresponding to the magnitude of the analog signal Ain. The counter circuit 70 includes N counters CNTR1 to CNTRN that count the number of pulses of the N series of periodic signals P1 to PN. The digital signal generation circuit 80 outputs a digital signal Dout corresponding to the magnitude of the analog signal Ain from the N series of periodic signals P1 to PN for each sample period.

  That is, by generating and counting a 1 / N period signal corresponding to the magnitude of the input signal, an AD converter circuit having a resolution N times the sample period is realized. By using this AD conversion circuit for a digitally controlled DC / DC converter, low power consumption can be realized.

US2006 / 0273831 A1 publication WO2008 / 041428 A1

The conventional digital control DC / DC converter described above has the following problems.
First, in the first circuit configuration example shown in FIG. 6, since it is necessary to use a high-speed operation clock for a digital compensation circuit that calculates a duty command signal from a digital error signal by digital control calculation, current consumption increases and power consumption increases. There is a problem that the conversion efficiency decreases. Further, when a high-speed arithmetic clock is not used, there is a problem that a circuit scale increases because a multiplication circuit and an accumulation circuit must be installed in parallel.

  In the second circuit configuration example shown in FIG. 10, a low-speed oscillation pulse is used in the AD converter circuit to achieve a resolution equivalent to that of a high-speed oscillation pulse, thereby reducing power consumption. There is no mention of low power consumption for digital control computation. That is, the problem described in the first circuit configuration example similarly occurs.

  The present invention has been made in view of the above-described problems, and a problem to be solved is a digitally controlled DC / DC converter that achieves low power consumption without increasing the circuit scale and has high power conversion efficiency. Is to provide.

  In order to solve the above-described problem, the invention according to claim 1 is a DC that performs on / off control of a switching element in accordance with a pulse width modulation signal whose duty ratio is obtained by digital calculation, and converts an input voltage into a desired output voltage. A first delay line circuit, which is a DC / DC converter, in which delay elements whose delay times are controlled by a reference voltage are connected in series, a start signal start is sequentially delayed to generate a plurality of output signals, and a delay time is output A delay element controlled by a voltage is connected in series, a second delay line circuit that sequentially delays the start signal start to generate a plurality of output signals, and a plurality of output signals of the first delay line circuit. Among the plurality of outputs of the second delay line circuit at the output timing of the signal output in the first (where l is a natural number). An AD conversion circuit having an error output circuit that takes in a signal and converts it into a digital error signal corresponding to an error voltage between the reference voltage and the output voltage; and k (k is a natural number) of the first delay line circuit And a digital compensation circuit that calculates the duty ratio by performing the digital calculation using the digital error signal in accordance with the timing at which the output signals after the first are sequentially output.

  According to a second aspect of the present invention, the first and second delay line circuits are configured by connecting a plurality of the same delay elements that generate a desired delay time based on an input control voltage, and The number of stages of serial connection of the delay elements of one delay line circuit is defined by the number of arithmetic processes of the digital compensation circuit, and the number of stages of serial connection of the delay elements of the second delay line circuit is converted by the AD converter circuit. It is characterized by accuracy.

  The invention according to claim 3 is characterized in that the digital compensation circuit has a function of PID calculation or PI calculation as the digital calculation, and completes the digital calculation by performing a plurality of calculation processes.

  The digital control DC / DC converter according to the present invention uses the output signals of a plurality of delay elements constituting the delay line circuit used in the AD conversion circuit as the control operation clock of the digital compensation circuit, thereby reducing the circuit scale without increasing the circuit scale. There is an effect of realizing power consumption.

It is a figure which shows the structural example of the digital control DC / DC converter which concerns on this invention. It is a figure which shows the structural example of the AD converter circuit which concerns on the Example of this invention. It is a figure which shows the timing chart of the AD converter circuit based on the Example of this invention. It is a figure which shows the structural example of the control circuit which concerns on the Example of this invention. It is a figure which shows the timing chart of the control circuit which concerns on the Example of this invention. It is a figure which shows the structural example of the conventional digital control DC / DC converter. It is a figure which shows the structural example of the AD converter circuit using the conventional delay line circuit. It is a figure which shows the circuit structural example (A) and timing chart (B) of the delay element used for the conventional delay line circuit. It is a figure which shows the timing chart of the AD converter circuit using the conventional delay line circuit. It is a figure which shows the structural example of an AD converter circuit as a conventional 2nd circuit structural example.

[Example 1]
Hereinafter, a digitally controlled DC / DC converter according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a digital control DC / DC of the present invention. The same parts as those in the configuration example of the conventional DC / DC converter shown in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The digitally controlled DC / DC converter shown in FIG. 1 is a voltage mode configuration example in which a switching element is controlled by a PWM signal to convert an input voltage Vin into an output voltage Vout. The AD converter circuit 11, the digital compensation circuit 21, , A control circuit 1 including a PWM circuit 30 and an oscillation circuit 40, a pair of switching elements PMOS and QP and NMOS and QN that are controlled to be turned on and off by the drive circuits DP and DN and the drive circuits DP and DN, Output circuit 2 and a smoothing circuit 3 made of inductor L and capacitor Co. In addition, Vin is a power source for inputting the input voltage Vin to the digital control DC / DC converter (the power source and its voltage have the same reference numerals), and the load circuit 4 is a load of the digital control DC / DC converter.

  In FIG. 1, an AD conversion circuit 11 is connected in series with delay elements A1 to Am (m is a natural number) whose delay time is controlled by a reference voltage Vref, and output signals A1 to Am obtained by sequentially delaying a start signal start according to the delay time. A delay line circuit 12 for generating (elements and their outputs are given the same reference numerals) and delay elements B1 to Bm whose delay time is controlled by the output voltage Vout are connected in series, and the start signal start is sequentially applied according to the delay time. The delay line circuit 13 that generates delayed output signals B1 to Bm (elements and their outputs are assigned the same sign), and the timing of the output signal Al output from the delay line circuit 12 to the lth (l is a natural number). The output signals B1 to Bm of the delay line circuit 13 are taken in, and the error voltage between the reference voltage Vref and the output voltage Vout It includes a corresponding digital miscalculation signal e error output circuit 14 which converts the [n] to output a. The start signal start is generated in synchronization with the rising edge of the switching frequency generated by the oscillation circuit 40, and the AD conversion operation is performed every switching cycle. Here, the delay element is configured such that the delay time is controlled by the input control voltage, similarly to the delay element shown in FIG.

  The digital compensation circuit 21 performs a digital operation using the digital error signal e [n] output from the AD conversion circuit 11 to calculate a duty command signal d [n] that indicates the duty ratio of the PWM signal. This digital calculation is completed by executing s (s is a natural number) times, and the calculation clocks clk1 to clks used for each calculation process are k (k) of the delay line circuit 12 of the AD conversion circuit 11. Is a natural number) and subsequent output signals A1 to Am (k = 1, m = s in the example of FIG. 1), and arithmetic processing is performed in accordance with the sequentially output timing.

  The PWM circuit 30 generates and outputs a PWM signal based on the duty command signal d [n]. The output circuit 2 performs on / off control of the switching elements PMOS • QH and NMOS • QN by the PWM signal. The smoothing circuit 3 smoothes the output of the output circuit 2 to generate an output voltage Vout, and supplies this to the load circuit 4.

  FIG. 2 is a circuit configuration example of the AD conversion circuit 11 and the digital compensation circuit 21 according to the present invention. The AD converter circuit 11 shown in FIG. 2 has a delay line circuit 12 in which delay elements A1 to A8 (m = 8) whose delay time is controlled by a reference voltage Vref are connected in series, and a delay time that is controlled by an output voltage Vout. The delay line circuit 13 to which the delay elements B1 to B8 are connected in series and the output signal B1 to B8 of the delay line circuit 13 are fetched at the timing of the output signal A4 (l = 4) of the delay line circuit 12, and the reference voltage Vref And an error output circuit 14 that converts and outputs a digital error calculation signal e [n] corresponding to an error voltage with respect to the output voltage Vout.

  The digital compensation circuit 21 shown in FIG. 2 performs a digital operation process six times (s = 6) using the digital error signal e [n] to indicate the duty ratio of the PWM signal. Is calculated. The arithmetic clocks clk1 to clk6 used for each arithmetic processing are connected to the third (k = 3) and subsequent output signals A3 to A8 of the delay line circuit 12, and the arithmetic processing is performed in accordance with the sequential output timing.

  FIG. 3 shows a timing chart of the delay line circuit 12 of the AD conversion circuit 11 shown in FIG. The start signal start synchronized with the switching cycle is propagated through the delay elements A1 to A8 while being sequentially delayed by the delay time tdelay controlled by the reference voltage Vref, and the output signal whose rise is delayed by the delay time tdelay during one switching cycle. A1 to A8 are generated. Then, by using the output signal whose rise is delayed by the delay time tdelay as the operation clock of the digital compensation circuit 21, the high frequency oscillation circuit used for the digital operation processing becomes unnecessary, and low power consumption can be realized.

  Here, when the resolution of the AD conversion circuit is ΔVadc, the output voltage Vout of the DC / DC converter is controlled to be the reference voltage Vref ± ΔVadc. Therefore, the number m of delay elements in the delay line circuit 12 is determined by the output accuracy required for the AD conversion circuit 11. For example, when a 4-bit output accuracy is required, the delay element configuration is at least m = 15 stages, and 15 output signals whose rising edges are equally spaced in one switching cycle can be generated. On the other hand, when the PID control calculation shown in the above equation (1) is performed as a digital calculation, it is sufficient if there are six operation clocks (s = 6) in one switching period, and 15 rising signals Therefore, it can be realized by extracting six (k = 10) signals at a necessary timing.

  On the other hand, when the digital calculation is complicated and the number of calculation processes exceeds 15, the number of calculation clocks is insufficient. In this case, the number m of delay elements of the delay line circuit 12 may be determined by the number s of digital processing operations. Although the circuit area and current consumption of the AD conversion circuit 11 increase, the circuit area and current consumption can be reduced as compared with the case where the control circuit 1 is provided with an oscillation circuit for an operation clock.

As described above, the present invention uses the fact that the delay line circuit 12 used in the AD converter circuit 11 is always constant because the delay time is controlled by the reference voltage Vref. By using the output signal as a calculation clock for digital calculation of the digital compensation circuit 21, a high-frequency oscillation circuit is unnecessary, and a reduction in circuit area and low power consumption can be realized. As a result, the conversion efficiency of the digitally controlled DC / DC converter can be improved.
[Example 2]
FIG. 4 shows a circuit configuration example of the AD conversion circuit 11 and the digital compensation circuit 21 according to the present invention as a second embodiment. The same parts as those in the first embodiment shown in FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the AD conversion circuit 11 shown in FIG. 4, delay elements A1 to A25 (m = 25) whose delay time is controlled by the reference voltage Vref are connected in series, and the output signals A1 to A25 are obtained by sequentially delaying the start signal start according to the delay time. A delay line circuit 12 for generating (elements and their outputs are given the same reference numerals) and delay elements B1 to B25 whose delay time is controlled by the output voltage Vout are connected in series, and the start signal start is sequentially applied according to the delay time. A delay line circuit 13 that generates delayed output signals B1 to B25 (elements and their outputs have the same reference numerals), and a delay line circuit 13 at the output timing of an output signal A17 (l = 17) of the delay line circuit 12 15-bit data of the output signals B18 to B25 of the reference voltage Vref and the output voltage Vout It includes the error output circuit 14 for converting a digital miscalculation signal e [n] of 4bit corresponding to the error voltage. The start signal start is generated in synchronization with the rising edge of the switching frequency generated by the oscillation circuit 40, and the AD conversion operation is performed every switching cycle.

  The digital compensation circuit 21 shown in FIG. 4 indicates the duty ratio of the PWM signal by performing the PID control calculation represented by the above equation (1) using the digital error signal e [n] output from the AD conversion circuit 11. The duty command signal d [n] to be calculated is calculated.

  The digital compensation circuit shown in FIG. 4 receives the digital error signal e [n], which is the output of the AD conversion circuit 11, and receives digital error signals e [n], e [n−1], e [for three switching periods. n−2], coefficient registers 24_1 to 24_3 for storing control coefficients A, B, and C used for the PID control calculation, and error registers according to the progress of the PID control calculation A multiplexer (hereinafter referred to as MUX) circuit 25 that selects and outputs a necessary digital error signal from 23_1 to 23_3, and a necessary control coefficient from the coefficient registers 24_1 to 24_3 according to the progress of the PID control calculation. A MUX circuit 26 that selects and outputs, and a multiplier circuit 2 that multiplies the digital error signal selected by the MUX circuit 25 and the control coefficient selected by the MUX circuit 26. And an accumulation circuit 28 for adding the multiplication results, an output register 29 for storing the calculation results and outputting them to the PWM circuit 30, and a selection signal sel_mux (2 bits) of the MUX circuits 25 and 26 from the calculation clock output from the delay line circuit 12. And a selection signal generation circuit 22 that generates a selection signal sel_acc (2-bit data) of the accumulation circuit.

  Here, the operation clock requires 8 types of operation clocks in total, that is, 6 types of 3 multiplication processes and 3 accumulation processes as PID control operations and 2 types for switching control of multiplication targets. The operation clocks clk1 to clk8 are connected to the 18th (k = 18) and subsequent output signals A18 to A25 of the delay line circuit 12.

FIG. 5 shows a timing chart of the AD conversion circuit 11 and the digital compensation circuit 21 shown in FIG.
First, when the digital error signal e [n] is output from the AD conversion circuit 11 by the latch signal A17, the digital error signal e [] is sent to the error register 23_1 of the digital compensation circuit 21 using the operation clock clk1 from the AD conversion circuit 11. n] is read, and the digital error signal e [n-1] before one switching period and the digital error signal e [n-2] two switching periods before are shifted and stored in the error registers 23_2 and 23_3, respectively. The

  Next, when the selection signal sel_mux generated by the operation clocks clk2 to clk8 becomes “01”, the MUX circuit 25 reads the digital error signal e [n−2] stored in the error register 23_3, and the MUX circuit 26 The control coefficient C stored in the register 24_3 is read, and the multiplication circuit 27 performs the multiplication process 1. Next, when the selection signal sel_acc signal generated by the clock signals clk <b> 2 to clk <b> 8 becomes “01”, the calculation result d [n−1] of the previous period held in the accumulation circuit 28 and the result of the multiplication process 1 are Accumulation process 1 is performed.

  Similarly, when the selection signal sel_mux generated by the operation clocks clk2 to clk8 becomes “10”, the MUX circuit 25 reads the digital error signal e [n−1] stored in the error register 23_2, and the MUX circuit 26 calculates the coefficient. The control coefficient B stored in the register 24_2 is read, and the multiplication circuit 27 performs the multiplication process 2. Next, when the selection signal sel_acc signal generated by the clock signals clk <b> 2 to clk <b> 8 becomes “10”, the accumulation process 2 of the result of the accumulation process 1 held in the accumulation circuit 28 and the result of the multiplication process 2 is performed.

  Similarly, when the selection signal sel_mux generated by the operation clocks clk2 to clk8 is “11”, the MUX circuit 25 reads the digital error signal e [n] stored in the error register 23_1, and the MUX circuit 26 is the coefficient register 24_1. And the multiplication circuit 27 performs a multiplication process 3. Next, when the selection signal sel_acc signal generated by the clock signals clk <b> 2 to clk <b> 8 becomes “11”, the accumulation process 3 of the result of the accumulation process 2 held in the accumulation circuit 28 and the result of the multiplication process 3 is performed. The calculation process of the PID control calculation is completed, and the duty command signal d [n] is calculated.

  The duty command signal d [n] is stored in the output register 29 at the rise of the operation clock clk8, is input to the PWM circuit 30 at the rise of the next switching cycle, and outputs a PWM signal corresponding to the duty command signal d [n]. To do.

  Although not shown in FIG. 4, the delay line circuit 12 and the delay line circuit 13 are configured such that all delay elements are reset at the rising edge of the switching cycle, and the start signal start rises at each switching cycle, The above operation is repeated.

  In the embodiment according to the present invention described above, the digital calculation is the PID control calculation represented by the equation (1), but the present invention can be similarly applied to PI (Proportional and Integral) control. The expression of the scattered digital PI control operation is generally expressed as follows.

Here, d [n-1] is a duty command signal in the previous period, e [n-1] is a digital error signal output in the previous period, and A and B control coefficients.
As shown in the above equation (2), since the PI control calculation requires two multiplications and two additions, it is only necessary to perform four calculation processes within one switching period. That is, it is possible to reduce the number of operation clocks, the error register 23_3, and the coefficient register 24_3 from the PID calculation control circuit configuration example shown in FIG.

  As described above, by using a plurality of delay signals generated by the delay line circuit that constitutes the AD conversion circuit and sequentially delayed with a constant delay time as a digital operation clock, a high-frequency oscillation circuit is not provided. Arithmetic processing can be performed within one switching cycle, the current consumption of the control circuit is reduced without increasing the circuit scale, and the power conversion efficiency of the digital control DC / DC converter can be improved.

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various improvements and modifications can be made without departing from the scope of the present invention.

DESCRIPTION OF SYMBOLS 1 Control circuit 2 Output circuit 3 Smoothing circuit 4 Load circuit 5, 6, 12, 13 Delay line circuit 7, 14 Error output circuit 8, 15 Start signal generation circuit 10, 11 AD conversion circuit 20, 21 Digital compensation circuit 22 Selection signal Generation circuit 23_1 to 23_3 Error register 24_1 to 24_3 Coefficient register 25, 26 Multiplexer (MUX) circuit 27 Multiplication circuit 28 Accumulation circuit 29 Output register 30 PWM circuit 40 Oscillation circuit 50 High frequency oscillation circuit 60 Periodic signal generation circuit 70 Counter circuit 80 Digital signal Generation circuits a1 to a8, A1 to Am, b1 to b8, B1 to Bm Delay elements and output signals A, B, C Control coefficients Ain Analog signals C0 Capacitor elements clk1 to clks Operation clocks d [n], d [ n-1], d [n-2] -Command signal Dout digital signal DP, DN drive circuit e [n], e [n-1], e [n-2] digital error signal Ib delay element bias current in delay element input signal INV inverter L inductor element o1, out Output signal of delay element QP, QP1 Switching element (PMOS)
QN, QN1, QN2 switching element (NMOS)
P1 to PN Periodic signal sel_acc Accumulation circuit selection signal sel_mux MUX circuit selection signal start Start signal td, tdelay Delay time of delay element Vb Control voltage signal and control voltage of delay element Vin Input power supply terminal and input voltage Vref Reference voltage terminal and Reference voltage Vout Output power supply terminal and output voltage

Claims (3)

A DC / DC converter that performs on / off control of a switching element according to a pulse width modulation signal for which a duty ratio is obtained by digital calculation, and converts an input voltage to a desired output voltage,
A delay element whose delay time is controlled by a reference voltage is connected in series, a first delay line circuit that sequentially delays a start signal to generate a plurality of output signals, and a delay element whose delay time is controlled by an output voltage A second delay line circuit connected in series and sequentially delaying the start signal to generate a plurality of output signals; and l (where l is a natural number) of the plurality of output signals of the first delay line circuit An error output circuit that takes in the plurality of output signals of the second delay line circuit at an output timing of a signal output to the digital signal and converts it into a digital error signal corresponding to an error voltage between the reference voltage and the output voltage; An AD conversion circuit having
A digital compensation circuit that calculates the duty ratio by performing the digital calculation using the digital error signal according to the timing at which the kth (k is a natural number) and subsequent output signals of the first delay line circuit are sequentially output. When,
A digitally controlled DC / DC converter comprising:   The first and second delay line circuits are configured by connecting a plurality of identical delay elements that generate a desired delay time according to an input control voltage, and the delay elements of the first delay line circuit are connected to each other. The number of stages of series connection is defined by the number of arithmetic processes of the digital compensation circuit, and the number of stages of series connection of the delay elements of the second delay line circuit is defined by the conversion accuracy of the AD converter circuit. The digitally controlled DC / DC converter according to claim 1.   2. The digital control DC / DC converter according to claim 1, wherein the digital compensation circuit has a function of PID calculation or PI calculation as the digital calculation, and completes the digital calculation by performing a plurality of calculation processes. .

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