JP2018100856A - Reciprocal count rate generation circuit and physical quantity sensor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reciprocal count rate generation circuit and a physical quantity sensor that have great accuracy and can reduce power consumption.SOLUTION: A reciprocal count rate generation circuit which counts a reference clock with timing stipulated by a measured signal comprises a plurality of first counters, which are electrically connected in parallel, and in which a plurality of the measured signals with different phases are input, and which detect an inversion edge representing inversion of levels of the plurality of measured signals using the reference clock, a second counter which counts the reference clock, and a reciprocal count rate generation unit, which integrates, in a section stipulated by the measured signal, a product of the detection number of the inversion edge of the measured signal in timing stipulated by the reference clock and a count rate of the second counter in the timing in order to generate a reciprocal count rate.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a reciprocal count value generation circuit and a physical quantity sensor.

  A frequency counter that generates a signal corresponding to the ratio between the frequency of a reference signal (reference clock) and the frequency of a signal under measurement is known (for example, see Patent Document 1). The apparatus described in Patent Document 1 includes a plurality of frequency delta-sigma modulation units (hereinafter referred to as “FDSM (Frequency Delta Sigma Modulator)”) electrically connected in parallel.

  In the frequency counter, when the direct counting method and the reciprocal counting method are to be realized, the direct counting method uses a reference signal as an operation clock among the reference signal and the signal under measurement. In the reciprocal counting method, on the contrary, the signal under measurement is used as an operation clock. Also, the frequency of the reference signal is compared with the frequency of the signal under measurement. If the frequency of the reference signal is lower, the direct count method is used. If the frequency of the signal under measurement is lower, the reciprocal counting method is used. By adopting, it is considered that measurement can be performed with higher resolution. Therefore, it is common to employ a method in which the signal having the lower frequency of the signal under measurement and the reference signal is used as the operation clock.

JP 2015-220552 A

  Here, assuming that the frequency of the signal under measurement is lower than the frequency of the reference signal, a reciprocal counting method is adopted, and a plurality of FDSMs electrically connected in parallel are adopted as counters of the frequency counter. To consider.

  First, there are various methods for realizing the different phase relationships in a plurality of FDSMs that are different in phase relationship between the signal under measurement and the reference signal and are electrically connected in parallel. From the viewpoint of power consumption, when a configuration in which a plurality of signals to be measured input to a plurality of FDSMs are sequentially delayed by a delay element is used, the signal is delayed by a delay element as compared to a configuration in which a reference signal is delayed. The number of times is reduced, which is preferable.

  However, in the reciprocal counting method, since the signal under measurement is used as an operation clock, there is a problem that the clock skew increases when a configuration in which the signal under measurement is delayed is employed.

  An object of the present invention is to provide a reciprocal count value generation circuit and a physical quantity sensor that have high accuracy and can reduce power consumption.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

A reciprocal count value generation circuit of the present invention is a reciprocal count value generation circuit that counts a reference clock at a timing defined by a signal under measurement.
A plurality of first signals that are electrically connected in parallel and each having a plurality of signals under different phases are input, and using the reference clock, a plurality of first edges that detect an inversion edge that represents a level inversion of the plurality of signals under measurement And the counter
A second counter for counting the reference clock;
The product of the number of inversion edges detected in the signal under measurement at the timing specified by the reference clock and the count value of the second counter at the timing is integrated in the interval specified by the signal under measurement, And a reciprocal count value generation unit for generating a reciprocal count value.

  In the present invention, since the phases of the plurality of signals under measurement are made different, the power consumption can be reduced compared to the case where the phases of the plurality of reference clocks are made different.

  In addition, by inputting signals under measurement having different phases to each first counter, it is possible to suppress quantization noise caused by idle tones, thereby improving accuracy.

  Moreover, it is possible to count without leaking without a dead period, a primary noise shaping effect is obtained, and noise can be effectively shifted to the high frequency side. Thereby, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. For example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter process can be simplified.

In the reciprocal count value generation circuit of the present invention, the first counter detects the inversion edge using a rising edge and a falling edge of the reference clock,
The second counter preferably counts the reference clock using a rising edge and a falling edge of the reference clock.

  This effectively counts twice the frequency and improves the S / N ratio.

The reciprocal count value generation circuit of the present invention includes a detection circuit that detects a rising edge and a falling edge of the reference clock and generates a pulse signal synchronized with the rising edge and the falling edge of the reference clock.
The first counter detects the inversion edge using the pulse signal,
The second counter preferably counts the reference clock using the pulse signal.

  As a result, the double frequency is effectively counted with a simple configuration, and the SN ratio can be improved.

The reciprocal count value generation circuit of the present invention includes a detection circuit that detects a rising edge and a falling edge of the reference clock and generates a pulse signal synchronized with the rising edge and the falling edge of the reference clock.
The second counter includes a first counting unit that counts rising edges of the reference clock, and a second counting unit that counts falling edges of the reference clock,
The first counter detects the inversion edge using the pulse signal,
The said 2nd counter counts the rising of the said reference clock by the said 1st counting part in the count of the said reference clock, and counts the falling of the said reference clock by the said 2nd counting part. The reciprocal count value generation circuit described.

  As a result, the double frequency is effectively counted with a simple configuration, and the SN ratio can be improved.

In the reciprocal count value generation circuit of the present invention, the number of inversion edges detected in the signal under measurement is preferably the number of rising or falling edges of the signal in the plurality of signals under measurement.
Thereby, the circuit configuration can be simplified.

  In the reciprocal count value generation circuit of the present invention, it is preferable that the number of inversion edges detected in the signal under measurement is a total value of the number of rising edges and the number of falling edges of the signals under measurement.

  Thereby, since the effective input frequency of the signal under measurement is doubled, the SN ratio can be improved by the oversampling effect.

The physical quantity sensor of the present invention includes a detection unit that detects a physical quantity related to vibration,
And a reciprocal count value generation circuit of the present invention to which the signal under measurement output from the detection unit is input.

  In the present invention, since the phases of the plurality of signals under measurement are made different, the power consumption can be reduced compared to the case where the phases of the plurality of reference clocks are made different.

  In addition, by inputting signals under measurement having different phases to each first counter, it is possible to suppress quantization noise caused by idle tones, thereby improving accuracy.

  Moreover, it is possible to count without leaking without a dead period, a primary noise shaping effect is obtained, and noise can be effectively shifted to the high frequency side. Thereby, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. For example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter process can be simplified.

In the physical quantity sensor of the present invention, the physical quantity is preferably a physical quantity related to vibration.
Thereby, a physical quantity related to vibration can be detected with high accuracy.

1 is a block diagram showing a first embodiment of a reciprocal count value generation circuit of the present invention. FIG. It is a block diagram which shows 2nd Embodiment of the reciprocal count value generation circuit of this invention. 3 is a timing chart for explaining the operation of the reciprocal count value generation circuit shown in FIG. 2. It is a block diagram which shows 3rd Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows 4th Embodiment of the reciprocal count value generation circuit of this invention. It is a block diagram which shows 5th Embodiment of the reciprocal count value generation circuit of this invention. It is a figure which shows the internal structure of the detection part in embodiment of the acceleration sensor which is an example of the physical quantity sensor of this invention. It is sectional drawing in the AA line in FIG.

  Hereinafter, a reciprocal count value generation circuit and a physical quantity sensor of the present invention will be described in detail based on embodiments shown in the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of a reciprocal count value generation circuit according to the present invention.

  In the drawings, the signal under measurement is described as “Fx” and the reference clock (reference signal) is described as “Fs” (the same applies to the drawings of other embodiments).

In the following description, a signal obtained by changing the phase of the signal under measurement is also referred to as a “signal under measurement”.
Further, the case where the signal level is “Low” is also referred to as “0”, and the case where the signal level is “High” is also referred to as “1”.

  Also, inversion of the signal, only the rising edge of the signal, that is, the case where the signal changes from “0” to “1”, and the falling edge of the signal, that is, the signal changes from “1” to “0”. Only the case, and both the rising and falling edges of the signal, that is, the case where the signal changes from “0” to “1” and the case where the signal changes from “1” to “0”. included.

  The signal inversion edge is a part representing the inversion of the signal level. As described above, the signal inversion edge represents only the rising edge of the signal and only the falling edge of the signal. , Representing both the rising and falling edges (both edges) of the signal.

  However, in the following description, each of the reference clock (reference signal) and the signal under measurement will be described by taking one of them as an example. In this embodiment, for the reference clock, the signal inversion is the rise of the signal, and for the signal under measurement, the inversion of the signal is both the rise and fall of the signal.

  The reciprocal count value generation circuit 1 (reciprocal count value generation device) shown in FIG. 1 has a value corresponding to the ratio between the frequency of the reference clock (reference signal) Fs whose frequency is known and the frequency of the signal to be measured Fx (or the above-mentioned It is a circuit (apparatus) that generates a reciprocal count value (a signal indicating a reciprocal count value), which is a value used to generate a value. The reciprocal count value generation circuit 1 employs a reciprocal count method, uses a signal under measurement as an operation clock, and the frequency of the signal under measurement is lower than the frequency of the reference clock.

  First, an outline of the reciprocal count value generation circuit 1 will be briefly described in accordance with the scope of claims, and then described in detail.

  The reciprocal count value generation circuit 1 is a circuit (reciprocal count value generation circuit) that counts a reference clock (Fs) at a timing defined by a signal under measurement (Fx). The reciprocal count value generation circuit 1 is electrically connected in parallel, and a plurality of signals under measurement (Fx) having different phases are respectively input thereto, and a plurality of signals under measurement (Fx) using a reference clock (Fs). A plurality of counters 3 as an example of a plurality of first counters for detecting an inversion edge representing inversion of the level of the counter, a counter 5 as an example of a second counter for counting a reference clock (Fs), and a reference The product of the number of inversion edges detected in the signal under test (Fx) at the timing specified by the clock (Fs) and the count value of the counter 5 at the timing is integrated in the interval specified by the signal under test (Fx). And a reciprocal count value generation unit 10 for generating a reciprocal count value. Hereinafter, “electrically connected” is also simply referred to as “connection”.

  Further, the reciprocal count value generation unit 10 includes not only a case where the products are integrated, but also a configuration capable of obtaining the same result as that obtained when the products are integrated.

  According to the reciprocal count value generation circuit 1, since the phases of the plurality of signals under measurement are made different, the power consumption can be reduced compared to the case where the phases of the plurality of reference clocks having high frequencies are made different. Further, by inputting signals under measurement having different phases to each counter 3, it is possible to suppress quantization noise caused by idle tones, thereby improving accuracy.

  Moreover, it is possible to count without leaking without a dead period, a primary noise shaping effect is obtained, and noise can be effectively shifted to the high frequency side. Thereby, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. For example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter process can be simplified.

  The number of inversion edges detected in the signal under measurement (Fx) in each counter is the total value of the number of rising edges and the number of falling edges of the signals under measurement (Fx). Thereby, since the effective input frequency of the signal under measurement is doubled, the SN ratio can be improved by the oversampling effect.

  Further, the number of inversion edges detected in the signal under measurement (Fx) in each counter is not limited to the total value, but may be the number of rising edges or the number of falling edges of the signals under measurement (Fx). Thereby, the circuit configuration can be simplified. This will be specifically described below.

  The reciprocal count value generation circuit 1 includes at least one delay element 2, a plurality of counters 3 as an example of a plurality of first counters, an adder 4, and a counter 5 as an example of a second counter. , A multiplier 6, an integrator 7, and a difference calculator 8. Each counter 3 is electrically connected in parallel. The number of delay elements 2 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is n (n is an integer of 2 or more), and the number of delay elements 2 is n-1. The upper limit of n is not particularly limited, but can be about 1000, for example.

  Each counter 3, adder 4, multiplier 6, integrator 7, and difference calculator 8 are connected in this order from the input side to the output side.

  In the present embodiment, the counter 3 includes a frequency delta sigma modulator (hereinafter referred to as “FDSM (Frequency Delta Sigma Modulator)”).

  That is, the counter 3 is synchronized with the latch 31 (first latch) that latches the signal under measurement Fx and outputs the first data in synchronization with the rising edge of the reference clock (reference signal) Fs, and with the rising edge of the reference clock. A latch 32 (second latch) that latches the first data and outputs the second data, and generates an output data by calculating an exclusive OR of the first data and the second data. And an OR circuit 33. For example, a D latch or the like can be used as each of the latch 31 and the latch 32, and the latch 31 and the latch 32 include, for example, a D flip-flop circuit.

  The delay element 2 has a function of delaying the signal under measurement, and is connected between the two counters 3 on the input side of the two adjacent counters 3. Therefore, the signal under measurement is input to the input terminal of the latch 31 of the predetermined counter 3, and the signal under measurement is delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. Similarly, the signal under measurement is further delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. As the delay element 2, an inverter is used in the present embodiment.

  A reference clock is input to the input terminal of the counter 5, and the output terminal of the counter 5 is connected to one input terminal of the multiplier 6. As the counter 5, for example, a free run counter or the like can be used. The output terminal of the adder 4 is connected to the other input terminal of the multiplier 6.

  The integrator 7 includes an adder 71 and a latch 72 electrically connected to the output side of the adder 71. As the latch 72, for example, a D latch or the like can be used.

  In addition, the difference calculator 8 includes a latch 81 and a subtracter 82. The output terminal of the latch 81 is connected to the negative input terminal of the subtractor 82. As the latch 81, for example, a D latch or the like can be used.

  The output terminal of the latch 72 of the integrator 7 is connected to the positive input terminal of the subtractor 82 of the difference calculator 8, the input terminal of the latch 81, and one input terminal of the adder 71. ing. The output terminal of the multiplier 6 is connected to the other input terminal of the adder 71.

  The adder 4, the multiplier 6, the integrator 7, and the difference calculator 8 constitute the main part of the reciprocal count value generation unit 10.

  The signal under measurement includes an input terminal of a latch 31 of a predetermined counter 3 among the plurality of counters 3, an input terminal of the first delay element 2 among the plurality of delay elements 2, and an adder of the integrator 7. 71 is input to the reset terminal 71, the clock input terminal of the latch 81 of the difference calculator 8 and the clock input terminal of the subtractor 82, respectively.

  The reference clock is input to the clock input terminal of the latch 31 and the clock input terminal of the latch 32 of each counter 3, the input terminal of the counter 5, and the clock input terminal of the latch 72 of the integrator 7, respectively. Yes.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
In the drawing, the signal under measurement is described as “Fx”, and the reference clock is described as “Fs”.

  As shown in FIG. 1, a signal under measurement includes an input terminal of a latch 31 of a predetermined counter 3 among a plurality of counters 3, an input terminal of a first delay element 2 among a plurality of delay elements 2, and integration. Is input to the reset terminal of the adder 71 of the calculator 7, the clock input terminal of the latch 81 of the difference calculator 8, and the clock input terminal of the subtractor 82.

  Further, the reference clock is input to the clock input terminal of the latch 31 and the clock input terminal of the latch 32 of each counter 3, the input terminal of the counter 5, and the clock input terminal of the latch 72 of the integrator 7, respectively. .

  The signal under measurement is delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. As a result, signals to be measured having the same frequency and different phases are input to the input terminals of the latches 31 of the counters 3.

  In each counter 3, the latch 31 latches the signal under measurement in synchronization with the rising edge of the reference clock and outputs the first data, and the latch 32 synchronizes with the rising edge of the reference clock. The data is latched and the second data is output, and the exclusive OR circuit 33 calculates the exclusive OR of the first data and the second data to generate and output the output data. That is, the exclusive OR circuit 33 outputs “0” if the number of inversions of the signal under measurement during the one-cycle transition of the reference clock is an even number, and “1” if it is an odd number. As a result, each counter 3 outputs “1” corresponding to the rise and fall of the signal under measurement, and “0” for the others.

  The signal output from each counter 3 is input to the adder 4. The adder 4 adds the numerical values indicated by the signals output from the counters 3 and outputs the result.

  The counter 5 counts the reference clock and outputs the count value of the reference clock.

  Next, the multiplier 6 multiplies the numerical value output from the adder 4 and the count value output from the counter 5 and outputs the multiplied value.

  Next, in the integrator 7, the adder 71 adds the current multiplication value and the previous multiplication value latched in the latch 72 and outputs the result. This output is the sum of the accumulated reciprocal count values.

  Next, in the difference calculator 8, the subtracter 82 subtracts the value indicated by the previous signal latched in the latch 81 from the value indicated by the signal output from the current integrator 7 and outputs the result. . This output is the sum of the reciprocal count values. When the sum of the reciprocal count values is divided by the number of counters 3, a reciprocal count value corresponding to one counter 3 is obtained.

  Here, the reciprocal count value in this embodiment is a value corresponding to the output of one of the plurality of counters 3, and the rising edge of the reference clock included between the rising edge and the falling edge of the signal under measurement. Is the number of

  The sum of the reciprocal count values is a value obtained by summing up the reciprocal count values obtained from the outputs of all the counters 3.

  In addition, the reciprocal count value in the present invention is not limited to the reciprocal count value in the narrow sense in the present embodiment, but includes a sum of reciprocal count values, an integrated reciprocal count value, an integrated sum of reciprocal count values, and the like.

  Although detailed description of subsequent operations is omitted, for example, a low-pass filter (filter) (not shown) is provided on the output side of the difference calculator 8, and the signal output from the difference calculator 8 by the low-pass filter. Process. As a result, the frequency component equal to or higher than the predetermined cutoff frequency is cut off or reduced by the low pass filter. For example, a moving average filter or the like may be provided.

  As described above, according to the reciprocal count value generation circuit 1, since the phases of the plurality of signals under measurement are made different, the power consumption is reduced compared to the case where the phases of the plurality of reference clocks having high frequencies are made different. be able to.

  Further, by inputting signals under measurement having different phases to each counter 3, quantization noise caused by idle tones can be suppressed. Thereby, accuracy can be improved.

  Moreover, it is possible to count without leaking without a dead period, a primary noise shaping effect is obtained, and noise can be effectively shifted to the high frequency side. Thereby, for example, by providing a low-pass filter on the output side, the noise component can be reduced and the accuracy can be improved. For example, when a moving average filter is provided on the output side, the configuration of the moving average filter and the moving average filter process can be simplified.

Further, modifications will be described below.
(1) The counter 3 and the counter 5 are not limited to the above-described configurations, and counters having other configurations can be used. Examples of other counters include a ripple counter.

(2) The frequency of the signal under measurement may be higher than the frequency of the reference clock.
(3) For the circuit at the subsequent stage (output side) of the difference calculator 8 (edge detection number calculation circuit), a reference clock may be used as an operation clock, or a signal under measurement may be used.

  (3-1) A reference clock is used as an operation clock for a circuit subsequent to the difference calculator 8 (edge detection number calculation circuit).

  Thereby, when the frequency of the reference clock is higher than the frequency of the signal under measurement, it is possible to finish the calculation accurately in time while dispersing the processing.

  (3-2) A signal under measurement is used as an operation clock for a circuit subsequent to the difference calculator 8 (edge detection number calculation circuit).

  Thereby, when the frequency of the reference clock is lower than the frequency of the signal under measurement, the power consumption can be reduced by pipeline processing with the low-frequency clock.

Second Embodiment
FIG. 2 is a block diagram showing a second embodiment of the reciprocal count value generation circuit of the present invention. FIG. 3 is a timing chart for explaining the operation of the reciprocal count value generation circuit shown in FIG. In FIG. 2, buses in the circuit are indicated by thick lines (the same applies to other drawings).

  In the drawings, subscripts (0, 1,..., 31) are added to “Fx” in order to distinguish the signals under measurement having different phases (the same applies to the drawings of other embodiments).

  In the drawing, a signal output from each latch 31 is described as “S”, and a subscript (0, 1,..., 31) is added to distinguish each signal (another implementation). The same applies to the drawings in the form)

  Hereinafter, the second embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  In the second embodiment, for each of the reference clock and the signal under measurement, the inversion of the signal is both the rise and fall of the signal.

  That is, in the second embodiment, the counter 3 (first counter) detects the inverted edge using the rising edge and falling edge of the reference clock (Fs), and the counter 11 (second counter) is The reference clock (Fs) is counted using the rising edge and falling edge of the reference clock (Fs).

  This effectively counts twice the frequency and improves the S / N ratio. This will be specifically described below.

  More specifically, the reciprocal count value generation circuit 1 of the second embodiment detects the rising and falling edges of the reference clock (Fs), and synchronizes with the rising and falling edges of the reference clock (Fs). The edge detection unit 9 is an example of a detection circuit that generates The counter 3 (first counter) detects the inverted edge using the pulse signal (P) generated by the edge detection unit 9, and the counter 11 (second counter) detects the edge detection unit 9 The reference clock (Fs) is counted using the pulse signal (P) generated in step (1).

  As a result, with a simple configuration, twice the frequency is effectively counted, and the SN ratio can be improved. This will be specifically described below.

  As shown in FIG. 2, the reciprocal count value generation circuit 1 according to the second embodiment includes an edge detection unit 9, a counter 11 that is an example of a second counter, at least one delay element 12, and a plurality of first count elements. A plurality of counters 3, which are an example of one counter, a plurality of latches 13, a plurality of latches 14, and an adder 4 are provided. Each counter 3 is electrically connected in parallel. The number of delay elements 12 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is 32, and the number of delay elements 12 is 31. The number of latches 13 and 14 is equal to the number of counters 3 and is 32.

  The edge detector 9, the counter 11, the latches 14, and the adder 4 are connected in this order from the input side to the output side.

  The edge detection unit 9 includes a delay element 91 and an exclusive OR circuit 92. The output terminal of the delay element 91 is connected to one input terminal of the exclusive OR circuit 92. As the delay element 91, a buffer is used in the present embodiment.

  The output terminal of the edge detector 9 is connected to the input terminal of the counter 11, and the output terminal of the counter 11 is connected to the input terminal of each latch 14. The output terminal of the latch 14 is connected to the input terminal of the adder 4. As the counter 11, for example, an up counter can be used.

  The output terminals of the edge detector 9 are connected to the clock input terminals of the latches 31 and the latches 32 of the counters 3 and the clock input terminals of the latches 13, respectively. The output terminal of each latch 13 is connected to the clock input terminal of each latch 14.

  The output terminal of each counter 3 is connected to the input terminal of the latch 13 corresponding to the counter 3. The output terminal of each latch 13 is connected to the clock input terminal of the latch 14 corresponding to the latch 13. In addition, as the latch 13 and the latch 14, for example, a D latch or the like can be used.

  The delay element 12 has a function of delaying the signal under measurement, and is connected between the two counters 3 on the input side of the two adjacent counters 3. Therefore, the signal under measurement is input to the latch 31 of the predetermined counter 3, and the signal under measurement is delayed by the delay element 12 and input to the latch 31 of another counter 3. The signal is further delayed by the delay element 12 and input to the latch 31 of another counter 3. In the present embodiment, a buffer is used as the delay element 12.

  The signal under measurement is input to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first delay element 12 among the plurality of delay elements 12. Yes.

  Further, the reference clock is supplied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. Have been entered.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 2, the signal under measurement is supplied to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first delay element 12 among the plurality of delay elements 12. Each is entered.

  Further, the reference clock is supplied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. Is entered.

  The signal under measurement is delayed by the delay element 2 and input to the input terminal of the latch 31 of another counter 3. As a result, signals under measurement having the same frequency and different phases are input to the input terminals of the latches 31 of the counters 3 (see FIG. 3).

  The edge detector 9 detects the rising edge and the falling edge of the reference clock (Fs). That is, the edge detector 9 outputs a pulse signal (P) having a pulse synchronized with the rising edge of the reference clock (Fs) and a pulse synchronized with the falling edge of the reference clock (Fs).

  The pulse signal (P) output from the edge detection unit 9 is input to the counter 11, and the counter 11 counts the pulses of the pulse signal (P) output from the edge detection unit 9, and counts the pulses. Output the value.

  The pulse signal (P) is input to the clock input terminal of the latch 31 and the clock input terminal of the latch 32 of each counter 3 and the clock input terminal of the latch 13, respectively.

  In each counter 3, the latch 31 latches the signal under measurement (Fx0 to Fx31) in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detector 9). The first data is output, the latch 32 latches the first data in synchronization with the rising edge of the reference clock and outputs the second data, and the exclusive OR circuit 33 outputs the first data and the first data. The exclusive OR of the second data is calculated to generate output data and output it. In each counter 3, the latch 31 latches the signal under measurement in synchronization with the falling edge of the reference clock and outputs the first data, and the latch 32 synchronizes with the falling edge of the reference clock. The first data is latched to output the second data, and the exclusive OR circuit 33 calculates the exclusive OR of the first data and the second data to generate and output the output data. . That is, each counter 3 outputs “1” corresponding to the rise and fall of the signal under measurement, and “0” for the others.

  The signals output from the counters 3 are latched and output by the latch 13 in synchronization with the rising edge and falling edge of the reference clock.

  The count value output from the counter 11 is input to each latch 14. Each latch 14 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

  In the example shown in FIG. 3, the count value output from the latch 14 of a predetermined counter 3 among the counters 3 is “6” at the rising edge of the signal under measurement, and “34” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “6” and “34”, and the reciprocal count value is 28 (= 34−6).

  The count value output from the latch 14 of the other counter 3 is “7” at the rising edge of the signal under measurement, and “34” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “7” and “34”, and the reciprocal count value is 27 (= 34−7).

  The count value output from the latch 14 of the other counter 3 is “7” at the rising edge of the signal under measurement, and “35” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “7” and “35”, and the reciprocal count value is 28 (= 35−7).

  The count value output from the latch 14 of the other counter 3 is “10” at the rising edge of the signal under measurement and “37” at the falling edge. That is, paying attention only to this counter 3, the integrated reciprocal count values are “10” and “37”, and the reciprocal count value is 27 (= 37−10).

  Next, the adder 4 adds the count value output from each latch 14 and outputs the result. This output is the sum of the accumulated reciprocal count values.

  Here, the reciprocal count value in this embodiment is a value corresponding to one output of the plurality of counters 3, and the rising edge of the reference clock included between the rising edge and the falling edge of the signal under measurement. And the number of falling edges.

  The sum of the reciprocal count values is a value obtained by summing the reciprocal count values obtained from the outputs of all the counters 3.

  Although a detailed description of the subsequent operation is omitted, for example, the difference between the total sum of the currently accumulated reciprocal count values and the sum of the previous accumulated reciprocal count values is obtained and output. This output is the sum of the reciprocal count values. Note that the method for obtaining the sum of the reciprocal count values is not limited to this method, and other methods may be used. Further, as described in the first embodiment, for example, a filter such as a low-pass filter or a moving average filter may be provided.

  According to the second embodiment as described above, the same effect as that of the above-described embodiment can be exhibited.

  In the second embodiment, since not only the signal under measurement but also the reference clock is defined as both the rising and falling edges of the signal, the accuracy can be further improved.

<Third Embodiment>
FIG. 4 is a block diagram showing a third embodiment of the reciprocal count value generation circuit of the present invention.

  Hereinafter, the third embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  In the third embodiment, for each of the reference clock and the signal under measurement, signal inversion is both rising and falling of the signal.

  As shown in FIG. 4, the reciprocal count value generation circuit 1 according to the third embodiment includes an edge detection unit 9, a counter 11 as an example of a second counter, a latch 18, and at least one delay element (see FIG. Not shown), a counter 30 (one shown) as an example of a plurality of first counters, a plurality of latches 17 (one shown), a counting unit 19, a multiplier 25, and a counter 20 A latch 24, a latch 26, and an adder 27.

  In this embodiment, the counter 30 is the same as the counter 3 for 32 in the second embodiment, and one counter indicates 32 counters 3 (the function of the counter 3 for 32 is provided). doing). That is, the counter 30 includes 32 latches (not shown) corresponding to the 32 latches 31 of the second embodiment, 32 latches 32 (only one is shown in the figure), and the second embodiment. 32 exclusive OR circuits 330 (only one is shown in the figure) corresponding to the 32 exclusive OR circuits 33 of the embodiment. Similarly, the latches 17 are the same as the 32 latches 14 of the second embodiment, and one latch 32 is shown (the function of the 32 latches 14 is provided). ) Therefore, the description of the counter 30 and the latch 17 is omitted.

  The counter 30, the latch 17, the counting unit 19, the multiplier 25, and the adder 27 are connected in this order from the input side to the output side. The counting unit 19 has a function of counting “1” bits.

  The edge detection unit 9, the counter 11, the latch 18, and the multiplier 25 are connected in this order from the input side to the output side.

  The counter 20 and the latch 24 are connected in this order from the input side to the output side.

  Although not shown, a plurality of (31 in this embodiment) delay elements are connected to the input side of the counter 30 as in the second embodiment.

  The counter 20 includes a latch 21, a latch 22, and an exclusive OR circuit 23, and is configured in the same manner as the counter 3 in the first and second embodiments. The signal under measurement is input to the input terminal of the latch 21 of the counter 20.

  Further, as the latch 17, the latch 18, the latch 21, the latch 22, and the latch 26, for example, a D latch or the like can be used.

  Further, the output terminals of the edge detector 9 are clock input terminals of latches not shown and clock inputs of the latches 32 corresponding to the latches 31 of the counter 30 of the second embodiment, input terminals of the counter 11, and A clock input terminal of the latch 18, a clock input terminal of the latch 26, a clock input terminal of each latch 17, a clock input terminal of the latch 21 of the counter 20 and a clock input terminal of the latch 22, and a clock input terminal of the latch 24 Are connected to each other.

  The output terminal of the counter 11 is connected to the input terminal of the latch 18. The output terminal of the latch 18 is connected to one input terminal of the multiplier 25. Further, the output terminal of the counting unit 19 is connected to the other input terminal of the multiplier 25.

  The output terminal of the multiplier 25 is connected to one input terminal of the adder 27. The output terminal of the adder 27 is connected to the input terminal of the latch 26, and the output terminal of the latch 26 is connected to the other input terminal of the adder 27. The output terminal of the latch 24 is connected to the reset terminal of the adder 27.

  Further, the reference clock is supplied to the input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9 and the other input terminal of the exclusive OR circuit 92, respectively. Have been entered.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 4, the process is the same as in the second embodiment until halfway, and “1” is output from the exclusive OR circuit 330 of the counter 30 corresponding to the rise and fall of the signal under measurement. Otherwise, “0” is output.

  The pulse signal output from the edge detection unit 9 and having a pulse synchronized with the rising edge of the reference clock and a pulse synchronized with the falling edge of the reference clock is supplied to the counter 11, the clock input terminal of the latch 18, and the latch 26. Are input to a clock input terminal of the latch 17, a clock input terminal of the latch 17, a clock input terminal of the latch 21 of the counter 20, a clock input terminal of the latch 22, and a clock input terminal of the latch 24, respectively.

  The signals output from the counter 30 are latched and output by the latch 17 in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detector 9).

  Next, the counting unit 19 counts “1” bits of the signal output from the counter 30. That is, the number of “1” s of the signal output from the counter 30 at each count value of the counter 11 is counted.

  The count value output from the counter 11 is input to the latch 18. The latch 18 latches and outputs the count value in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9).

  Next, the multiplier 25 multiplies the numerical value output from the counting unit 19 and the count value of the counter 11 output from the latch 18 and outputs the multiplied value. This multiplication value is input to one input terminal of the adder 27.

  In the counter 20, the latch 21 latches the signal under measurement in synchronization with the rising edge of the reference clock (the rising edge of the pulse of the pulse signal output from the edge detection unit 9) and outputs the first data, The latch 22 latches the first data in synchronization with the rising edge and falling edge of the reference clock and outputs the second data, and the exclusive OR circuit 23 outputs the first data and the second data. An exclusive OR is calculated and output data is generated and output. That is, the counter 20 outputs “1” corresponding to the rise and fall of the signal under measurement, and outputs “0” for the others.

  The signal output from the counter 20 is latched by the latch 24 in synchronization with the rising edge and falling edge of the reference clock, output, and input to the reset terminal of the adder 27.

  The multiplication value output from the multiplier 25 is input to one input terminal of the adder 27. The output of the adder 27 is latched and output by the latch 26 in synchronization with the rising edge and falling edge of the reference clock, and input to the other input terminal of the adder 27.

  The adder 27 adds the current multiplication value and the previous multiplication value latched in the latch 26 and outputs the result. This output is the sum of the accumulated reciprocal count values.

  Although a detailed description of the subsequent operation is omitted, for example, the difference between the total sum of the currently accumulated reciprocal count values and the sum of the previous accumulated reciprocal count values is obtained and output. This output is the sum of the reciprocal count values. Note that the method for obtaining the sum of the reciprocal count values is not limited to this method, and other methods may be used. Further, as described in the first embodiment, for example, a filter such as a low-pass filter or a moving average filter may be provided.

  According to the third embodiment as described above, the same effects as those of the above-described embodiment can be exhibited.

<Fourth embodiment>
FIG. 5 is a block diagram showing a fourth embodiment of the reciprocal count value generation circuit of the present invention.

  Hereinafter, the fourth embodiment will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  In the fourth embodiment, for each of the reference clock and the signal under measurement, signal inversion is both rising and falling of the signal.

  A reciprocal count value generation circuit 1 according to the fourth embodiment detects a rising edge and a falling edge of a reference clock (Fs) and generates a pulse signal (P) synchronized with the rising edge and the falling edge of the reference clock (Fs). An edge detection unit 9 is provided as an example. The counter 110, which is an example of the second counter, includes a first count unit 111 that counts the rising edge of the reference clock (Fs) and a second counting unit 112 that counts the falling edge of the reference clock (Fs). And. The counter 3 (first counter) detects the inverted edge using the pulse signal (P) detected by the edge detection unit 9, and the counter 110 (second counter) detects the reference clock (Fs). ), The first count unit 111 counts the rising edge of the reference clock (Fs), and the second counting unit 112 counts the falling edge of the reference clock (Fs).

  As a result, the double frequency is effectively counted with a simple configuration, and the SN ratio can be improved. This will be specifically described below.

  As shown in FIG. 5, the reciprocal count value generation circuit 1 according to the fourth embodiment includes an edge detection unit 9, a counter 110 that is an example of a second counter, at least one delay element 12, and a plurality of first count elements. 1 includes a plurality of counters 3, a plurality of latches 13, a plurality of latches 141, a plurality of latches 142, and an adder 4. Each counter 3 is electrically connected in parallel. The number of delay elements 12 is one less than the number of counters 3. In the present embodiment, the number of counters 3 is 32, and the number of delay elements 12 is 31. The number of latches 13, latch 141, and latch 142 is 32, which is equal to the number of counters 3, respectively.

  Note that the edge detection unit 9, each delay element 12, and each counter 3 are the same as those in the second embodiment, and a description thereof will be omitted.

  The counter 110 includes a first count unit 111, a second count unit 112, and an inverter 113 (phase inversion circuit). The second count unit 112 is connected to the output side of the inverter 113. And the series circuit comprised by the inverter 113 and the 2nd count part 112 and the 1st count part 111 are connected in parallel. The output terminal of the first count unit 111 is connected to the input terminal of each latch 141, and the output terminal of the second count unit 112 is connected to the input terminal of each latch 142. The output terminal of each latch 141 and the output terminal of each latch 142 are connected to the input terminal of the adder 4, respectively. Further, as the first count unit 111 and the second count unit 112, for example, an up counter can be used, for example.

  The output terminals of the edge detector 9 are connected to the clock input terminals of the latches 31 and the latches 32 of the counters 3 and the clock input terminals of the latches 13, respectively.

  The output terminal of each counter 3 is connected to the input terminal of the latch 13 corresponding to the counter 3. The output terminal of each latch 13 is connected to the clock input terminal of the latch 141 corresponding to the latch 13 and the clock input terminal of the latch 142, respectively. Further, as the latch 13, the latch 141, and the latch 142, for example, a D latch or the like can be used.

  The signal under measurement is input to the input terminal of the latch 31 of the predetermined counter 3 among the plurality of counters 3 and the input terminal of the first delay element 12 among the plurality of delay elements 12. Yes.

  The reference clock includes an input terminal of the delay element 91 connected to one input terminal of the exclusive OR circuit 92 of the edge detection unit 9, the other input terminal of the exclusive OR circuit 92, and a counter 110. Are input to the input terminal of the first count unit 111 and the input terminal of the inverter 113, respectively.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 5, the process is the same as in the second embodiment until halfway, and each counter 3 outputs “1” corresponding to the rise and fall of the signal under measurement, and the others are “0”. Is output.

  On the other hand, the reference clock is input to the counter 110. The first count unit 111 counts the rising edge of the reference clock and outputs the count value of the rising edge of the reference clock.

  The phase of the reference clock is inverted by the inverter 113 and input to the second count unit 112. The second count unit 112 counts the rising edge of the inverted reference clock obtained by inverting the phase of the reference clock, that is, the falling edge of the reference clock, and outputs the count value of the falling edge of the reference clock.

  The signals output from each counter 3 are latched and output by the latch 13 in synchronization with the rising edge and falling edge of the reference clock.

  Further, the count value output from the first count unit 111 is input to each latch 141. Each latch 141 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

  Similarly, the count value output from the second count unit 112 is input to each latch 142. Each latch 142 latches and outputs the count value in synchronization with the rising edge of the signal output from the latch 13.

  Next, the adder 4 adds the count value output from each latch 141 and each latch 142, and outputs it. This output is the sum of the accumulated reciprocal count values.

  Although a detailed description of the subsequent operation is omitted, for example, the difference between the total sum of the currently accumulated reciprocal count values and the sum of the previous accumulated reciprocal count values is obtained and output. This output is the sum of the reciprocal count values. Note that the method for obtaining the sum of the reciprocal count values is not limited to this method, and other methods may be used. Further, as described in the first embodiment, for example, a filter such as a low-pass filter or a moving average filter may be provided.

  According to the fourth embodiment as described above, the same effect as that of the above-described embodiment can be exhibited.

<Fifth Embodiment>
FIG. 6 is a block diagram showing a fifth embodiment of the reciprocal count value generation circuit of the present invention.

  Hereinafter, the fifth embodiment will be described with a focus on differences from the above-described embodiments, and description of similar matters will be omitted.

  In the fifth embodiment, for each of the reference clock and the signal under measurement, signal inversion is both rising and falling of the signal.

  As shown in FIG. 6, the reciprocal count value generation circuit 1 of the fifth embodiment includes an inverter 115 (phase inverting circuit), a counter 110 that is an example of a second counter, at least one delay element 12, A plurality of counters 280, which are an example of a plurality of first counters, a plurality of latches 141, a plurality of latches 142, an adder 4, and a difference calculator 8 are provided. Each counter 280 is electrically connected in parallel. Further, the number of delay elements 12 is one less than the number of counters 280. In this embodiment, the number of counters 280 is 32, and the number of delay elements 12 is 31. The number of latches 141 and 142 is equal to the number of counters 280 and is 32.

  The counter 280 includes a first count unit 28, a second count unit 29, a latch 131, a latch 132, and an OR circuit 133.

  The first count unit 28 includes latches 281 and 282 and an exclusive OR circuit 283. The second count unit 29 includes latches 291 and 292 and an exclusive OR circuit 293. The first count unit 28 and the second count unit 29 are the same as those of the counter 3 of the first, second, and fourth embodiments, respectively, and thus description thereof is omitted.

  The output terminal of the first count unit 28 is connected to the input terminal of the latch 131, and the output terminal of the second count unit 29 is connected to the input terminal of the latch 132. Note that the series circuit constituted by the first count unit 28 and the latch 131 and the series circuit constituted by the second count unit 29 and the latch 132 are electrically connected in parallel. The output terminal of the latch 131 and the output terminal of the latch 132 are connected to the input terminal of the OR circuit 133, respectively. Further, as the latch 131 and the latch 132, for example, a D latch or the like can be used. Since the delay element 12 is the same as the delay element 12 of the fourth embodiment, description thereof is omitted.

  The counter 110 includes a first count unit 111 and a second count unit 112 connected in parallel to each other. The output terminal of the first count unit 111 is connected to the input terminal of each latch 141, and the output terminal of the second count unit 112 is connected to the input terminal of each latch 142. The output terminal of each latch 141 and the output terminal of each latch 142 are connected to the input terminal of the adder 4, respectively. Further, as the first count unit 111 and the second count unit 112, for example, an up counter can be used, for example. Moreover, as each latch 141 and each latch 142, D latch etc. can be used, for example.

  In addition, the difference calculator 8 includes a latch 81 and a subtracter 82. The output terminal of the latch 81 is connected to the negative input terminal of the subtractor 82. As the latch 81, for example, a D latch or the like can be used.

  The output terminal of the adder 4 is connected to the plus-side input terminal of the subtractor 82 of the difference calculator 8 and the input terminal of the latch 81, respectively.

  The output terminal of the inverter 115 includes the input terminal of the second count unit 112 of the counter 110, the clock input terminal of the latch 281 of the first count unit 28 of each counter 280, the clock input terminal of the latch 282, and the latch 131. Are respectively connected to the clock input terminals.

  Among the counters 280, the counter 280 to which the signal under measurement that is not delayed by the delay element 12 is input has a clock input terminal of the corresponding latch 141 and a clock input terminal of the corresponding latch 142. Are connected to the clock input terminal of the latch 81 of the difference calculator 8 and the clock input terminal of the subtractor 82, respectively. For the other counters 280, the output terminals are connected to the clock input terminal of the corresponding latch 141 and the clock input terminal of the corresponding latch 142, respectively. Instead of the counter 280, the output terminal of another counter 280 may be connected to the clock input terminal of the latch 81 of the difference calculator 8 and the clock input terminal of the subtractor 82. Further, as each of the latch 141, each of the latch 142, and the latch 81, for example, a D latch or the like can be used.

  In addition, the signal under measurement is input to the input terminal of the latch 281 and the input terminal of the latch 291 of the predetermined counter 280 of the plurality of counters 280 and to the input terminal of the first delay element 12 of the plurality of delay elements 12. , Respectively.

  The reference clock includes an input terminal of the first count unit 111 of the counter 110, an input terminal of the inverter 115, a clock input terminal of the latch 291 of the second count unit 29 of each counter 280, and a clock input of the latch 292. And the clock input terminal of the latch 132, respectively.

Next, the operation of the reciprocal count value generation circuit 1 will be described.
As shown in FIG. 6, the reference clock is input to the first count unit 111 and the inverter 115 of the counter 110, respectively. The first count unit 111 counts the rising edge of the reference clock and outputs the count value of the rising edge of the reference clock.

  The phase of the reference clock is inverted by the inverter 115 and input to the second count unit 112. The second count unit 112 counts the rising edge of the inverted reference clock obtained by inverting the phase of the reference clock, that is, the falling edge of the reference clock, and outputs the count value of the falling edge of the reference clock.

  Further, from the first count section 28 of each counter 280, “1” is output corresponding to the rise and fall of the signal under measurement, and “0” is output otherwise.

  Further, from the second count section 29 of each counter 280, “1” is output corresponding to the rise and fall of the signal under measurement, and “0” is output otherwise.

  However, in the first count unit 28 and the second count unit 29, the signal input to the clock input terminal is inverted in the phase of the reference clock by the inverter 115 in the first count unit 28. This is an inverted reference clock, and the second count unit 29 is different in that it is a reference clock.

  Further, the signals output from the first count unit 28 of each counter 280 are respectively supplied to the rising edge of the inverted reference clock obtained by inverting the phase of the reference clock by the inverter 115 by the latch 131, that is, the reference clock. It is latched and output in synchronization with the falling edge.

  The signals output from the second count unit 29 of each counter 280 are latched and output by the latch 132 in synchronization with the rising edge of the reference clock.

  Next, in each counter 280, the signal output from the latch 131 and the signal output from the latch 132 are respectively input to the OR circuit 133, and predetermined OR processing is performed in the OR circuit 133 for output. Is done.

  Further, the count value output from the first count unit 111 is input to each latch 141. Each latch 141 latches and outputs the count value in synchronization with the rising edge of the signal output from the corresponding counter 280.

  Similarly, the count value output from the second count unit 112 is input to each latch 142. Each latch 142 latches and outputs the count value in synchronization with the rising edge of the signal output from the corresponding counter 280.

  Next, the adder 4 adds the count value output from each latch 141 and each latch 142, and outputs it. This output is the sum of the accumulated reciprocal count values.

  Next, in the difference calculator 8, the subtracter 82 subtracts the value indicated by the previous signal latched in the latch 81 from the value indicated by the signal output from the current adder 4 and outputs the result. . This output is the sum of the reciprocal count values.

  According to the fifth embodiment as described above, the same effect as that of the above-described embodiment can be exhibited.

  Further, since the edge detection unit 9 (analog element) is not used, a more stable operation is possible.

<Embodiment of physical quantity sensor>
FIG. 7 is a diagram showing an internal structure of a detection unit in an embodiment of an acceleration sensor which is an example of the physical quantity sensor of the present invention. 8 is a cross-sectional view taken along line AA in FIG.

  Hereinafter, an embodiment of an acceleration sensor, which is an example of a physical quantity sensor, will be described with a focus on differences from the above-described embodiment, and description of similar matters will be omitted.

  As shown in FIGS. 7 and 8, the acceleration sensor 100 (physical quantity sensor) of the present embodiment includes a detection unit 200 that detects acceleration, which is an example of a physical quantity related to vibration, and a signal under measurement output from the detection unit 200. Is input to the reciprocal count value generation circuit 1 (see FIG. 1 and the like for the reciprocal count value generation circuit 1). The detection unit 200 and the reciprocal count value generation circuit 1 are electrically connected. Since the reciprocal count value generation circuit 1 has already been described, the description thereof is omitted.

  The detection unit 200 includes a flat base portion 210, a substantially rectangular flat plate-shaped movable portion 212 connected to the base portion 210 via a joint portion 211, and a physical quantity spanned between the base portion 210 and the movable portion 212. An acceleration detection element 213 that is an example of the detection element, and a package 220 that houses at least each of the above-described components are provided.

  The detection unit 200 is driven by a drive signal applied to the excitation electrode of the acceleration detection element 213 via the external terminals 227 and 228, the internal terminals 224 and 225, the external connection terminals 214e and 214f, the connection terminals 210b and 210c, and the like. The vibrating beams 213a and 213b of the acceleration detecting element 213 oscillate (resonate) at a predetermined frequency. And the detection part 200 outputs the resonance frequency of the acceleration detection element 213 which changes according to the applied acceleration as a to-be-measured signal (detection signal).

  This signal under measurement is input to the reciprocal count value generation circuit 1, and the reciprocal count value generation circuit 1 operates as described in the above embodiment.

  Moreover, although the number of the detection parts 200 is one in this embodiment, it is not restricted to this, For example, two or three may be sufficient. By providing three detection units 200 and making the detection axes of each detection unit 200 orthogonal (cross) each other, it is possible to detect the acceleration in the axial direction of each of the three detection axes orthogonal to each other.

  Even with the acceleration sensor 100 as described above, the reciprocal count value generation circuit 1 included in the acceleration sensor 100 can exhibit the same effects as those of the above-described embodiment. Thereby, the acceleration sensor 100 can detect the acceleration with high accuracy.

  As described above, the reciprocal count value generation circuit and the physical quantity sensor according to the present invention have been described based on the illustrated embodiment. However, the present invention is not limited to this, and the configuration of each unit may be any arbitrary function having the same function. It can be replaced with that of the configuration. Moreover, other arbitrary components may be added.

  Further, the present invention may be a combination of any two or more configurations (features) of the above embodiments.

  In the above embodiment, the acceleration sensor is described as an example of the physical quantity sensor. However, in the present invention, if the physical quantity sensor can detect a change in physical quantity as a frequency change, In addition, for example, a mass sensor, an ultrasonic sensor, an angular acceleration sensor, a capacitance sensor, and the like can be given.

  The physical quantity sensor of the present invention includes, for example, various electronic devices such as an inclinometer, a seismometer, a navigation device, an attitude control device, a game controller, a mobile phone, a smartphone, a digital still camera, and various moving bodies such as an automobile. It is possible to apply to. That is, according to the present invention, it is possible to provide an electronic device including the physical quantity sensor of the present invention, a moving object including the physical quantity sensor of the present invention, and the like.

  DESCRIPTION OF SYMBOLS 1 ... Reciprocal count value generation circuit, 2 ... Delay element, 3 ... Counter, 4 ... Adder, 5 ... Counter, 6 ... Multiplier, 7 ... Integrator, 8 ... Difference calculator, 9 ... Edge detection part, 10 ... Reciprocal count value generation unit, 11 ... counter, 12 ... delay element, 13 ... latch, 14 ... latch, 17 ... latch, 18 ... latch, 19 ... counting unit, 20 ... counter, 21 ... latch, 22 ... latch, 23 ... Exclusive OR circuit, 24 ... latch, 25 ... multiplier, 26 ... latch, 27 ... adder, 28 ... first count unit, 29 ... second count unit, 30 ... counter, 31 ... latch, 32 ... Latch, 33 ... exclusive OR circuit, 71 ... adder, 72 ... latch, 81 ... latch, 82 ... subtractor, 91 ... delay element, 92 ... exclusive OR circuit, 100 ... acceleration sensor, 110 Counter 111 111 First count 112 112 Second count 113 Inverter 115 Inverter 131 Latch 132 Latch 133 OR circuit 141 Latch 142 Latch 200 Detection 210, base portion, 210b, connection terminal, 210c, connection terminal, 211, joint portion, 212, movable portion, 213, acceleration detecting element, 213a, vibration beam, 213b, vibration beam, 214e, external connection terminal, 214f. ... External connection terminal, 220 ... Package, 224 ... Internal terminal, 225 ... Internal terminal, 227 ... External terminal, 228 ... External terminal, 280 ... Counter, 281 ... Latch, 282 ... Latch, 283 ... Exclusive OR circuit, 291 ... Latch, 292 ... Latch, 293 ... Exclusive OR circuit, 330 ... Exclusive OR circuit

Claims (8)

A reciprocal count value generation circuit that counts a reference clock at a timing defined by a signal under measurement,
A plurality of first signals that are electrically connected in parallel and each having a plurality of signals under different phases are input, and using the reference clock, a plurality of first edges that detect an inversion edge representing an inversion of the levels of the plurality of signals under measurement are detected. And the counter
A second counter for counting the reference clock;
The product of the number of inversion edges detected in the signal under measurement at the timing specified by the reference clock and the count value of the second counter at the timing is integrated in the interval specified by the signal under measurement, A reciprocal count value generation circuit comprising: a reciprocal count value generation unit that generates a reciprocal count value. The first counter detects the inversion edge using a rising edge and a falling edge of the reference clock,
The reciprocal count value generation circuit according to claim 1, wherein the second counter counts the reference clock using a rising edge and a falling edge of the reference clock. A detection circuit for detecting a rising edge and a falling edge of the reference clock and generating a pulse signal synchronized with the rising edge and the falling edge of the reference clock;
The first counter detects the inversion edge using the pulse signal,
The reciprocal count value generation circuit according to claim 1, wherein the second counter counts the reference clock using the pulse signal. A detection circuit for detecting a rising edge and a falling edge of the reference clock and generating a pulse signal synchronized with the rising edge and the falling edge of the reference clock;
The second counter includes a first counting unit that counts rising edges of the reference clock, and a second counting unit that counts falling edges of the reference clock,
The first counter detects the inversion edge using the pulse signal,
The said 2nd counter counts the rising of the said reference clock by the said 1st counting part in the count of the said reference clock, and counts the falling of the said reference clock by the said 2nd counting part. The reciprocal count value generation circuit described.   2. The reciprocal count value generation circuit according to claim 1, wherein the number of inversion edges detected in the signal under measurement is the number of rising or falling edges of the signal in the plurality of signals under measurement.   5. The reciprocal count value generation circuit according to claim 1, wherein the number of inversion edges detected in the signal under measurement is a total value of the number of rising edges and the number of falling edges of the plurality of signals under measurement. . A detection unit for detecting a physical quantity;
A physical quantity sensor comprising: the reciprocal count value generation circuit according to claim 1, to which the signal under measurement output from the detection unit is input.   The physical quantity sensor according to claim 7, wherein the physical quantity is a physical quantity related to vibration.

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