JP6759636B2 - Frequency delta-sigma modulation signal output device - Google Patents

Description

The present invention relates to a frequency delta-sigma modulated signal output device.

A frequency delta-sigma-modulated signal output device that generates a frequency delta-sigma-modulated signal indicating the ratio of the frequency of the reference signal to the frequency of the signal to be measured is known.

The frequency delta sigma modulation signal output device has a frequency delta sigma modulator (hereinafter referred to as "Frequency Delta Sigma Modulator"), and the FDSM modifies the signal to be measured with frequency delta sigma using a reference signal. Then, a frequency delta-sigma modulated signal is generated and output.

In this frequency delta-sigma modulation signal output device, periodic quantization noise called idle tone is generated. That is, the output signal of the FDSM is a signal in which an idle tone is superimposed on the baseband signal component of the signal to be measured.

Patent Document 1 discloses a frequency delta sigma modulated signal output device including a plurality of FDSMs connected in parallel in order to suppress an idle tone in a frequency delta sigma modulated signal. In this device, the idle tones superimposed on the output signals of each FDSM are temporally dispersed by inputting the measured signals out of phase with each other to the plurality of FDSMs. As a result, the quantization noise caused by the idle tone superimposed on the frequency delta-sigma modulation signal can be suppressed, and the SN ratio of the frequency delta-sigma modulation signal can be improved.

JP-A-2015-220552

However, in the apparatus described in Patent Document 1, since a circuit is configured by using a plurality of FDSMs connected in parallel, there is a problem that the circuit scale becomes large and the circuit configuration becomes complicated. Further, although the accuracy is improved by increasing the operating frequency, there is a problem that the power consumption is increased by increasing the operating frequency.

An object of the present invention is to provide a frequency delta-sigma modulated signal output device capable of suppressing quantization noise caused by idle tones with a simple and small-scale circuit.

The present invention has been made to solve at least a part of the above-mentioned problems, and can be realized as the following forms or application examples.

The frequency delta sigma modulated signal output device of the present invention is a frequency delta sigma modulated signal output device that modulates the signal to be measured with frequency delta sigma based on a reference signal and outputs a frequency delta sigma modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
It is characterized by including a calculation unit that generates a frequency delta-sigma modulation signal based on the count value of the count unit.

As a result, the quantization noise caused by the idle tone can be suppressed. Further, the circuit scale can be reduced and the circuit configuration can be simplified as compared with the frequency delta-sigma modulation signal output device using a plurality of FDSMs connected in parallel.

In the frequency delta-sigma modulated signal output device of the present invention, the counting unit includes a clock signal generating unit that generates the clock signal and a clock signal generating unit.
It is preferable to include a counter for counting the clock signal.

This makes it possible to generate a high frequency clock signal, which increases the effective number of parallels and improves the signal-to-noise ratio of the frequency delta-sigma modulated signal.

In the frequency delta-sigma modulated signal output device of the present invention, it is preferable that the clock signal generation unit includes a voltage controlled oscillator or an inverter oscillator.

This makes it possible to generate a high frequency clock signal, which increases the effective number of parallels and improves the signal-to-noise ratio of the frequency delta-sigma modulated signal.

Further, when the inverter oscillator is used, the start and stop of the operation can be easily controlled, and the error of each timing can be reduced.

In the frequency delta-sigma modulated signal output device of the present invention, the calculation unit subtracts the count value from the number of the clock signals included in the period of the predetermined cycle of the reference signal, and based on the subtracted value, the calculation unit It is preferable to generate a frequency delta-sigma modulated signal.
This makes it possible to appropriately generate a frequency delta-sigma modulated signal.

In the frequency delta sigma modulation signal output device of the present invention, the calculation unit subtracts the count value from the number of the clock signals included in the period of the predetermined cycle of the reference signal, and the subtracted value and the counting unit. It is preferable to generate the frequency delta sigma modulation signal based on the count value of.
This makes it possible to appropriately generate a frequency delta-sigma modulated signal.

The frequency delta-sigma modulated signal output device of the present invention preferably includes a storage unit that stores the number of the clock signals included in the period of the predetermined period of the reference signal.

This makes it possible to use information on the number of clock signals included in a predetermined period of the reference signal when necessary.

In the frequency delta-sigma modulation signal output device of the present invention, the clock signal is counted in a predetermined period of the reference signal, and the number stored in the storage unit is updated to the number obtained by the counting. It is preferable to do so.

As a result, even if the frequency of the clock signal is unknown or the frequency of the clock signal fluctuates due to the influence of temperature characteristics or the like, an appropriate value can be obtained as the number of clock signals included in the period of the predetermined period of the reference signal. ..

In the frequency delta-sigma modulated signal output device of the present invention, the frequency of the clock signal is preferably an integral multiple of 2 or more of the frequency of the reference signal.

As a result, the clock signal and the reference signal are synchronized, and an appropriate count value of the clock signal can be obtained.

Further, if it is known how many times the frequency of the clock signal is a reference signal, it is not necessary to obtain the number of clock signals included in the period of the predetermined period of the reference signal.

In the frequency delta-sigma modulated signal output device of the present invention, when the frequency of the signal to be measured is twice the frequency of the reference signal or less, it is preferable to operate the counting unit only during the measurement period.

As a result, the clock signal is counted by the counting unit only during the measurement period, not during the entire period, so that power consumption can be reduced.

In the frequency delta sigma modulated signal output device of the present invention, when twice the frequency of the signal to be measured is larger than the frequency of the reference signal, the following equation (1) is satisfied and the frequency division ratio is an integer of 2 or more. It is provided with a frequency dividing signal generation unit that obtains m and divides the frequency of the signal to be measured by 1 / m to generate a frequency dividing signal.
Using the frequency division signal as the signal to be measured,
It is preferable to operate the counting unit only during the measurement period.
(Frequency of the signal to be measured) x 2 / m ≤ frequency of the reference signal ... (1)

This makes it possible to generate a frequency delta-sigma modulated signal even when the frequency of the signal to be measured is twice as high as the frequency of the reference signal.

Further, since the clock signal is counted by the counting unit only during the measurement period, not during the entire period, the power consumption can be reduced.

In the frequency delta-sigma modulated signal output device of the present invention, the frequency division signal generation unit generates a plurality of frequency division signals having different phases from each other in synchronization with the timing of inversion of the signal to be measured.
It is preferable to use the plurality of divided signals as the signal to be measured.

As a result, the information contained in the signal to be measured can be used without leakage, so that the SN ratio of the frequency delta-sigma modulated signal can be improved.

In the frequency delta-sigma modulated signal output device of the present invention, it is preferable that the counting unit resets the count value and restarts the counting of the clock signal when the count value reaches a predetermined value.

As a result, the calculation unit can perform processing with an algorithm different from the case where the count value is not reset within the measurement period. Thereby, for example, the same effect as when a plurality of frequency division signals are used as the measurement signal can be obtained without using the plurality of frequency division signals. As a result, the number of arithmetic processes can be reduced as compared with the case where a plurality of frequency division signals are used as the signal to be measured.

In the frequency delta-sigma modulation signal output device of the present invention, it is preferable to provide a filter after the calculation unit.

As a result, the noise component contained in the frequency delta-sigma modulated signal can be removed, and the SN ratio of the frequency delta-sigma modulated signal can be improved.

It is a block diagram which shows 1st Embodiment of the frequency delta sigma modulation signal output apparatus of this invention. It is a timing chart for demonstrating the operation of the frequency delta sigma modulation signal output apparatus shown in FIG. It is a block diagram which shows the 2nd Embodiment of the frequency delta sigma modulation signal output apparatus of this invention. It is a timing chart for demonstrating the operation of the frequency delta sigma modulation signal output apparatus shown in FIG. It is a timing chart for demonstrating the operation of the frequency delta sigma modulation signal output apparatus shown in FIG. It is a timing chart for demonstrating the operation of the 3rd Embodiment of the frequency delta sigma modulation signal output apparatus of this invention. It is a block diagram which shows the 4th Embodiment of the frequency delta sigma modulation signal output apparatus of this invention. It is a block diagram which shows the conventional frequency delta sigma modulation signal output device.

Hereinafter, the frequency delta-sigma modulated signal output device of the present invention will be described in detail based on the preferred embodiments shown in the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a first embodiment of the frequency delta-sigma modulated signal output device of the present invention. FIG. 2 is a timing chart for explaining the operation of the frequency delta-sigma modulation signal output device shown in FIG. FIG. 8 is a block diagram showing a conventional frequency delta-sigma modulated signal output device.

In the following description, the case where the signal level is "low" is also referred to as "0", and the case where the signal level is "high" is also referred to as "1".

Further, inversion of the signal is performed when the signal rises, that is, when the signal changes from "0" to "1", and when the signal falls, that is, when the signal changes from "1" to "0". Both rising and falling, that is, both when the signal goes from "0" to "1" and when the signal goes from "1" to "0". However, in the following description, one of these will be taken as an example for explanation.

The frequency delta sigma modulation signal output device 1 shown in FIG. 1 frequency-delta sigma-modulates the measured signal based on a reference signal having a known frequency, and corresponds to the ratio of the frequency of the reference signal to the frequency of the measured signal. It is a device that outputs a frequency delta sigma modulated signal.

As shown in FIG. 1, the frequency delta sigma modulation signal output device 1 includes a timing generation unit 2 that specifies a measurement period between the time of inversion of the signal to be measured and the time of inversion of the reference signal, and a clock in the measurement period. It includes a count unit 3 that counts signals, a calculation unit 4 that generates a frequency delta sigma modulation signal based on the count value of the clock signal of the count unit 3, and a storage unit 5 that stores each information. The timing generation unit 2, the counting unit 3, and the calculation unit 4 are connected in this order toward the output side.

The storage unit 5 stores the number of clock signals included in the period of a predetermined cycle of the reference signal, and in the present embodiment, the number of clock signals included in the period of one cycle of the reference signal.

Thereby, when necessary, the information on the number of clock signals included in the period of one cycle of the reference signal can be used.

The number of clock signals is the number of pulses of the clock signal. Further, from the viewpoint of improving accuracy, the higher the frequency of the clock signal, the more preferable.

Further, the number of the clock signals stored in the storage unit 5 is updated as necessary. That is, in the period of a predetermined cycle of the reference signal, in the present embodiment, the clock signal is counted in the period of one cycle of the reference signal, and the number stored in the storage unit 5 is updated to the number obtained by the counting. To do.

As a result, even if the frequency of the clock signal is unknown or the frequency of the clock signal fluctuates due to the influence of temperature characteristics or the like, an appropriate value can be obtained as the number of clock signals included in the period of the predetermined period of the reference signal. ..

Further, the counting unit 3 includes a clock signal generation unit 31 that generates a clock signal and a counter 32 that counts the clock signal output from the clock signal generation unit 31.

The clock signal generation unit 31 is not particularly limited as long as it has a function of generating a clock signal, and is, for example, a voltage controlled oscillator (VCO), an inverter oscillator, or a circuit including a voltage controlled oscillator or an inverter oscillator. Can be mentioned.

This makes it possible to generate a high frequency clock signal, which increases the effective number of parallels and improves the signal-to-noise ratio of the frequency delta-sigma modulated signal.

Further, when the inverter oscillator is used, the start and stop of the operation can be easily controlled, and the error of each timing can be reduced.

In this frequency delta sigma modulation signal output device 1, a device equivalent to the frequency delta sigma modulation signal output device 100 shown in FIG. 8 is realized by a circuit and an algorithm. The frequency delta-sigma modulation signal output device 100 is configured to temporally disperse the idle tone superimposed on the output signal OUT of each FDSM 102, for example, by inputting signals to be measured that are out of phase with each other. .. Therefore, the frequency delta-sigma modulation signal output device 1 can similarly suppress the quantization noise caused by the idle tone.

Hereinafter, the frequency delta-sigma modulation signal output device 100 will be briefly described.
The frequency delta sigma modulation signal output device 100 includes a phase adjusting unit 101, a plurality of frequency delta sigma modulation units 102 (hereinafter referred to as "FDSM (Frequency Delta Sigma Modulator)") connected in parallel, and an adder 103. It has.

The phase adjusting unit 101 relatively adjusts the phase of the measured signal Fx and the reference signal Fc, and n sets of the measured signal and the reference signal (Fx1, Fc1), (Fx2, Fc2), ... (Fxj, Fcj), ... (Fxn, Fcn) are generated. Note that n is an integer of 2 or more. Further, j is an arbitrary number from 1 to n, but in FIG. 8, an arbitrary number of 3 or more and n-1 or less is imaged. Further, in the following, as an example, a case where the reference signal is common and the phases of the signals to be measured are out of phase with each other will be described as an example.

The FDSM 102 is an FDSM having a bitstream configuration, that is, an FDSM that outputs an output signal in a bitstream format.

The FDSM 102 latches the first data d1 in synchronization with the rising edge of the reference signal Fcj and the first data d1 in synchronization with the rising edge of the reference signal Fcj. A second latch 123 that outputs the second data d2, and an exclusive logical sum circuit 125 that calculates the exclusive logical sum of the first data d1 and the second data d2 to generate an output signal OUT (output data). To be equipped. In this example, it is assumed that the latch operation is performed at the rising edge, but the latch operation may be performed at the falling edge or both the rising edge and the falling edge. The first latch 122 and the second latch 123 are composed of, for example, a D flip-flop circuit or the like.

The FDSM 102 holds the “high” or “low” state of the measured signal Fxj by the first latch 122, and outputs the even / odd number of inversions during one cycle of the reference signal Fcj as an output signal OUT. That is, if the number of inversions is even, "0" is output, and if it is odd, "1" is output.

The adder 103 adds the output signals OUT of each FDSM 102 and outputs them as a frequency delta-sigma modulation signal.

Next, the principle of the frequency delta-sigma modulation signal output device 1 will be described.
Further, here, a circuit equivalent to the case where the number of parallel FDSM 102s in the frequency delta-sigma modulation signal output device 100 is 16, that is, the case where 16 FDSM 102s are connected in parallel will be described as an example. The number of clock signals included in one cycle of the reference signal is equal to the number of parallel signals. Therefore, 16 clock signals are included in the period of one cycle of the reference signal. Further, it is preferable that the reference signal and the clock signal are synchronized.

As shown in FIG. 2, the 16 measured signals Fx1 to Fx16, which are out of phase with each other, are out of timing by one clock signal that switches from "0" to "1". The timing of switching from "1" to "0" is also the same.

First, a case where a frequency delta-sigma modulation signal is generated based on the measured signal Fx1 input to the first FDSM 102 will be described.

In this case, as the measurement period A, a period from the rise C of the reference signal to the rise of the measured signal Fx1, that is, the switching D of the measured signal Fx1 from "0" to "1" is set. ..

The number of "0" s of the measured signal Fx1 in the measurement period A is five. In this case, "0" surrounded by a quadrangle at the rising edge C of the reference signal is not included. This also applies to the following description.

The value (difference) obtained by subtracting "5", which is the number of "0" of the signal to be measured Fx1 in the measurement period A, from "16", which is the number of parallels, is "11".

The number of "1" s of the measured signal Fx1 in the measurement period B described later is 11. In this case, "1" surrounded by a quadrangle at the rising edge E of the reference signal is included. This also applies to the following description.

On the other hand, among the output signal OUTs output from the 16 FDSM 102s, the number of output signal OUTs having a value of "1" is "11". This "11" is a value indicated by the frequency delta-sigma modulation signal output from the frequency delta-sigma modulation signal output device 100, and corresponds to the subtracted value "11".

Further, among the output signal OUTs output from the 16 FDSM 102s at the next latch timing, the number of output signal OUTs having a value of "1" is "5". This "5" is a value shown next to the above-mentioned "11" of the frequency delta-sigma modulation signal output from the frequency delta-sigma modulation signal output device 100, and is the number of "0" of the measured signal Fx1 in the measurement period A. Consistent with "5".

Further, in the other period of one cycle of the signal to be measured, the next frequency delta sigma modulation signal output from the frequency delta sigma modulation signal output device 100 is “0”.

The same applies to the case where the frequency delta-sigma modulation signal is generated based on the measured signal Fx1 input to the other 15 FDSM 102s.

Therefore, in the frequency delta sigma modulation signal output device 1, the counting unit 3 counts the number of “0” of the measured signal Fx1 in the measurement period A, and the calculation unit 4 counts from “16” to the counting unit 3. By subtracting the values, the number of output signal OUTs whose value is "1" is obtained from each output signal OUT output from the 16 FDSM 102s. That is, the subtracted value is taken as the value indicated by the frequency delta-sigma modulated signal.

Further, the count value of the count unit 3 is set to the value indicated by the frequency delta-sigma modulation signal next. Further, in the other period of one cycle of the signal to be measured, the value indicated by the frequency delta-sigma modulated signal is set to "0".

The calculation unit 4 is the count value of the clock signal of the counting unit 3 from the number of the clock signals included in the period of the predetermined cycle of the reference signal, and in the present embodiment, the number of clock signals included in the period of one cycle of the reference signal. Is subtracted. Then, a frequency delta-sigma modulation signal is generated based on the subtracted value and the count value of the clock signal of the counting unit 3.
This makes it possible to appropriately generate a frequency delta-sigma modulated signal.

Further, in the frequency delta sigma modulation signal output device 1, the counting unit 3 may be operated at least during the measurement period A, but in the present embodiment, when the frequency of the signal to be measured is twice the frequency of the reference signal or less. Operates the counting unit 3 only during the measurement period A, which is an example of the measurement period.

As a result, the operation of the counting unit 3 can be stopped in the measurement period B instead of counting the entire period, so that the power consumption can be reduced.

Next, the operation of the frequency delta-sigma modulation signal output device 1 will be described.
First, the signal to be measured is input to the timing generation unit 2. Further, the reference signal is input to the timing generation unit 2, the counting unit 3, and the calculation unit 4.

In the timing generation unit 2, the measurement period A is specified. Further, the timing generation unit 2 outputs a signal in which the clock signal generation unit 31 is in the operating state to the clock signal generation unit 31 only during the measurement period A. As a result, the clock signal generation unit 31 operates only in the measurement period A and generates a clock signal.

Then, the counter 32 counts the clock signal, and the count value of the counter 32 is input to the calculation unit 4.

The calculation unit 4 includes the number of clock signals included in the period of the predetermined period of the reference signal, and in the present embodiment, the number of clock signals included in the period of one period of the reference signal "16" to the clock of the counting unit 3. Subtract the signal count value. Then, a frequency delta-sigma modulation signal is generated based on the subtracted value and the count value of the counting unit 3.

The frequency delta-sigma modulation signal may be generated based on one of the subtracted value and the count value of the counting unit 3.

Specifically, the calculation unit 4 outputs the subtracted value as a value indicated by the frequency delta-sigma modulated signal, and outputs the count value of the counting unit 3 as a value indicated by the frequency delta-sigma modulated signal next. .. Further, the calculation unit 4 outputs "0" as a value indicated by the frequency delta-sigma modulation signal in the other period of one cycle of the signal to be measured. This makes it possible to appropriately generate a frequency delta-sigma modulated signal.

In this way, the frequency delta-sigma modulation signal output device 1 generates and outputs the frequency delta-sigma modulation signal.

Here, in the above description, the measurement period A is set, but the measurement period A is not limited to this. For example, as the measurement period B, a period from the rising edge D of the measured signal Fx1 to the rising edge E of the reference signal may be set. Good.

In this case, the counting unit 3 counts the number of “1” of the measured signal Fx1 in the measurement period B. Then, the count value of the count unit 3 is set to the value indicated by the frequency delta-sigma modulation signal.

Further, in the calculation unit 4, by subtracting the count value of the count unit 3 from "16", the output signal OUT whose value is "0" among the output signal OUTs output from the 16 FDSM 102s Find the number. Then, the subtracted value is set as the value indicated by the frequency delta-sigma modulation signal. Further, in the other period of one cycle of the signal to be measured, the value indicated by the frequency delta-sigma modulated signal is set to "0".

As described above, according to the frequency delta-sigma modulation signal output device 1, the quantization noise caused by the idle tone can be suppressed.

Further, the circuit scale can be reduced and the circuit configuration can be simplified as compared with the frequency delta-sigma modulation signal output device using a plurality of FDSMs connected in parallel.

Further, in a frequency delta-sigma modulation signal output device using a plurality of FDSMs connected in parallel, increasing the number of FDSMs further increases the circuit scale and further complicates the circuit configuration. However, this frequency delta-sigma modulation In the signal output device 1, it is not necessary to change the circuit configuration, and it can be dealt with by changing the algorithm. Therefore, the frequency delta-sigma modulation signal output device 1 has a wide range of versatility and can appropriately handle various cases.

Further, since the clock signal is counted by the counting unit 3 only during a predetermined measurement period instead of the entire period, power consumption can be reduced.

Here, as another configuration example, there is a configuration in which the frequency of the clock signal is an integral multiple of 2 or more of the frequency of the reference signal. In this case, the clock signal and the reference signal are synchronized. In order to generate the clock signal and the reference signal having such a relationship, for example, the reference signal is multiplied to obtain the clock signal, or the clock signal is divided to obtain the reference signal.

As a result, an appropriate count value of the clock signal can be obtained. Further, if it is known how many times the frequency of the clock signal is the frequency of the reference signal, it is not necessary to obtain the number of clock signals included in the period of one cycle of the reference signal.

<Second Embodiment>
FIG. 3 is a block diagram showing a second embodiment of the frequency delta-sigma modulated signal output device of the present invention. 4 and 5 are timing charts for explaining the operation of the frequency delta-sigma modulated signal output device shown in FIG. 3, respectively.

Hereinafter, the second embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same matters will be omitted.

As shown in FIG. 3, the frequency delta-sigma modulation signal output device 1 of the second embodiment further includes a frequency dividing signal generation unit 6.

In this frequency delta sigma modulation signal output device 1, when twice the frequency of the signal to be measured is larger than the frequency of the reference signal, the frequency dividing signal generator 6 satisfies the following equation (1) and is an integer of 2 or more. The frequency division ratio m is obtained, and the frequency of the signal to be measured is divided by 1 / m to generate a frequency division signal.

(Frequency of the signal to be measured) x 2 / m ≤ frequency of the reference signal ... (1)
Further, the frequency dividing signal is used as the signal to be measured. In addition, the counting unit 3 is operated only during the measurement period.

This makes it possible to generate a frequency delta-sigma modulated signal even when the frequency of the signal to be measured is twice as high as the frequency of the reference signal.

Further, since the clock signal is counted by the counting unit 3 only during the measurement period, not during the entire period, the power consumption can be reduced.

Further, in the present embodiment, the frequency dividing signal generation unit 6 generates a plurality of divided signals having different phases from each other in synchronization with the timing of inversion of the signal to be measured. Then, the plurality of frequency division signals are used as the signals to be measured.

As a result, the information contained in the signal to be measured can be used without leakage, so that the SN ratio of the frequency delta-sigma modulated signal can be improved.

Hereinafter, in the present embodiment, the case where the frequency division ratio m is 10 will be described as an example. The first to tenth frequency division signals are as shown in FIG. 4, respectively.

The frequency delta-sigma modulation signal output device 1 performs the same processing as the measured signal of the first embodiment for the first to tenth frequency division signals.

Then, as shown in FIG. 5, the calculation unit 4 obtains the sum of the values of the first to tenth frequency division signals at the rise of the reference signal, that is, the latch timing, and generates the frequency delta-sigma modulation signal. In the illustrated configuration, the values of the frequency delta-sigma modulated signal are "36", "36", and "37".

The second embodiment as described above can also exert the same effect as the first embodiment described above.

In the present embodiment, all 10 frequency dividing signals are used, but the present invention is not limited to this, and a part of the 10 frequency dividing signals, that is, at least one may be used. Good.

<Third Embodiment>
FIG. 6 is a timing chart for explaining the operation of the third embodiment of the frequency delta-sigma modulation signal output device of the present invention.

Hereinafter, the third embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same matters will be omitted.

The frequency delta-sigma modulation signal output device 1 of the third embodiment realizes a device equivalent to that of the second embodiment without using a plurality of divided signals.

In this case, the difference from the above-described embodiment is that when the count value reaches a predetermined value, the count unit 3 resets the count value and restarts the count of the clock signal.

Specifically, as shown in FIG. 6, the counting unit 3 continuously counts the clock signals, counts the clock signals from "0" to "15", and after "15", counts the clock signals. , Reset to "0" and restart. The count of "0" after "15" is also performed at the same timing as the count of other values.

As a result, by performing the processing described later in the calculation unit 4, the same effect as that of the second embodiment can be obtained without using a plurality of frequency division signals. As a result, the number of arithmetic processes can be reduced as compared with the second embodiment.

Next, the operation of the frequency delta-sigma modulation signal output device 1 will be described.
First, the count value of the clock signal is reset to "0" at each of the rising edge F of the reference signal and the latch timings Q, R, S, and T. The latch timings Q, R, S, and T are the rising edges of the reference signal, respectively.

Further, in the range shown in the figure, the measurement period is the period between the rising edge F of the reference signal and the rising edge H of the measured signal and the period between the rising edge F of the reference signal and the falling edge I of the measured signal. The period between the rising edge F of the reference signal and the rising edge J of the measured signal, the period between the rising edge F of the reference signal and the falling edge K of the measured signal, and the rising edge F of the reference signal and the measured signal. The period between the rising edge L of the reference signal, the rising edge F of the reference signal and the falling edge M of the measured signal, the period between the rising edge F of the reference signal and the rising edge N of the measured signal, and the reference. The period is set between the rising edge F of the signal and the falling edge O of the measured signal, and the period between the rising edge F of the reference signal and the rising edge P of the measured signal.

First, the count value n of the clock signal at the fall G of the signal to be measured is "0", the count value n of the clock signal at the rise H is "7", and the count value n of the clock signal at the fall I Is "14", the clock signal count value n at the rising edge J is "5", the clock signal count value n at the falling edge K is "12", and the clock signal count value n at the rising edge L is , "3", the clock signal count value n at the falling edge M is "10", the clock signal count value n at the rising edge N is "1", and the clock signal count value n at the falling edge O is , "8", the count value n of the clock signal at the rising edge P is "15".

As a result, in the calculation unit 4, based on the information that the count value n is "0", "16-0", that is, "16" is associated with the latch timing Q next to the rising edge F of the reference signal. Further, in the next latch timing R, "0" is associated.

Similarly, based on the information that the count value n is "7", "16-7", that is, "9" is associated with the latch timing Q, and "7" corresponds to the latch timing R. Can be attached.

Similarly, based on the information that the count value n is "14", "16-14", that is, "2" is associated with the latch timing Q, and "14" corresponds to the latch timing R. Can be attached.

Similarly, based on the information that the count value n is "5", "16-5", that is, "11" is associated with the latch timing R, and "5" corresponds to the latch timing S. Can be attached.

Similarly, based on the information that the count value n is "12", "16-12", that is, "4" is associated with the latch timing R, and "12" corresponds to the latch timing S. Can be attached.

Similarly, based on the information that the count value n is "3", "16-3", that is, "13" is associated with the latch timing S, and "3" corresponds to the latch timing T. Can be attached.

Similarly, based on the information that the count value n is "10", "16-10", that is, "6" is associated with the latch timing S, and "10" corresponds to the latch timing T. Can be attached. Hereinafter, the description will be omitted.

Then, the calculation unit 4 adds the associated values at each latch timing.
First, at the latch timing Q, the information is insufficient, and the value of the frequency delta-sigma modulated signal output is undefined.

Further, in the latch timing R, "0", "7", "14", "11" and "4" are added, and the added value "36" becomes the value of the frequency delta-sigma modulation signal.

Further, in the latch timing S, "5", "12", "13" and "6" are added, and the added value "36" becomes the value of the frequency delta-sigma modulation signal. Hereinafter, the description will be omitted.

In this way, the frequency delta-sigma modulation signal output device 1 generates and outputs the frequency delta-sigma modulation signal.

The third embodiment as described above can also exert the same effect as the first embodiment described above.

<Fourth Embodiment>
FIG. 7 is a block diagram showing a fourth embodiment of the frequency delta-sigma modulated signal output device of the present invention.

Hereinafter, the fourth embodiment will be described mainly on the differences from the above-described embodiment, and the description of the same matters will be omitted.

As shown in FIG. 7, the frequency delta-sigma modulation signal output device 1 of the fourth embodiment includes a timing generation unit 2, a counting unit 3, a calculation unit 4, a storage unit 5, and a low-pass filter which is an example of a filter. It is equipped with 7. The timing generation unit 2, the counting unit 3, the calculation unit 4, and the low-pass filter 7 are connected in this order toward the output side. That is, the frequency delta-sigma modulation signal output device 1 includes a low-pass filter 7 after the calculation unit 4.

The low-pass filter 7 is not particularly limited, and examples thereof include a general low-pass filter, a lag lead filter, and a lag filter.

The cutoff frequency (cutoff frequency) of the low-pass filter is not particularly limited and is appropriately set according to various conditions.

The low-pass filter 7 cuts off or reduces frequency components above a predetermined cutoff frequency. As a result, the high frequency noise component included in the frequency delta sigma modulated signal can be removed, and the SN ratio of the frequency delta sigma modulated signal can be improved.

Further, the frequency of the reference signal is set higher than the cutoff frequency of the low-pass filter 7. Thereby, the SN ratio of the frequency delta-sigma modulated signal can be improved.

The fourth embodiment as described above can also exert the same effect as the first embodiment described above.
The fourth embodiment can be applied to each of the other embodiments.

The frequency delta-sigma modulated signal output device of the present invention has been described above based on the illustrated embodiment, but the present invention is not limited to this, and the configuration of each part is an arbitrary configuration having the same function. Can be replaced with one. Further, any other constituents may be added.

1 ... Frequency delta sigma modulation signal output device, 2 ... Timing generation unit, 3 ... Count unit, 4 ... Calculation unit, 5 ... Storage unit, 6 ... Divided signal generation unit, 7 ... Low pass filter, 31 ... Clock signal generation unit , 32 ... counter, 100 ... frequency delta sigma modulation signal output device, 101 ... phase adjuster, 102 ... FDSM, 103 ... adder, 122 ... first latch, 123 ... second latch, 125 ... exclusive logic sum circuit, A ... Measurement period, B ... Measurement period, C ... Rise, D ... Rise, E ... Rise, F ... Rise, Fc ... Reference signal, Fcj ... Reference signal, Fcn ... Reference signal, Fx ... Measured signal, Fx1 ... Measurement signal, Fx2 ... Measured signal, Fx3 ... Measured signal, Fx4 ... Measured signal, Fx5 ... Measured signal, Fx6 ... Measured signal, Fx7 ... Measured signal, Fx8 ... Measured signal, Fx9 ... Measured signal , Fx10 ... signal to be measured, Fx11 ... signal to be measured, Fx12 ... signal to be measured, Fx13 ... signal to be measured, Fx14 ... signal to be measured, Fx15 ... signal to be measured, Fx16 ... signal to be measured, Fxj ... signal to be measured, Fxn ... signal to be measured, G ... falling, I ... falling, K ... falling, M ... falling, O ... falling, H ... rising, J ... rising, L ... rising, N ... rising, P ... rising, OUT ... output signal, Q ... latch timing, R ... latch timing, S ... latch timing, T ... latch timing, d1 ... first data, d2 ... second data, m ... frequency division ratio, n ... count value

Claims (12)

A frequency delta-sigma modulation signal output device that frequency-delta-sigma-modulates a signal to be measured based on a reference signal having a known period and outputs a frequency delta-sigma-modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
A calculation unit that subtracts the count value of the count unit from the number of clock signals included in a period that is a natural number multiple of one cycle of the reference signal, and generates the frequency delta sigma modulation signal based on the subtracted value. A frequency delta sigma modulated signal output device, characterized in that it comprises. A frequency delta-sigma modulation signal output device that frequency-delta-sigma-modulates a signal to be measured based on a reference signal having a known period and outputs a frequency delta-sigma-modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
The count value of the count unit is subtracted from the number of clock signals included in a period that is a natural number multiple of one cycle of the reference signal, and the frequency delta sigma modulation is performed based on the subtracted value and the count value. A frequency delta sigma modulated signal output device comprising: a calculation unit for generating a signal. A frequency delta-sigma modulation signal output device that frequency-delta-sigma-modulates a signal to be measured based on a reference signal having a known period and outputs a frequency delta-sigma-modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
A storage unit that stores the number of clock signals included in a period that is a natural number multiple of one cycle of the reference signal.
A frequency delta-sigma modulation signal output device including a calculation unit that generates the frequency delta-sigma modulation signal based on the count value of the count unit. The frequency according to claim 3, wherein the clock signal is counted in a period of one cycle of the reference signal, which is a natural number, and the number stored in the storage unit is updated to the number obtained by counting. Delta-sigma modulated signal output device. A frequency delta-sigma modulation signal output device that frequency-delta-sigma-modulates a signal to be measured based on a reference signal having a known period and outputs a frequency delta-sigma-modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
An arithmetic unit that generates the frequency delta-sigma modulation signal based on the count value of the count unit, and
A frequency delta-sigma modulation signal output device including a filter arranged after the arithmetic unit. The frequency delta-sigma modulation signal output device according to any one of claims 1 to 5, wherein when the count value reaches a predetermined value, the count unit resets the count value and restarts counting of the clock signal. .. A frequency delta-sigma modulation signal output device that frequency-delta-sigma-modulates a signal to be measured based on a reference signal having a known period and outputs a frequency delta-sigma-modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
A calculation unit that generates the frequency delta-sigma modulation signal based on the count value of the count unit is provided.
A frequency delta-sigma modulated signal output device, characterized in that the counting unit is operated only during the measurement period when twice the frequency of the signal to be measured is equal to or lower than the frequency of the reference signal. A frequency delta-sigma modulation signal output device that frequency-delta-sigma-modulates a signal to be measured based on a reference signal having a known period and outputs a frequency delta-sigma-modulated signal.
A timing generator that specifies a measurement period between the time when the measured signal is inverted and the time when the reference signal is inverted, and
In the measurement period, the counting unit that counts the clock signal and
A calculation unit that generates the frequency delta-sigma modulation signal based on the count value of the count unit is provided.
When twice the frequency of the signal to be measured is larger than the frequency of the reference signal, the following equation (1) is satisfied, the frequency division ratio m which is an integer of 2 or more is obtained, and the frequency of the signal to be measured is set to 1. It is equipped with a frequency dividing signal generator that divides the frequency to / m and generates a frequency dividing signal.
Using the frequency division signal as the signal to be measured,
A frequency delta-sigma modulated signal output device characterized in that the counting unit is operated only during the measurement period.
(Frequency of the signal to be measured) x 2 / m ≤ frequency of the reference signal ... (1) The frequency dividing signal generation unit generates a plurality of the frequency dividing signals having different phases from each other in synchronization with the timing of inversion of the signal to be measured.
The frequency delta-sigma modulation signal output device according to claim 8, wherein the plurality of divided signals are used as the signal to be measured. The counting unit includes a clock signal generating unit that generates the clock signal and a clock signal generating unit.
The frequency delta-sigma modulated signal output device according to any one of claims 1 to 9, further comprising a counter for counting the clock signal. The frequency delta-sigma modulated signal output device according to claim 10, wherein the clock signal generation unit includes a voltage controlled oscillator or an inverter oscillator. The frequency delta-sigma modulated signal output device according to any one of claims 1 to 11, wherein the frequency of the clock signal is an integral multiple of 2 or more of the frequency of the reference signal.

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